Abstract: The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

Abstract: One aspect of the present disclosure relates to a novel sensor mechanism based on the aggregation of nanoparticles for target molecule detection and quantification. The nanoparticles that can be used include non-conducting polymers and conducting polymers such as polyaniline, polypyrrole and polythiophene derived nanofibers. Embodiments can include covalently functionalized nanoparticles with probes for target molecules, a biosensor where functionalized nanoparticles bind to one another upon presence of target to generate a visible conjugate induced aggregation, a biosensor wherein nanoparticles bind spontaneously in the presence of target molecules such as biological molecules, cells and biological markers.

Abstract: Disclosed herein is a sequential functionalization methodology for the covalent modification of nanotubes with between one and four repeat units of a polymer. Covalent attachment of oligomer units to the surface of nanotubes results in oligomer units forming an organic sheath around the nanotubes, polymer-functionalized-nanotubes (P-NTs). P-NTs possess chemical functionality identical to that of the functionalizing polymer, and thus provide nanoscale scaffolds which may be readily dispersed within a monomer solution and participate in the polymerization reaction to form a polymer-nanotube/polymer composite. Formation of polymer in the presence of P-NTs leads to a uniform dispersion of nanotubes within the polymer matrix, in contrast to aggregated masses of nanotubes in the case of pristine-NTs.

Abstract: An x-ray window comprising a plurality of thin film layers stacked together, including a thin film layer and a polymer layer. The thin film layer can be diamond, graphene, diamond-like carbon, beryllium, and combinations thereof. The polymer layer can be a polyimide. A boron hydride layer may also be included.

Abstract: A membrane electrode assembly including an anode that incorporates a porous support and a hydrogen permeable metal thin film disposed on the porous support; a cathode; and a proton conductive solid oxide electrolyte membrane disposed between the anode and the cathode.

Abstract: Carbon nanoflakes, methods of making the nanoflakes, and applications of the carbon nanoflakes are provided. In some embodiments, the carbon nanoflakes are carbon nanosheets, which are less than 2 nm thick. The carbon nanoflakes may be made using RF-PECVD. Carbon nanoflakes may be useful as field emitters, for hydrogen storage applications, for sensors, and as catalyst supports.

Abstract: Certain spin-coatable liquids and application techniques are described, which can be used to form nanotube films or fabrics of controlled properties. A spin-coatable liquid for formation of a nanotube film includes a liquid medium containing a controlled concentration of purified nanotubes, wherein the controlled concentration is sufficient to form a nanotube fabric or film of preselected density and uniformity, and wherein the spin-coatable liquid comprises less than 1×1018 atoms/cm3 of metal impurities. The spin-coatable liquid is substantially free of particle impurities having a diameter of greater than about 500 nm.

Abstract: A method of creating graphene comprising the steps of dispersing graphene oxide into water to form a dispersion. Where the method further comprises adding a solvent to the dispersion to form a solution, and controlling a temperature of the solution to form graphene.

Abstract: A yellow Light Emitting Diode (LED) with a peak emission wavelength in the range 560-580 nm is disclosed. The LED is grown on one or more III-nitride-based semipolar planes and an active layer of the LED is composed of indium (In) containing single or multi-quantum well structures. The LED quantum wells have a thickness in the range 2-7 nm. A multi-color LED or white LED comprised of at least one semipolar yellow LED is also disclosed.

Abstract: Disclosed herein is a metal-air battery having a cathode, an anode, and an electrolyte. The cathode has a cathode current collector and a composite of a porous carbon structure and a pseudocapacitive coating. The coating does not completely fill or obstruct a majority of the pores, and the pores can be exposed to a gas. The electrolyte is in contact with the anode and permeates the composite without completely filling or obstructing a majority of the pores.

Abstract: A three-dimensional electrode array for use in electrochemical cells, fuel cells, capacitors, supercapacitors, flow batteries, metal-air batteries and semi-solid batteries.

Abstract: The present invention relates to negative-electrode active material for rechargeable lithium battery comprising: a core comprising material capable of doping and dedoping lithium; and, a carbon layer formed on the surface of the core, wherein the carbon layer has a three dimensional porous structure comprising nanopores regularly ordered on the carbon layer with a pore wall of specific thickness placed therebetween.

Abstract: Electrodes for lithium batteries are coated via an atomic layer deposition process. The coatings can be applied to the assembled electrodes, or in some cases to particles of electrode material prior to assembling the particles into an electrode. The coatings can be as thin as 2 ?ngstroms thick. The coating provides for a stable electrode. Batteries containing the electrodes tend to exhibit high cycling capacities.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 ?m to 5 ?m. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode.

Abstract: The invention provides a method for forming a light emitting device. A first substrate is provided. A plurality of patterned masks is formed on the first substrate, or on a semiconductor epitaxial layer grown on the first substrate, or the first substrate is etched to form a plurality of trenches, followed by performing an epitaxial lateral overgrowth process to grow an epitaxy layer over the first substrate. A light emitting structure is formed on the epitaxy layer. A first electrode layer is formed on the light emitting structure. The light emitting structure is wafer bonded to a second substrate. A photoelectrochemical etching process is performed to lift off the first substrate from the epitaxy layer.

Abstract: A reflector structure suitable for extreme ultraviolet lithography (EUVL) is provided. The structure comprises a substrate having a multi-layer reflector. A capping layer is formed over the multi-layer reflector to prevent oxidation. In an embodiment, the capping layer is formed of an inert oxide, such as Al2O3, HfO2, ZrO2, Ta2O5, Y2O3-stabilized ZrO2, or the like. The capping layer may be formed by reactive sputtering in an oxygen environment, by non-reactive sputtering wherein the materials are sputtered directly from the respective oxide targets, by non-reactive sputtering of the metallic layer followed by full or partial oxidation (e.g., by natural oxidation, by oxidation in oxygen-containing plasmas, by oxidation in ozone (O3), or the like), by atomic level deposition (e.g., ALCVD), or the like.

Abstract: A semiconductor optical amplifier includes an n-type semiconductor layer, a p-type semiconductor layer an active layer provided between the n-type semiconductor layer and the p-type semiconductor layer, the active layer transmitting an optical signal and a current-injection part that injects current into the active layer via the n-type semiconductor layer and the p-type semiconductor layer, the active layer including a first active layer that includes AlGaInAs, and a second active layer that includes GaInAsP, the second active layer provided closer to an output side than the first active layer, and the first active layer and the second active layer being butt-jointed.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer.

Abstract: Nanolithography and nanoscale device features based on a self-assembled film comprising an ABC triblock terpolymer disposed on a substrate surface are provided. The self-assembled film has a controlled pattern of features over the entire film. Each feature comprises block A, block B, or block C of the ABC triblock terpolymer. One or more blocks (A, B, or C) of the self-assembled film can be transformed by, for example, being removed, to provide a particular pattern geometry for nanolithography.

Abstract: Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.

Abstract: A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.

Abstract: A semiconductor light emitting device includes a structural body, a first electrode layer, an intermediate layer and a second electrode layer. The structural body includes a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type, and a light emitting layer between the first and second semiconductor layers. The first electrode layer is on a side of the second semiconductor layer opposite to the first semiconductor layer; the first electrode layer includes a metal portion and plural opening portions piercing the metal portion along a direction from the first semiconductor layer toward the second semiconductor layer, having an equivalent circular diameter not less than 10 nanometers and not more than 5 micrometers. The intermediate layer is between the first and second semiconductor layers in ohmic contact with the second semiconductor layer. The second electrode layer is electrically connected to the first semiconductor layer.

Abstract: A semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a light emitting layer, a first electrode layer, and a second electrode layer. The light emitting layer is between the first semiconductor layer and the second semiconductor layer. The first electrode layer is on a side of the second semiconductor layer opposite to the first semiconductor layer. The first electrode layer includes a metal portion and a plurality of opening portions piercing the metal portion along a direction from the first semiconductor layer toward the second semiconductor layer. The metal portion contacts the second semiconductor layer. An equivalent circular diameter of a configuration of the opening portions as viewed along the direction is not less than 10 nanometers and not more than 5 micrometers.

Abstract: A catalyst structure for an electrochemical cell includes a catalyst support structure, catalyst particles and an outer carbide film The catalyst particles are deposited on the catalyst support structure. The outer carbide film is formed on the catalyst support structure. The outer carbide film surrounds the catalyst particles.

Abstract: An electrode composite material includes an individual electrode active material particle and a protective film coated on a surface of the particle. A composition of the protective film is at least one of AlxMyPO4 and AlxMy(PO3)3, M represents at least one chemical element selected from the group consisting of Cr, Zn, Mg, Zr, Mo, V, Nb, and Ta, and a valence of M is represented by k, wherein 0<x<1, 0<y<1, and 3x+ky=3.

Abstract: When forming complex gate electrode structures, a double exposure double etch strategy may be applied, in which the lateral distance in the width direction of the gate electrode structures may be defined prior to forming mask features for defining the gate length. In this case, the width dimension of the mask opening may be adjusted on the basis of a spacer element, which may thus allow providing a reduced dimension on the basis of well-established process techniques.

Abstract: An all-solid battery includes: a positive electrode active material layer that includes a positive electrode active material; a negative electrode active material layer that includes a negative electrode active material; and a solid electrolyte layer that is formed between the positive electrode active material layer and the negative electrode active material layer. The positive electrode active material layer or the solid electrolyte layer further includes a solid electrolyte material. A reaction suppressing portion is formed at an interface between the positive electrode active material and the solid electrolyte material. The reaction suppressing portion is a chemical compound that includes a cation portion formed of a metal element and a polyanion portion formed of a central element that forms covalent bonds with a plurality of oxygen elements.

Abstract: A DRAM cell structure with extended trench, the DRAM cell structure comprises: a NMOS transistor and a trench capacitor connected with the source electrode of the NMOS transistor; the trench capacitor comprises: a semiconductor substrate; a multilayer structure as the bottom plate of the trench capacitor, formed over the semiconductor substrate, which is composed of N-type SiGe layers and N-type Si layers arranged alternatively; a trench formed through the multilayer structure deeply into the semiconductor substrate, whose sidewall cross section is serrate-shaped; a dielectric layer formed on the inner face of the trench; a first polycrystalline silicon layer which is filled in the trench as the top plate of the trench capacitor; and a P-type Si layer formed over the multilayer structure. The present invention adopts doping epitaxial growth process to fabricate a multilayer structure composed of N-type SiGe layers and N-type Si layers arranged alternatively as the bottom plate of the trench capacitor.

Abstract: The present disclosure relates to a method for synthesizing gold nanoparticles. In the method, a gold ion containing solution and a carboxylic acid including at least two carboxyl groups are provided. The gold ion containing solution and the carboxylic acid are mixed to form a mixture. The mixture is reacted at a reaction temperature of about 20° C. to about 60° C.

Abstract: The invention provides methods functionalizing a planar surface of a graphene layer, a graphite surface, or microelectronic structure. The graphene layer, graphite surface, or planar microelectronic structure surface is exposed to at least one vapor including at least one functionalization species that non-covalently bonds to the graphene layer, a graphite surface, or planar microelectronic surface while providing a functionalization layer of chemically functional groups, to produce a functionalized graphene layer, graphite surface, or planar microelectronic surface.

Abstract: In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer.

Abstract: A light emitting diode (LED) having a p-type layer having a thickness of 100 nm or less, an n-type layer, and an active layer, positioned between the p-type layer and the n-type layer, for emitting light, wherein the LED does not include a separate electron blocking layer.

Abstract: Disclosed is a light emitting structure comprising a first semiconductor layer, a substrate, a reflection electrode disposed on the substrate, a light transmitting electrode disposed on the reflection electrode, and a light emitting structure disposed on the light transmitting electrode, the light emitting structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first and second semiconductor layer. The light transmitting electrode has a thickness of 20 to 200 A.

Abstract: The present invention provides a process for producing nano graphene platelets (NGPs) that are dispersible and conducting. The process comprises: (a) preparing a graphite intercalation compound (GIC) or graphite oxide (GO) from a laminar graphite material; (b) exposing the GIC or GO to a first temperature for a first period of time to obtain exfoliated graphite; and (c) exposing the exfoliated graphite to a second temperature in a protective atmosphere for a second period of time to obtain the desired dispersible nano graphene platelet with an oxygen content no greater than 25% by weight, preferably below 20% by weight, further preferably between 5% and 20% by weight. Conductive NGPs can find applications in transparent electrodes for solar cells or flat panel displays, additives for battery and supercapacitor electrodes, conductive nanocomposite for electromagnetic wave interference (EMI) shielding and static charge dissipation, etc.

Abstract: The invention is directed to a method for fabricating a mesoporous carbon material, the method comprising subjecting a precursor composition to a curing step followed by a carbonization step, the precursor composition comprising: (i) a templating component comprised of a block copolymer, (ii) a phenolic compound or material, (iii) a crosslinkable aldehyde component, and (iv) at least 0.5 M concentration of a strong acid having a pKa of or less than ?2, wherein said carbonization step comprises heating the precursor composition at a carbonizing temperature for sufficient time to convert the precursor composition to a mesoporous carbon material. The invention is also directed to a mesoporous carbon material having an improved thermal stability, preferably produced according to the above method.

Abstract: Provided is a biological component detection device with which a biological component can be detected at high sensitivity by using an InP-based photodiode in which a dark current is reduced without using a cooling mechanism and the sensitivity is extended to a wavelength of 1.8 ?m or more. An absorption layer 3 has a multiple quantum well structure composed of group III-V semiconductors, a pn-junction 15 is formed by selectively diffusing an impurity element in the absorption layer, and the concentration of the impurity element in the absorption layer is 5×1016/cm3 or less, the diffusion concentration distribution control layer has an n-type impurity concentration of 2×1015/cm3 or less before the diffusion, the diffusion concentration distribution control layer having a portion adjacent to the absorption layer, the portion having a low impurity concentration.

Abstract: The invention relates to the electric connection of conductor ends (26b), which are arranged in pairs and are positioned on top of each other, of a winding comprising individual conductors and to a method for establishing the connection, wherein a plurality of the conductor ends in pairs are arranged next to each other at a distance (a). In order to establish the electric connection with the briefest and most spatially delimited heating possible, it is proposed to insert a nanofoil (30) between the conductor ends (26b) that are to be connected in pairs, to then press the conductor ends together to clamp the nanofoil (30), and to finally weld or solder the conductor ends to each other by igniting the nanofoil (30).

Abstract: The present invention provides a method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. The present invention also provides a semiconductor device manufactured by this process.

Abstract: A battery anode comprised of metallic nanowire arrays is disclosed. In one embodiment the lithium battery uses Silicon nanowires or another element that alloy with Lithium or another element to produce high capacity lithium battery anodes.

Abstract: Disclosed are a semiconductor light emitting device and a method of manufacturing the same. The method includes providing a substrate having first and second main surfaces opposing each other and forming a first uneven structure in the first main surface, forming a sacrificial layer on the first main surface of the substrate, forming a mask having open regions on the sacrificial layer so as to expose a portion of an upper surface of the sacrificial layer, forming a second uneven structure in the substrate by etching the sacrificial layer and the substrate through the open regions, removing the sacrificial layer and the mask from the substrate, and forming a light emitting stack on the first and second uneven structures of the substrate.

Abstract: A cathode composite material includes a cathode active material particle having a surface, and a continuous aluminum phosphate layer coated on the surface of the cathode active material particle. A material of the cathode active material particle is layered type lithium nickel oxide. The present disclosure also relates to a lithium ion battery and a method for making the cathode composite material.

Abstract: A cathode composite material includes a cathode active material particle having a surface, and a continuous aluminum phosphate layer coated on the surface of the cathode active material particle. A material of the cathode active material particle is spinel type lithium manganese oxide. The present disclosure also relates to a lithium ion battery and a method for making the cathode composite material.

Abstract: A lithium battery comprising an anode and a cathode structure separated from one another by a membrane structure. The membrane structure comprises a layer which is only conductive to lithium ions and which is characterized by the property of having sufficient mechanical stability at temperatures higher than 150° C. to prevent a local short circuit between the anode and the cathode structure.

Abstract: A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.

Abstract: Provided is a reflective photomask reflecting an EUV light and used to irradiate a reflected light to a transfer sample, the reflective photomask including: a substrate; a high reflection part formed on the substrate; and a low reflection part formed on the high reflection part and being patterned, wherein the low reflection part, being patterned, includes at least one or more layers being stacked; and at least one layer of the low reflection part, being patterned, includes a layer including an Sn and an oxygen.

Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

Abstract: To provide a semiconductor transistor without variation in threshold voltage of an FET and a method of manufacturing the semiconductor transistor, the semiconductor transistor includes: a substrate; a first compound semiconductor layer formed above the substrate; a second compound semiconductor layer formed on the first compound semiconductor layer and having a bandgap larger than a bandgap of the first compound semiconductor layer; an oxygen-doped region formed by doping at least part of the second compound semiconductor layer with oxygen; a third compound semiconductor layer formed on the second compound semiconductor layer; a source electrode electrically connected to the first compound semiconductor layer; a drain electrode electrically connected to the first compound semiconductor layer; and a gate electrode formed on and in contact with the oxygen-doped region.

Abstract: According to various aspects, exemplary embodiments are provided of EMI shielding materials. In one exemplary embodiment, an EMI shielding material generally includes a conductive metal layer disposed on a thin carrier film. The EMI shielding material may be sufficiently compliant such that the conductive metal layer and thin carrier film are capable of conforming to an irregular surface when the EMI shielding material is applied to the irregular surface.