Abstract: A bipolar semiconductor device and manufacturing method. One embodiment provides a diode structure including a structured emitter coupled to a first metallization is provided. The structured emitter includes a first weakly doped semiconductor region of a first conductivity type which forms a pn-load junction with a weakly doped second semiconductor region of the diode structure. The structured emitter includes at least a highly doped first semiconductor island of the first conductivity type which at least partially surrounds a highly doped second semiconductor island of the second conductivity type.

Abstract: Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g.

Abstract: A method for forming a capacitor of a semiconductor device includes f forming a cylindrical storage node over a semiconductor substrate; depositing a first dielectric layer over the cylindrical storage node; and etching the first dielectric layer to reduce a thickness of a portion of the first dielectric layer on a protruded end of the cylindrical storage node. The method further includes depositing a second dielectric layer over the etched first dielectric layer, wherein the second dielectric layer supplements a thickness of a portion of the first dielectric layer on a bottom corner of the cylindrical storage node. Finally, a cell plate is formed over the second dielectric layer.

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications.

Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor device. Cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process including, applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate and forming interconnect metal layers.

Abstract: Embodiments relate to a bipolar junction transistor and a method for manufacturing the same. An oxide pattern may be formed on a P type semiconductor substrate. A low-density N type collector area may be formed in the semiconductor substrate. First spacers may be formed at sidewalls of the oxide pattern, and a low-density P type base area may be formed in the semiconductor substrate. Second spacers may be formed on sidewalls of the first spacers. A high-density N type emitter area may be formed in the low-density P type base area between the second spacers, and a high-density N type collector area may be formed in the semiconductor substrate at an outside of the first spacers. The bipolar junction transistor may be realized through a self-aligned scheme using dual nitride spacers. A base width between the emitter area and the low-density collector area may be narrowed by the width of the second spacer.

Abstract: A monolithic semiconductor device has an insulating layer formed over a first substrate. A second substrate is disposed over the first insulating layer. A power MOSFET with body diode is formed over the second substrate. A Schottky diode is formed over the second substrate in proximity to the MOSFET. An insulation trench is formed within the second substrate between the MOSFET and Schottky diode. The isolation trench surrounds the MOSFET and first Schottky diode. A first electrical connection is formed between a source of the MOSFET and an anode of the Schottky diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the Schottky diode. The Schottky diode reduces charge build-up within the body diode and reverse recovery time of the first power MOSFET. The power MOSFET and integrated Schottky can be used in power conversion or audio amplifier circuit.

Abstract: Disclosed is a semiconductor device with a bipolar transistor and method of fabricating the same. The device may include a collector region in a semiconductor substrate. A base pattern may be disposed on the collector region. A hard mask pattern may be disposed on the base pattern. The hard mask pattern may include a buffering insulation pattern and a flatness stopping pattern stacked in sequence. An emitter electrode may be disposed in a hole that locally exposes the base pattern, penetrating the hard mask pattern. A base electrode may contact an outer sidewall of the hard mask pattern and may be disposed on the base pattern. The flatness stopping pattern may contain an insulative material with etching selectivity to the buffering insulation pattern, the emitter electrode, and the base electrode.

Abstract: A method for micro-machining a varactor that is part of a membrane suspended MEMS tunable filter. In one non-limiting embodiment, the method includes providing a main substrate; depositing a membrane on the main substrate; depositing and patterning a plurality of sacrificial photoresist layers at predetermined times during the fabrication of the varactor; depositing metal layers that define a fabricated varactor structure enclosed within photoresist; coupling a carrier substrate to the fabricated structure opposite to the main substrate using a release layer; etching a central portion of the main substrate to expose the membrane; removing the carrier substrate by dissolving the release layer in a material that attacks the release layer but does not dissolve the photoresist; and removing the photoresist layers to provide a released varactor.

Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers.

Abstract: Provided is a power semiconductor device including a guard ring region to protect control devices. The power semiconductor device includes a semiconductor body layer extending over a semiconductor substrate of a first conductivity type. The semiconductor body layer has a second conductivity type opposite the first conductivity type. A well of the first conductivity type extends in the semiconductor body layer and is configured to be electrically insulated from the semiconductor substrate. At least one control device is formed in the well, where the control device comprises at least one of PN junction. A guard ring region of the first conductivity type is laterally spaced from but surrounds the well. The guard ring region together with the semiconductor substrate and the semiconductor body layer form a parasitic bipolar transistor, and the guard ring region functions as a collector of the parasitic bipolar transistor.

Abstract: An integrated circuit including a resistive memory element and a method of manufacturing the integrated circuit are described. The method of manufacturing the integrated circuit includes depositing a switching layer material and intentionally forming inhomogeneously distributed defects within the switching layer material to increase a number of switching cycles of the resistive memory element. The resistive memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state. The switching layer contains intentionally formed defects that increase the number of switching cycles of the switching layer.

Abstract: A transfer base substrate comprises: a substrate; a plurality of transfer thin film circuits formed on the substrate via removing layer; a test circuit formed on the substrate for checking circuit operation; and a wiring coupling each of transfer thin film circuits with a test circuit.

Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

Abstract: A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154) over the base electrode layer; (c) forming a mask layer (280) over a first portion of the base electrode layer, a portion of the first portion of the emitter electrode and a portion of the semiconductor substrate; and (d) implanting a dopant into a second portion of the base electrode layer after forming the emitter electrode after forming the mask layer.

Abstract: A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.

Abstract: A memory cell and a method of fabricating the same. A first conductive layer on a substrate is provided and a first type doped semiconductor layer is then formed on the first conductive layer. The first type doped semiconductor layer and the first conductive layer are patterned into a first line. A dielectric layer is formed on the substrate with an opening exposing the first line. A column comprising a second diode component, a buffer layer, and an anti-fuse layer is formed in the opening. A second line is formed connecting the column on the dielectric layer running generally perpendicularly to the first line.

Abstract: A method of manufacturing a nonvolatile organic memory device including a memory layer interposed between an upper electrode layer and a lower electrode layer, which includes dispersing ions of conductive nanoparticles in an organic material disposed between the two electrode layers and then reducing the ions of conductive nanoparticles into conductive nanoparticles in the organic material to form a desired memory layer. In addition, a nonvolatile organic memory device manufactured by the method of the current invention is also provided. The method allows the memory device to be manufactured using a rapid, simple, and environmentally friendly process, without the need for an encapsulation process. As well, the memory device has a low operating voltage, and hence, is suitable for application to various portable electronic devices that must have low power consumption.

Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.

Abstract: A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications.

Abstract: A rectifying contact to an n-type oxide material and/or a substantially insulating oxide material includes a p-type oxide material. The p-type oxide material includes a copper species and a metal species, each of which are present in an amount ranging from about 10 atomic % to about 90 atomic % of total metal in the p-type oxide material. The metal species is selected from tin, zinc, and combinations thereof.

Abstract: In one embodiment, a thyristor device may be formed in series relationship with a MOSFET. Alternating regions of opposite conductivity type may be formed in semiconductor material for defining source, body and drain regions for the MOSFET device, and in series relationship to the thyristor. A primary dopant for a commonly-shared cathode/anode-emitter and drain/source region may have a concentration that is at least one order of magnitude greater than that of any background dopant therein. In a particular embodiment, the thyristor device and the MOSFET in series relationship therewith collectively define part of a thyristor-based memory.

Abstract: Provided is a method for manufacturing a semiconductor device, including a dual-stage deposition step including: a first stage for introducing tantalum penta-ethoxide containing tantalum as a material gas into a reaction chamber in which a semiconductor substrate on a surface of which a lower electrode is made of ruthenium is placed to thus form a tantalum oxide film by a vapor-phase growth method such as a chemical vapor deposition method and the following second stage for removing from the reaction chamber the material gas introduced into the reaction chamber at the first stage and a byproduct produced at the first stage by introducing a nitrogen gas, and wherein the tantalum oxide film is formed on the semiconductor substrate, by repeating the dual-stage deposition step two or more times.

Abstract: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.

Abstract: A programmable structure and device and methods of forming and using the structure and device are disclosed. The structure includes a soluble electrode, an ion conductor, and an inert electrode. Upon application of a sufficient voltage, a conductive region forms within or on the ion conductor and between the electrodes. The presence or absence of the conductive region can be used to store information in memory devices.

Abstract: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate.

Abstract: A CMOS imager with two adjacent pixel active area regions without the presence of an intervening trench isolation region that typically separates two adjacent pixels and their associated photodiodes is provided. The shared active area region isolates the two adjacent photodiodes and provides good substrate to surface pinned layer contact without the presence of n? type dopant ions and due to the presence of p-type dopant ions. As a result, the size of the imager can be reduced and the photodiodes of the two adjacent pixels have increased capacitance.

Abstract: After a capacitor device including a lower electrode, a capacitor dielectric film made from a ferroelectric film and an upper electrode is formed on a substrate, an insulating film covering the capacitor device is formed. Subsequently, the capacitor device covered with the insulating film is annealed for crystallizing the ferroelectric film.

Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.