Abstract: This invention relates to a method for producing group IB-IIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source of a first group VIA element (said first group VIA element hereinafter being referred to as VIA1) under conditions to form a first film comprising a mixture of at least one binary alloy selected from the group consisting of a group IB-VIA1 alloy and a group IIIA-VIA1 alloy and at least one group IB-IIIA-VIA1 ternary alloy (iii) optionally heat treating the first film in the presence of a source of a second group VIA element (said second group VI element hereinafter being referred to as VIA2) under conditions to convert the first film into a second film comprising at least one alloy selected from the group consisting of a group IB-VIA1-VIA2 alloy and a group IIIA-VIA1-VIA2 alloy; and the at least one group IB-III-VI

Abstract: A thin film transistor is manufactured by forming a gate electrode on a substrate, forming a first insulating film on the gate electrode, forming an oxide semiconductor layer on the first insulating film with an amorphous oxide, patterning the first insulating film, patterning the oxide semiconductor layer, forming a second insulating film on the oxide semiconductor layer in an oxidative-gas-containing atmosphere, patterning the second insulating film to expose a pair of contact regions, forming an electrode layer on the pair of contact regions, and patterning the electrode layer to for a source electrode and a drain electrode.

Abstract: Provided are a thin-film transistor (TFT) display panel having improved electrical properties that can be fabricated time-effectively and a method of fabricating the TFT display panel. The TFT display panel includes: gate wirings which are formed on an insulating substrate; oxide active layer patterns which are formed on the gate wirings; data wirings which are formed on the oxide active layer patterns to cross the gate wirings; a passivation layer which is formed on the oxide active layer patterns and the data wirings and is made of silicon nitride (SiNx); and a pixel electrode which is formed on the passivation layer.

Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.

Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Abstract: A semiconductor device including thin film transistors having high electrical properties and reliability is proposed. Further, a method for manufacturing the semiconductor devices with mass productivity is proposed. The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, a buffer layer over the source electrode layer and the drain electrode layer, and a semiconductor layer over the buffer layer. A part of the semiconductor layer overlapping with the gate electrode layer is over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer contains a metal oxide having n-type conductivity.

Abstract: In a thin-film transistor comprising respective elements of: three electrodes of a source electrode, a drain electrode and a gate electrode; a channel layer; and a gate insulating film, at least the channel layer is formed by a metal oxide film including indium. Therefore, it is possible to obtain the thin-film transistor, which can manufacture an element to a polymer substrate without using a high temperature process and which can achieve a high performance and a high reliability at low cost.

Abstract: A semiconductor device has an integrated passive device (IPD) formed on a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed on the front side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed on the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed on the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed on the substrate and electrically connects the conductive layer to a ground point.

Abstract: A production method of a thin film transistor including an active layer including an amorphous oxide semiconductor film, wherein a step of forming the active layer includes a first step of forming the oxide film in an atmosphere having an introduced oxygen partial pressure of 1×10?3 Pa or less, and a second step of annealing the oxide film in an oxidative atmosphere after the first step.

Abstract: The present invention provides a p-type zinc oxide thin film that is clearly shown to be a p-type semiconductor based on the magnetic field dependence of the Hall voltage in the measurement of the Hall effect using a Hall bar, as well as a method for producing such a thin film with good reproducibility, and a light-emitting element thereof, and the present invention relates to the method for producing a p-type zinc oxide semiconductor thin film, for which combination is effected between a high temperature annealing step for activating a p-type dopant added to a zinc oxide thin film in order to develop the p-type semiconductor properties of zinc oxide or irradiating the thin film with an active species of p-type dopant to dope the film while the p-type dopant is active, and a low temperature annealing step in an oxidizing atmosphere, whereby conversion to a p-type semiconductor is realized, and relates to a p-type zinc oxide thin film thus produced using this method and a light-emitting element thereof, the pr

Abstract: A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.

Abstract: Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects.

Abstract: One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

Abstract: A method for manufacturing a thin film transistor containing an channel layer 11 having indium oxide, including forming an indium oxide film as an channel layer and subjecting the formed indium oxide film to an annealing in an oxidizing atmosphere.

Abstract: In an organic thin film transistor (TFT) substrate, the organic TFT substrate includes gate lines, data lines, a gate electrode, a source electrode, a drain electrode, a gate insulating layer, an organic semiconductor layer, and an organic protective layer. The gate and data lines are insulated from each other and cross each other to define pixel areas. The gate electrode is connected to the gate line. The source electrode is connected to the data line. The drain electrode faces the source electrode with the gate electrode disposed therebetween. The gate insulating layer covers the gate electrode and exposes a portion of the source and drain electrodes. The organic semiconductor layer contacts the source and drain electrodes. The organic protective layer is disposed on the organic semiconductor layer to protect the organic semiconductor layer.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.

Abstract: Embodiments of a thin film transistor with an atomic layer deposition gate dielectric layer having a high dielectric constant and a zinc indium oxide channel are disclosed.

Abstract: A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.

Abstract: A method of manufacturing a metal oxide semiconductor comprising the step of: conducting a transformation treatment on a semiconductor precursor layer containing a metal salt to form the metal oxide semiconductor, wherein the metal salt comprises one or more metal salts selected from the group consisting of a nitrate, a sulfate, a phosphate, a carbonate, an acetate and an oxalate of a metal; and the semiconductor precursor layer is formed by coating a solution of the metal salt.

Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.

Abstract: This invention provides a transparent oxide semiconductor, which comprises an oxide comprising indium oxide as a main component and cerium oxide as an additive and has such properties that light-derived malfunction does not occur, there is no variation in specific resistance of a thin film caused by heating and the like, and the mobility is high, and a process for producing the same. A semiconductor thin film characterized by comprising indium oxide and cerium oxide and being crystalline and having a specific resistance of 10+1 to 10+8 ?cm is used. This semiconductor thin film has no significant change in specific resistance and has high mobility. Accordingly, an element having improved switching properties can be provided by constructing a switching element using this semiconductor thin film.

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.

Abstract: In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.

Abstract: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the (0001) plane by about 2 degrees or less. ZnO based compound semiconductor crystal is grown on the principal surface.

Abstract: A semiconductor device and its manufacturing method are disclosed. The semiconductor device includes at least one integrated circuit on a semiconductor substrate having an active side and a back side. The lattice constant of the semiconductor material is increased. The manufacturing method includes stretching the semiconductor lattice in near-surface areas of the back side of the semiconductor substrate.

Abstract: The present invention provides methods of forming metal oxide semiconductor nanostructures and, in particular, zinc oxide (ZnO) semiconductor nanostructures, possessing high surface area, plant-like morphologies on a variety of substrates. Optoelectronic devices, such as photovoltaic cells, incorporating the nanostructures are also provided.

Abstract: The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into an electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.

Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.

Abstract: A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a blanket layer of a dielectric capping layer, wherein the depositing covers an exposed surface of the dielectric material layer and a surface of the bi-layer metallic cap. The bi-layer metallic cap includes a metal capping layer formed on a conductive surface of the interconnect feature; and a metal nitride formed on a top portion of the metal capping layer. An interconnect structure is also described having an interconnect feature formed in a dielectric layer; a bi-layer metallic cap formed on a top portion of the interconnect feature; and a dielectric capping layer formed over the bi-layer metallic cap.

Abstract: A semiconductor device and a fabricating method thereof are provided. A first device having a photodiode cell can be disposed adjacent to a second device having a transistor, and a connection electrode can electrically connect the first device and the second device.

Abstract: A method of integrated processing is provided for a substrate in the substrate processing tool. The substrate contains an etch feature in a dielectric film and an exposed metal interconnect pattern formed underneath the etch feature. The integrated process includes pretreating exposed surfaces of the etch feature and the exposed metal interconnect pattern with a flow of hydrogen radicals generated by thermal decomposition of H2 gas by a hot filament hydrogen radical source separated from the substrate by a showerhead plate containing gas passages facing the substrate. The integrated process further includes depositing a barrier metal film over the pretreated exposed surfaces, and forming a Cu metal film on the barrier metal film.

Abstract: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.