Abstract: A threshold comparator with hysteresis includes a comparator circuit, having a first input, for receiving an input voltage, a second input, and an output, which supplies an output voltage having a first value and a second value. A current generator, controlled by the output voltage, supplies a current to the first input in the presence selectively of one between the first value and second value of the output voltage. A selector circuit connects the second input of the comparator circuit to a first reference voltage source, which supplies a first reference voltage, in response to first edges of the output voltage, and to a second reference voltage source, which supplies a second reference voltage, in response to second edges of the output voltage, opposite to the first edges.

Abstract: An apparatus comprises a supply voltage divider, a state machine, two comparators and a threshold selector. The supply voltage divider divides a VCC into N states SK, and acquires the border voltages VK and VK+1 corresponding to the SK through a resistor divider. The threshold selector acquires a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine and then sends the acquired VK as VH to a first comparator, and acquires a corresponding voltage VK+1 and sends the acquired VK+1 as VL to a second comparator. The state machine determines whether or not the VH and the VL are matched with the current state SK. If matched, the OSC of the state machine will be turned off, otherwise, the next state Sk+1 or Sk?1 of the SK will be outputted.

Abstract: In a power detector, a comparator for detection receives an input signal and a reference voltage, and compares the input signal to the reference voltage around the switching time of active and inactive states of the output of the comparator in accordance with an output of an input switching signal generator. Except for the switching time, an input voltage for non-use of the comparator is inputs to the comparator for detection, and the differential inputs are fixed to the same potential. Therefore, aging reduction in the accuracy of power detection caused by BT degradation is effectively mitigated.

Abstract: A command detecting device of the present invention includes a comparator, a detection state selector, a time detector, and a detection time switch. The comparator compares a command input from the outside with a certain voltage value and outputs its comparison result as a first state or a second output state. The detection state selector selects an output state that has been determined as a valid output state out of the two output states from the comparator. The time detector measures a duration time of the valid output state and switches the control command when the duration time reaches a given set time. The detection time switch switches the set time for the time detector. The output state selected as the valid output state by the detection state selector is switched by the control command.

Abstract: A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.

Abstract: Disclosed herein is a data reproduction circuit including: a comparator configured to compare input data resulting from capacitive coupling with a comparison voltage as a threshold voltage and output a comparison result; and a comparison voltage variable section configured to change the comparison voltage along a mark rate of the input data and supply the changed comparison voltage to the comparator.

Abstract: A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.

Abstract: In one embodiment, a circuit is provided. The circuit includes a low-ohmic circuit and a a power supply node configured and arranged for providing a supply voltage across the low-ohmic circuit to a load from which current can be drawn. The circuit also includes a current reference circuit, configured and arranged for setting a current reference level that is based on a portion of the current from the power supply node, and a current-sensing circuit. The current-sensing circuit senses and is responsive to current passing through the low-ohmic circuit. The current-sensing circuit operates in a normal mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is less than the current threshold level, and in an over-current mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is greater than the current threshold level.

Abstract: There is provided a continuous time cross-correlator comprising: a quantizer for quantizing the incoming signal into discrete levels; a delay line comprising one or more delay units separating a plurality of delay line taps; for each of said delay line taps, a comparator for comparing the signal level of the delay line tap with a correlation value; a continuous time counter for taking the outputs of the plurality of comparators as its inputs, counting the results of the comparisons and outputting the results of the comparisons; and an output comparator for comparing the counter output with a threshold value. The cross-correlator provides for high speed continuous time cross-correlation with low power consumption and a small chip area. Methods of continuous time cross correlation are also provided.

Abstract: A zero-crossing gain control system is disclosed herein. The system comprises a gain control unit for amplifying an input signal to an output signal, a zero-crossing monitoring circuit for monitoring the input signal or output signal, and a register for latching the digital control signal and generating a gain control signal that controls the gain control unit. The system may further comprise a maximum write time setting circuit for generating a write signal. The digital control signal is written into the register when a zero-crossing state is monitored or a maximum write time since a change occurred on of the digital control signal is expired. An automatic gain control system is also disclosed herein and further comprises a peak detecting circuit for detecting the level of output signal, a logic circuit for lowering or restoring the digital control signal according to the result from the peak detecting circuit.

Abstract: Embodiments of the present invention provide a system and method for controlling a power down functionality for a component while limiting the number of inputs to the component. Embodiments may include a single input that may serve the dual purpose of providing both an input analog signal and a power down control. According to an embodiment, the power down threshold may be set as the defined minimum operating input voltage such that any input signals below the operating range may be interpreted as a power down command. Alternate signal ranges may be defined as indicating a power down command. According to an embodiment, an input signal having an improperly high voltage may additionally be interpreted as a power down or other predefined command such that any input signals outside of the predefined operating range may be interpreted as a power down command.

Abstract: A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train.

Abstract: The device for generating three mode signals includes: a voltage setting block including an input terminal receiving three input signals of driving voltage, open, and ground and setting three voltages according to the three input signals; and an output block including two output terminals and a second node B receiving the three voltages from the voltage setting block, and outputting three combined signals by comparing an input voltage with a reference voltage, whereby only a small number of resistors and amplifiers generates three mode signals to further reduce the chip size than the related art and the external power source is not required to solve the problems of the related art due to noise.

Abstract: An input buffer circuit for use in a semiconductor device includes a comparator configured to compare a reference voltage with a voltage of an input signal, and output the result of comparison, an activation unit configured to control an activation state of an input buffer in response to an enable signal, a skew adjusting unit configured to change an amount of a current flowing in the comparator in response to one or more skew adjusting signals, and a control signal generator configured to control the enable signal and the skew adjusting signal in response to one or more calibration codes and an input control signal.

Abstract: An identifying circuit is connected between a Universal Serial Bus (USB) interface and a controller. The identifying circuit includes first and second resistors, and a diode. When a power adapter is connected to the USB interface, a negative data pin of the USB interface is floating, an identify pin of the controller receives a high level signal to determine that the power adapter is connected to the USB interface. When a computer is connected to the USB interface, the negative data pin of the USB interface outputs a low level signal, the identify pin of the controller receives a low level signal to determine that the USB interface is connected to the computer.

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract: A voltage regulator that modulates the switching of a switching circuit to regulate the output voltage level supplied to a system. The regulator uses a comparator circuit to compare a reference signal to an analog signal derived from the output voltage of the regulator, and outputs a binary signal based on the comparison. The regulator may use a counter circuit that interrogates the binary signal from the comparator circuit and generates a counter signal proportional to, for example, the duration of the binary signal when it stays in one of the two binary states. The regulator then uses a trigger circuit that generates a signal based on the counter signal to effectuate the modulation of the switching of the switching circuit. The reference signal may be modified by a hysteresis level adjuster to force a triggering event at the switching circuit.

Abstract: A disclosed semiconductor device includes an input terminal, a power line, a pnp-bipolar transistor connected to the power line, a first resistor connecting an emitter of the transistor to the input terminal, a second resistor connecting a collector of the transistor to ground, an operation circuit operable when the input voltage is a predetermined voltage or higher, the predetermined voltage being set within a first voltage region in which the input voltage cannot turn on the transistor, a comparator comparing an internal voltage with a reference voltage, the internal voltage being changed from a voltage value in a non-conductive state in which the transistor is not turned on, and an output terminal configured to output an output voltage which changes in response to a result of comparing the internal voltage with the reference voltage.

Abstract: A method of monitoring supply voltage includes providing a single reference voltage, providing a single ratioed supply voltage, comparing the reference voltage to the ratioed supply voltage to provide an output signal, wherein the output signal comprises a first logic value in first and second operating conditions, and a second logic value in a third operating condition, wherein the first, second, and third operating conditions are determined by two crossing points of the reference voltage and ratioed supply voltage characteristics. The first and second operating conditions can represent undervoltage and overvoltage conditions, and the third operating condition can represent a normal operating condition. The reference voltage can be provided by a bandgap reference circuit.

Abstract: A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.

Abstract: A method and a device for canceling an offset voltage in an output of a comparator circuit include applying a signal to a first input of the comparator as a function of an initial tap point in a resistor ladder. While the signal is applied to the first input, a nominal voltage is applied to a second input of the comparator, and then an output of the comparator is analyzed. The signal to the first input is changed in response to the analyzing, by accessing a different tap point in the resistor ladder.

Abstract: A gate driving circuit includes a thermal sensing unit for sensing temperature to output a sensing voltage, a compare unit for comparing the sensing voltage with a reference voltage to output a control voltage, a charging control module for controlling a pre-charging operation according to the control voltage, and a plurality of shift register stages. Each shift register stage includes an input unit for outputting a driving control voltage according to a first input signal, a clock input unit for outputting a driving voltage according to a system clock, a driving unit for outputting a gate signal according to the driving control voltage and the driving voltage, and a pull-down unit for pulling down the gate signal and the driving control voltage according to a second input signal. The driving voltage is also controlled by the pre-charging operation for enhancing driving ability.

Abstract: An output current detecting circuit includes: a current detecting transistor having a size smaller than that of an output transistor and a control terminal, to which a voltage same as a control voltage of the output transistor is applied; a sensing resistor connected to the current detecting transistor in a serial mode; a comparison circuit comparing a voltage converted by the sensing resistor and a reference voltage to judge a magnitude of a current flowing through the output transistor; and a reference voltage generating circuit, wherein the reference voltage generating circuit includes a constant current circuit flowing a constant current and a resistance element having one terminal connected to a power source voltage terminal, the reference voltage generating circuit generating the reference voltage based on a power source voltage by the conversion of the constant current into a voltage by flowing the constant current through the resistance element.

Abstract: A comparator includes a first power source terminal, a second power source terminal, a first transistor of a first conductivity type coupled between the first power source terminal and a first node, and including a control terminal coupled to a first terminal, a second transistor of the first conductivity type coupled between the first power source terminal and a second node, and including a control terminal coupled to a second terminal, a third transistor of a second conductivity type coupled between the first node and a third terminal, and including a control terminal coupled to the first node, a fourth transistor of the second conductivity type coupled between the second node and the second power source terminal, and including a control terminal coupled to the first node, and a fourth terminal coupled to the second node.

Abstract: A comparison circuit includes: an offset removal unit configured to store offset information of a comparator in response to a reference voltage, and compare a pad voltage with the reference voltage based on the offset information to drive a first node; and a comparison signal output unit configured to buffer a signal of the first node and output a comparison signal.

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract: According to one embodiment, a power supply voltage monitor circuit includes a constant voltage circuit, a level shift circuit, a clamping circuit, a first differential circuit, and a second differential circuit. The first differential circuit include a differential unit receiving a constant current supplied from a current source and outputting an output voltage in accordance with a potential difference between a first input voltage obtained by subjecting the second constant voltage to resistive division and a second input voltage obtained by subjecting the power supply voltage to resistive division, and an output unit outputting a rectangular signal in accordance with the output voltage of the differential unit.

Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.

Abstract: A voltage detection device and a semiconductor device including the same are provided. The voltage detection device includes: a first clock generator which generates a first clock signal having a period that changes according to an external voltage; a second clock generator which generates a second clock signal having a predetermined period corresponding to a reference voltage; and a detector which detects a change of the external voltage by comparing the first clock signal with the second clock signal.

Abstract: An output transistor bias generation circuit which applies a bias voltage to one of two NMOS transistors constituting an output circuit having a stack structure, includes diode-connected NMOS transistors provided between an external connection pad connected to an external signal line having a voltage higher than a power supply voltage of an LSI circuit, and the gate of an NMOS transistor, diode-connected NMOS transistors provided between the gate of the NMOS transistor and a ground line, a diode-connected NMOS transistor provided between the power supply line and the gate of the NMOS transistor, and a capacitor-connected NMOS transistor provided between the gate of the NMOS transistor and the ground line.

Abstract: Systems and methods for achieving multiple supply voltage compatibility of an input/output (I/O) ring of an integrated circuit (IC) chip. The IC chip includes a core surrounded by the I/O ring which includes a voltage detector circuit. An I/O supply voltage of the IC chip is sensed by the voltage detector circuit to generate a control signal. The control signal is used to configure the I/O ring to operate at the I/O supply voltage of the I/O ring, thus enabling the IC to operate at multiple supply voltage levels.

Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.

Abstract: Power supply detection circuit. The power supply detection circuit includes an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node. The power supply detection circuit also includes a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH. Further, the power supply detection circuit includes a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage. Moreover, the power supply detection circuit also includes an output circuit that inverts the first output voltage to generate a second output voltage at a second node.

Abstract: This transmission input circuit is provided with an adjustment processing section which turns ON a switch at an empty timing where transmission current from a slave device is not flowing, to allow a reference current to flow from a constant current circuit to a current detection resistor, generates in the current detection resistor a target adjustment voltage, in which a threshold voltage corresponding to the reference current is added to a load current detection voltage corresponding to the load current, and adjusts a digital value so that a reference voltage output from a digital variable resistor matches with the target adjustment voltage.

Abstract: According to one embodiment, a hysteresis comparator is provided with to first to third current sources, a comparison amplifying unit, a reference voltage generating unit, a current mirror circuit, first to fifth N-channel MOS transistors, and first to fifth terminals.

Abstract: A transmission input circuit of the present invention is provided with: a current detection resistor which receives an input of a line current flowing through a transmission line and generates a line current detection voltage; a constant current circuit which generates a predetermined reference current; a first switch which performs a switching operation at an empty timing where a transmission current is not flowing, to thereby allow the reference current to flow from the constant current circuit to the current detection resistor, and generate a reference voltage, in which a threshold voltage corresponding to the reference current is added to a load current detection voltage corresponding to the load current; a capacitor which is connected to the current detection resistor via the first switch; a second switch which performs a switching operation in synchronization with the first switch to thereby sample-hold the reference voltage generated by the current detection resistor in the capacitor; and a comparator

Abstract: A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current (920); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal (930); latching the difference signal and the inverted difference signal to generate a first and second latched signals (950); generating a control signal using at least the first and second latched signals (970); and controlling the bias current in response to the control signal (980), wherein the comparing the input signal and the reference signal (930) is activated and deactivated in response to the controlling the bias current (980).

Abstract: In one general aspect, an apparatus can include a first voltage detect circuit configured to produce an output signal at a first power supply voltage, and configured to be in a non-monitoring state at a second power supply voltage greater than the first power supply voltage. The apparatus can include a second voltage detect circuit configured to change from a non-monitoring state to a monitoring state and configured to produce an output signal at a third power supply voltage between the first power supply voltage and the second power supply voltage. The apparatus can also include a combination circuit configured to produce a power-on-reset signal based on a logical combination of the output signal produced by the first voltage detect circuit and the output signal produced by the second voltage detect circuit.

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract: An apparatus for providing programmable hysteresis control using an enable pin of a device is disclosed. An enable pin is configured to receive an input signal to enable and disable an associated device responsive to the input signal. A current sink is attached to the enable pin and is responsive to circuitry that disables the current sink responsive to application of the input signal at a first voltage level and enables the current sink responsive to application of the input signal at a second voltage level.

Abstract: A coupling failure of a supply terminal or a ground terminal is easily detected. A diode is disposed between a supply terminal of a semiconductor device and a first I/O terminal so that the supply terminal is located on a cathode side, and the first I/O terminal is located on an anode side. A determination unit determines whether or not a voltage of the supply terminal is lower than a voltage of the first I/O terminal when a signal of high level equal to a supply voltage is input to the first I/O terminal.

Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected between the first transistor and the fourth terminal, and a fourth transistor of the second conductivity type connected between the second transistor and the third terminal, the fourth transistor flowing a mirror current depending on a current passing through the third transistor.

Abstract: Techniques for providing a comparator incorporating amplitude hysteresis. In an exemplary embodiment, a current offset stage is coupled to a comparator having a folded cascode architecture. The current offset stage offsets the current generated from an input stage to delay switching of the comparator output to implement amplitude hysteresis. In an exemplary embodiment, rail-to-rail input voltages may be accommodated by providing dual NMOS and PMOS input stages. In another exemplary embodiment, the amplitude hysteresis may be controlled by an adjustable threshold voltage. In yet another exemplary embodiment, a constant transconductance gm bias circuit may be provided to maintain the stability of the threshold voltage across input common-mode voltage and/or other variations.

Abstract: A reset circuit for resetting and terminating the resetting of a reset target includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), a gate drive circuit configured to switch a drain voltage of the n-channel MOSFET from a low level to a high level when a power supply voltage exceeds a predetermined threshold, a sink circuit configured to maintain the drain voltage at the low level by sinking a current flowing from a drain side of the n-channel MOSFET to the sink circuit, and a block circuit configured to block the current sinking to the sink circuit when the power supply voltage exceeds the predetermined threshold. The low level indicates a state where the reset target is in a reset state and the high level indicates a state where the reset state of the reset target is terminated.

Abstract: The present invention relates to a simple and small-sized circuit configuration (10) for significantly reducing resettling time of a peak or zero current comparator. This circuit configuration (10) provides the comparator input stage with an alternative current path at the comparator input submitted to a large voltage variation able to disturb the DC-settings. This circuit configuration (10) comprises a pair of small transistors (P3, P4) coupled to a differential pair of transistors (N1, N2) of the comparator input stage and having a polarity different from said pair of transistors (P3, P4). The gates of the transistors P3 and P4 share a common terminal connected to said comparator input. The currents and voltages across the comparator are always maintained close to the normal DC-setting values during the voltage transition phase. This circuit configuration (10) can be used in any current comparator for detecting a peak or a zero current, in particular, in DC-DC converters based on a switched operating mode.

Abstract: A host computer includes an enclosure, a motherboard mounted in the enclosure. The motherboard includes a battery, a reference voltage generating circuit, an electronic switch, an alarm unit mounted on the enclosure, and a comparator. The reference voltage generating circuit generates a reference voltage. The comparator is connected to the battery and the reference voltage generating circuit to receive the reference voltage and detect a voltage of the battery. The comparator compares the detected voltage of the battery with the reference voltage, and outputs a control signal to turn on the electronic switch to start the alarm unit when the voltage of the battery is less than the reference voltage.

Abstract: A data input device of a semiconductor memory apparatus includes: a differential amplifier configured to compare an input to a reference voltage and output a differential signal based on the comparison; and a control circuit configured to adjust a current driving capacity of the differential amplifier by turning on a first current path connected to the differential amplifier in response to a first enable signal and turning off a second current path connected to the differential amplifier in response to a second enable signal in a standby mode, wherein, during a time that a plurality of external command signals toggle back and forth between a status of all being high signals and a status of all being low signals repeatedly, the second enable signal is controlled to be maintained at a low state signal.

Abstract: A detection circuit is disclosed in specification and drawing, where the detection circuit includes a current source, a voltage-current converter and a current comparator. The voltage-current converter is configured to acquire a receiving current from the current source by comparing a reference voltage with an input voltage of a detecting terminal. The current comparator is configured to output an output voltage by comparing a steady current with an output current based on the receiving current.

Abstract: Methods, devices and circuits are provided for protection from backdrive current. One such device is subject to back voltage from an output node of the device and includes circuitry that is configured to compare the supply voltage node and the output node. In response to the comparison, the circuitry generates an output signal. Level shifted versions of the output signal are used to provide an output voltage corresponding to the higher of a supply voltage node and an output node. Switches are used to place the device in different modes in response to the output signal.