Abstract: According to one embodiment, a semiconductor integrated circuit includes first to six transistors and a constant current source circuit. The first and second transistors form a current mirror circuit connected to a first power source node. The third and fourth transistors form a differential pair circuit. The third and fourth transistors receive first and second external signals at their gates, respectively. The constant current source circuit has one end connected to source terminals of the third and fourth transistors, and the other end connected to a second power source node. The fifth and sixth transistors form a current pathway between a common gate node of the first and second transistors and the constant current source circuit. The gate of fifth transistor is connected to a signal output node. The gate of sixth transistor receives a signal of logic opposite to a signal to be obtained at the signal output node.

Abstract: A branch device has a connector for connecting to a display device as a sink device. A pull-up resistor is connected between an internal power source in the branch device and a first terminal in the connector when power supply from the display device is not necessary for the branch device, and a short resistor is connected between the first terminal and a second terminal in the connector when power from the display device is necessary. An evaluation circuit determines whether or not the power has to be supplied from the display device to the branch device by evaluating a voltage appearing at the first terminal when the signal for determination is applied to the second terminal by comparing that voltage to two different reference voltages which are within a range higher than a GND voltage and lower than the voltage of a second internal power source of the device itself.

Abstract: A data processing system (100), such as a System-on-Chip, includes a processor (120), a memory (140) that has an expected minimum data retention voltage, and a brown-out detector (160), which includes a brown-out detection circuit (201) that has an analog output, and an output circuit (248 and 252) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.

Abstract: A power-on reset circuit includes a first monitor circuit that monitors a power supply voltage, an output circuit that outputs a reset release signal upon detection, by the first monitor circuit, of the power supply voltage exceeding a first predetermined value, and a control circuit having lower current consumption than the first monitor circuit, wherein the control circuit includes a second monitor circuit that monitors the power supply voltage, a suppression circuit that suppresses current flowing through the first monitor circuit upon detection, by the second monitor circuit, of the power supply voltage exceeding a second predetermined value higher than the first predetermined value, and an output fixing circuit that fixes the output of the output circuit to a predetermined potential upon detection, by the second monitor circuit, of the power supply voltage exceeding the second predetermined value.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals connected to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected in series with the first transistor, a fourth transistor of the second conductivity type connected in series with the second transistor, a fifth transistor of the second conductivity type through which a mirror current depending on a current flowing through the third transistor, a sixth transistor of the second conductivity type flowing a mirror current depending on a current flowing through th

Abstract: An improved fast settling bit slicing comparator circuit includes a comparator having a non-inverting and inverting input; the non-inverting input receiving an input signal; a filter circuit for receiving the input signal and being connected with the inverting input of the comparator; a positive feedback circuit interconnected between the output of the comparator and the non-inverting input of the comparator for introducing a predetermined hysteresis offset; the filter circuit including a filter resistance and filter capacitance having a reduced time constant sufficient to compensate for at least a portion of the hysteresis offset. Additionally, the positive feedback circuit may be interconnected with the inverting input of the comparator through the filter circuit for gradually reducing the effect of the hysteresis offset by reducing the differential voltage between the inverting and non-inverting inputs.

Abstract: A resistor-programmable device generates pulses counted by a counter. The counter's output controls a drive signal generator, such as an adjustable current source. The drive signal generator generates a drive signal (such as a current), which leads to the creation of a sense signal (such as a voltage) using a resistance. The resistance can have one of a set of specified values or fall within one of a set of specified windows. The resistor-programmable device can convert the resistance value into a digital value, which can be used to set a sensor trip point threshold or some other parameter. The digital or parameter value is independent of changes in the resistance that are within a specified tolerance. For instance, the same parameter value could be selected even when the resistance varies within some tolerance (such as 1%) as the resistor-programmable device can determine the window in which the resistance falls.

Abstract: A single-ended signaling system in which transmitted and returned signal currents are enabled to flow substantially parallel to one another and thereby maintain a substantially uniform impedance along the length of a single-ended signal conductor. A reference plane is disposed substantially parallel to a single-ended signaling conductor and coupled to the signaling conductor within a signal-receiving IC and to signaling supply voltage nodes within a signal-transmitting IC. By this arrangement, an signal current flowing to or from the receiving IC via the signaling conductor is conducted to the reference plane, thereby enabling a signal-return current to flow back to or back from the transmitting IC along a single path that is substantially parallel to the signal conductor.

Abstract: A Group III-N high electron mobility transistor is driven by a high-voltage gate driver that limits the gate-to-source voltage across the transistor by controlling the maximum charge that can be placed on a boot strap capacitor that charges up the gate of the transistor to turn on the transistor.

Abstract: A Universal Series Bus USB port detection and testing circuit, configured to detect the voltage output of a USB port of an electronic device, includes a voltage comparing circuit and an indicating circuit. The indicating circuit is connected to an output terminal of the voltage comparing circuit. The voltage comparing circuit compares the voltage output from the USB port against a reference voltage and output a signal whereby the indicating circuit indicates whether the voltage is within, or above, or below, the standard range.

Abstract: A circuit is for generating a signal that indicates whether or not an input current exceeds a pre-established threshold current and, in the affirmative case, that is representative of the difference between the input current and the threshold current. The circuit includes a diode-connected transistor biased with a first constant current in a saturation functioning condition, a sense transistor mirrored to the diode-connected transistor and biased in a linear (triode) functioning condition, a load transistor connected in series to the sense transistor, biased with a second constant current and the control terminal of which is connected in common with the respective terminals of the diode-connected transistor and of the sense transistor. The input current to be compared is injected to a common current node of the load transistor and of the sense transistor, and the output voltage is available on the other current node of the load transistor.

Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.

Abstract: A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator.

Abstract: An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level.

Abstract: A circuit arrangement for operating voltage detection has a detection block (1) and a control block (2). Detection block (1) has a first transistor (P1) that is connected between a first supply voltage terminal (VDD) and a first node (K1) and has a first control terminal (S1), a first resistor element (R1) that is connected between first node (K1) and second supply voltage terminal (VSS), a second transistor (P2) that is connected between first supply voltage terminal (VDD) and a second node (K2) and has a second control terminal (S2), a second resistor element (R2) that is connected between second node (K2) and second supply voltage terminal (VSS), a first switch (N1) that connects first node (K1) to second control terminal (S2), and a third resistor element (R3) that is connected between second control terminal (S2) and first supply voltage terminal (VDD).

Abstract: An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits.

Abstract: A chopper type comparator including a first power supply line to which a first power source is supplied, a second power supply line to which a second power source having lower voltage than the first power source is supplied, a reference voltage input part to which a reference voltage is input, a target comparison voltage input part to which a target comparison voltage is input, a comparing part configured to compare the size between the reference voltage input from the reference voltage input part and the target comparison voltage input from the target comparison voltage input part, an output part configured to output a comparison result of the comparing part, and a resistance value setting part configured to set resistance values of the first power supply line and/or the second power supply line.

Abstract: An integrated circuit die includes a microprocessor and a control circuit to control elements of a voltage regulator to supply power to the microprocessor.

Abstract: The device for generating three mode signals includes: a voltage setting block including an input terminal receiving three input signals of driving voltage, open, and ground and setting three voltages according to the three input signals; and an output block including two output terminals and a second node B receiving the three voltages from the voltage setting block, and outputting three combined signals by comparing an input voltage with a reference voltage, whereby only a small number of resistors and amplifiers generates three mode signals to further reduce the chip size than the related art and the external power source is not required to solve the problems of the related art due to noise.

Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

Abstract: A power integration circuit includes: a first transistor having a control electrode connected to a first voltage source to be supplied with a control signal therefrom, the first transistor being connected between a switch and a ground. A sense resistor has one end connected to the ground. A second transistor has a control electrode connected to the first voltage source to be applied with a control signal therefrom, with the second transistor being connected between the switch and the other end of the sense resistor. The power integration circuit further includes: a comparator for comparing the sense voltage with the reference voltage and delivering a difference between the sense voltage and the reference voltage to a logic circuit.

Abstract: A host computer includes an enclosure, a motherboard mounted in the enclosure. The motherboard includes a battery, a reference voltage generating circuit, an electronic switch, an alarm unit mounted on the enclosure, and a comparator. The reference voltage generating circuit generates a reference voltage. The comparator is connected to the battery and the reference voltage generating circuit to receive the reference voltage and detect a voltage of the battery. The comparator compares the detected voltage of the battery with the reference voltage, and outputs a control signal to turn on the electronic switch to start the alarm unit when the voltage of the battery is less than the reference voltage.

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract: Embodiments of this invention provide enhanced triggering capabilities such as frequency and phase triggering in a test and measurement instrument, such as a Real-Time Spectrum Analyzer (RTSA) or oscilloscope. A test and measurement instrument can include input terminals to receive RF signals, an ADC to digitize the RF signals, a digital downconverter to produce I and Q baseband component information, and a power detector to determine a power level using the I and Q information. A comparator compares the power level received from the power detector with a user-definable power threshold, and produces a logic signal for enabling one or more phase or frequency demodulators. The one or more demodulators produce IQ-based time-domain traces derived from the I and Q component information when the power level determined by the power detector exceeds the power threshold. Trigger circuitry is configured to trigger on an event responsive to a delayed trigger enable signal.

Abstract: Plurality of current mirror circuits CM1 to CM5 at which the same amount of current I1 flows in the circuits. Transistors Qa4/Qb5 are ON state when it is in the steady state. Transistors Qa5/Qb7 turn ON and transistors Qb6/Qa6 turn OFF when a voltage generation circuit 3 applies a voltage more than predetermined value V12 to node N3. Therefore node N3 becomes fixed voltage V12. On the other hand, voltage generation circuit 3 applies a voltage less than predetermined value V23 to node N3, transistors Qb5/Qa6 turn ON, and transistors Qa5/Qb7 turn OFF. Accordingly, the node N3 becomes fixed voltage V23.

Abstract: An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode.

Abstract: A resistor-programmable device generates pulses counted by a counter. The counter's output controls a drive signal generator, such as an adjustable current source. The drive signal generator generates a drive signal (such as a current), which leads to the creation of a sense signal (such as a voltage) using a resistance. The resistance can have one of a set of specified values or fall within one of a set of specified windows. The resistor-programmable device can convert the resistance value into a digital value, which can be used to set a sensor trip point threshold or some other parameter. The digital or parameter value is independent of changes in the resistance that are within a specified tolerance. For instance, the same parameter value could be selected even when the resistance varies within some tolerance (such as 1%) as the resistor-programmable device can determine the window in which the resistance falls.

Abstract: A circuit for detecting an input voltage includes a voltage-to-current converter and a current comparator. The voltage-to-current converter is operable for generating a monitoring current that varies in accordance with the input voltage. The current comparator coupled to the voltage-to-current converter is operable for comparing the monitoring current to a threshold current proportional to the temperature of the circuit, and for generating a detection signal indicating a condition of the input voltage based on a result of the comparison.

Abstract: An internal voltage generator includes a comparison unit, a driving circuit and a bias unit. The comparison unit compares a reference voltage and an internal voltage and is configured to output a comparison voltage, which is based on a difference between the reference voltage and the internal voltage. The driving circuit receives the comparison voltage and an external power supply voltage and is configured to output the internal voltage to an output node in response to the comparison voltage. The bias unit receives the internal voltage and is configured to adaptively adjust a bias current that flows through the bias unit to drive the comparison unit, in consideration of a level of the internal voltage.

Abstract: A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.

Abstract: An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.

Abstract: An output stage includes a first transistor pair with a first conductivity type and a second transistor pair with a second conductivity type. The source connections of the first and second transistors in the first transistor pair and of the first and second transistors in the second transistor pair are respectively connected to a first and a second circuit node. The output stage further includes a first current mirror with the first conductivity type and a second current mirror with the second conductivity type. The current mirror transistors are connected to the signal output. The signal input is connected to control connections of the first transistors in the first and second transistor pairs. A second connection of the second transistor in the first transistor pair is connected to the second current mirror, and a second connection of the second transistor in the second transistor pair is connected to the first current mirror.

Abstract: A level detector, a voltage generator, and a semiconductor device are provided. The voltage generator includes a level detector that senses the level of an output voltage to output a sensing signal and a voltage generating unit that generates the output voltage in response to the sensing signal. The level detector may include a first reference voltage generator configured to divide a first voltage and to output a first reference voltage, a second reference voltage generator configured to divide a second voltage in response to the output voltage and to output a second reference voltage that varies as a function of temperature, and a differential amplifier configured to receive the first and second reference voltages and to output a sensing signal in response to a sensing voltage generated by amplifying a difference between the first and second reference voltages.

Abstract: A peak detection/digitization circuit includes a plurality of level detect units, each having a comparator and a flip-flop with a clock input responsive to the output of the comparator. For a detection period, each level detect unit configures a data output signal of the flip-flop to a first data state responsive to a start of the detection period. Further, each level detect unit is configured to enable the comparator responsive to the data output signal having the first data state or a second data state, respectively. While the comparator is enabled during the detection period, the level detect unit configures the data output signal of the flip-flop responsive to a comparison of an input signal to a corresponding reference voltage level by the comparator. The data output signals of the flip-flops of the level detect units at the end of the detection period are used to determine a digital value representative of a peak voltage level of the input signal.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently.

Abstract: A single-ended thermal switch, design structure, and method of sensing temperature. A circuit includes a first MOS transistor and a second MOS transistor connected in series between a first power supply and a second power supply. The circuit apparatus also includes a signal conditioner connected to a node between the first and second MOS transistors. The first MOS transistor and the second MOS transistor are configured such that a leakage current of the second MOS transistor decreases a voltage of the node below a switch point of the signal conditioner when the temperature exceeds a threshold temperature.

Abstract: According to an exemplary aspect of the present invention, it is possible to provide a communication device that can prevent misdetection of a disconnection and achieve a high output level on a receptacle side. In the communication device, a reference voltage generating circuit outputs a reference voltage that changes according to a first control signal. A differential amplifier circuit amplifies input signals and outputs differential output signals, the voltages of which change according to a second control signal, to a receptacle. A disconnection detector circuit outputs a disconnection detecting signal when a differential amplitude voltage between the differential output signals is equal to or higher than the reference voltage. The reference voltage generating circuit outputs the reference voltage that is larger than the differential amplitude voltage when the receptacle is terminated and that is smaller than the differential amplitude voltage when the receptacle is opened.

Abstract: Embodiments related to an undervoltage detector are described and depicted. An undervoltage detector is formed to detect a low input bias voltage with a voltage divider network including first and second series circuits of semiconductor devices coupled to terminals of the input bias voltage source, and a resistor voltage divider including first and second voltage divider resistors coupled in series with the first and second series circuits. A ratio representing the numbers of semiconductor devices in the series circuits is substantially equal to a ratio of resistances in the resistor voltage divider. The equality of the ratios may be corrected by the presence of other resistances in the undervoltage detector. The semiconductor devices are each coupled in a diode configuration. The first series circuit is coupled to a current mirror to provide a bias current for a comparator that produces an output signal for the undervoltage detector.

Abstract: Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.

Abstract: Monitoring parameters of memory modules is described. According to certain embodiments, one or more parameters on respective memory modules are monitored. Corresponding parameter information is transmitted away from the respective memory module to a device that is external to the respective memory modules.

Abstract: A circuit for detecting a phase imbalance of signals includes a conversion block and a comparator coupled to the conversion block. The conversion block generates generating a direct current (DC) signal based on a first signal and a second signal. The level of the DC signal is determined by a phase difference between the first signal and the second signal. The comparator compares the DC signal to a reference signal and generates an alert signal if a difference between the DC signal and the reference signal is greater than a predetermined threshold.

Abstract: According to one general aspect, an output driver configured to drive output signals from a core device may include a voltage convertor, an output stage, and a biasing unit. In various embodiments, the output driver is configured to operate in either a core device voltage mode or a high voltage mode. In some embodiments, the voltage convertor may be configured to receive a pair of differential input signals from a core device, wherein a maximum voltage of the input signals is equivalent to a core device voltage, and convert the input signals to a pair of intermediate input signals. In one embodiment, when in high voltage mode, the maximum voltage of the intermediate input signals may be equivalent to a high voltage that is higher than the core device voltage.

Abstract: Apparatus, systems and methods are provided for protecting a processing system from electromagnetic interference. An integrated circuit comprises a sensing arrangement configured to sense an interference signal and an interference detection module coupled to the sensing arrangement. The interference detection module is configured to detect when a power level associated with the interference signal is greater than a threshold value. In one embodiment, the interference detection module generates an interrupt for a processing system when the power level associated with the interference signal is greater than the threshold value.

Abstract: A soft-start device including a current source, a first transistor, and a second transistor is described. The first transistor is coupled to the current source, and an amount of current conducted by the first transistor is determined according to a voltage. The second transistor is also coupled to the current source, and an amount of current conducted by the second transistor is determined according to a fixed bias. An initial voltage value of the voltage is smaller than a voltage value of the fixed bias. However, after a soft start, the voltage value of the first voltage is increased gradually to be larger than the voltage value of the fixed bias, such that the soft start may be implemented smoothly.

Abstract: An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level.

Abstract: In an integrated circuit, a state of a switch coupled to the integrated circuit is determined by comparing a switch voltage at a first terminal of the switch to a reference voltage at a first time. If the switch voltage is higher than the reference voltage, the switch is determined to be in a first state. If the switch voltage is lower than the reference voltage, the switch voltage is stored in a storage element to produce a stored voltage. The stored voltage is compared to the switch voltage at a second time after the first time. A determination is made that the switch is in the first state if the switch voltage is higher than the stored voltage at the second time. A determination is made that the switch is in a second state if the switch voltage is not higher than the stored voltage at the second time.

Abstract: Disclosed is a reference voltage generating circuit including a constant current circuit which comprises: a first resistive element and a bipolar transistor connected in series between a supply voltage terminal and a constant potential point; a first MOS transistor having a gate connected to a node connecting the first resistive element with the bipolar transistor; a second resistive element connected in series between a source of the first MOS transistor and the constant potential point; a second MOS transistor connected between a drain of the first MOS transistor and the supply voltage terminal; and a third MOS transistor forming a current mirror in conjunction with the second MOS transistor, wherein a constant current generated by the constant current circuit or a current proportional to the generated constant current is converted to a voltage as a reference voltage.

Abstract: A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.