Contacts in Semiconductor Devices
Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.
The present invention relates generally to semiconductor devices, and more particularly to contacts for semiconductor devices and mask sets, layouts, and methods of fabrication thereof.
BACKGROUNDGenerally, semiconductor devices are used in a variety of electronic applications, such as computers, cellular phones, personal computing devices, and many other applications. For example, home, industrial, and automotive devices that, in the past, comprised only mechanical components now have electronic parts that require semiconductor devices.
Semiconductor devices are manufactured by depositing many different types of material layers over a semiconductor workpiece or wafer, and patterning the various material layers using lithography. The material layers typically comprise thin films of conductive, semi-conductive and insulating materials that are patterned and etched to form integrated circuits (ICs). There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single die or chip, for example.
The accurate reproduction of patterns on the surface of a semiconductor substrate is critical to the proper fabrication of semiconductor devices. The semiconductor substrate may have undergone previous fabrication processes and may already feature layers and structures created by those fabrication processes. Improperly reproduced patterns can result in semiconductor devices that do not operate to design specifications or that do not operate at all. For example, transistors can be created with improperly sized gates; conductors can be created that are short circuited or open circuited with other conductors or devices; structures can be created with wrong geometries, and so forth. Improperly reproduced patterns can reduce the yield of the fabrication process, thereby increasing the overall cost of the product. The reproduction process typically involves the use of optical lithography to reproduce the patterns onto the surface of the semiconductor substrate followed by a variety of processes either to subtract (for example, etch) or to add (for example, deposit) materials from and to the semiconductor substrate.
There is a trend in the semiconductor industry towards reducing the size of features, e.g., the circuits, elements, conductive lines, and vias of semiconductor devices, in order to increase performance of the semiconductor devices, for example. The minimum feature size of semiconductor devices has steadily decreased over time. However, as features of semiconductor devices become smaller, it becomes more difficult to pattern the various material layers because of diffraction and other effects that occur during a lithography process. Interference and processing effects can cause distortion and deviation in the mask's patterns as they are reproduced onto the semiconductor substrate. For example, key metrics such as resolution and depth of focus of the imaging systems may suffer when patterning features at small dimensions.
Shrinking device geometries have a particularly acute affect on patterning small contact holes. As contact holes become smaller, masks used to pattern contact holes require smaller apertures. The smaller the aperture, the more difficult it is to get enough light through the aperture to adequately expose the resist disposed on the semiconductor wafer below. If enough light is not used to expose the mask, a pattern will not print on the resist below. If, on the other hand, the mask and semiconductor wafer is exposed with a high intensity of light, the exposed pattern below becomes washed out and side-lobes are exposed beyond the desired perimeter of the exposed area. Consequently, the generation and exposure of small contact whole regions require a very narrow lithographic process window, thereby limiting the range of exposure settings that will produce an adequate exposure. These exposure settings can include illumination or dose, focus, numerical aperture, and light coherence factor, sigma.
Hence, what is needed are methods, designs and structures of producing small geometry contact holes without degrading manufacturing process windows.
SUMMARY OF THE INVENTIONThese and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention.
Embodiments of the invention include contacts for semiconductor devices. In accordance with a preferred embodiment of the present invention, a semiconductor device includes a plurality of contacts disposed over a substrate. The plurality of contacts is disposed as rows and columns on an orthogonal grid. Each row of the plurality of contacts is spaced from a neighboring row of the plurality of contacts by a first distance. Each column of the plurality of contacts is spaced from a neighboring column of the plurality of contacts by a second distance.
The foregoing has outlined rather broadly the features of an embodiment of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTSThe making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Embodiments of the present invention achieve technical advantages by providing a method to simultaneously increase process margin, yield, and product performance using double patterning techniques. The present invention will be described with respect to preferred embodiments in a specific context, namely printing contacts for MOS transistors. The invention may also be applied, however, to other types of devices that require contacts such as diodes, bipolar junction transistors, thyristors, and memory devices such as DRAM, FeRAM, phase change memories, or floating gate devices. Similarly, the invention may also be applied to other types of devices in other applications and other technological fields. Embodiments of the invention may be implemented in many types of semiconductor devices, such as logic, memory, peripheral circuitry, power applications, and other types of semiconductor devices, as examples.
The present invention will be described with respect to preferred embodiments in a specific context, namely an optical lithography method for the reproduction of patterns of very small dimensions. This invention may also be applied to semiconductor fabrication processes where other forms of lithography are used; for example, where the wavelength of the electromagnetic waves used to transfer the patterns is on the same order as the pattern dimensions. The present invention can also be used in lithographic processes outside the semiconductor field; for example, in processes where the interaction between wavelength, numerical aperture of the imaging system, and minimum pitch between structures distort the reproduction of mask patterns, or where small features require masks with very small apertures.
One of the challenges in lithography includes the formation of contacts, especially narrow contacts, primarily due to a narrow process window. Forming contacts in tight spaces, for example, between adjacent gate lines in a scaled cell, is extremely challenging since any mistakes result in undesirable shorts or undesirable capacitive coupling between source and gate lines. However, contacts should also be large enough to minimize resistance. In various embodiments, the present invention overcomes these limitations by using a double patterning and freeze technique in contact formation. Instead of forming small apertures in the mask, the contacts are formed by a summation of multiple exposures of lines over multiple mask layers. The shape of the lines in each mask layer governs the final shape of the contact. Using embodiments of the invention, contacts of desirable dimensions that minimize resistances can be fabricated without degrading process margin.
Referring to
In various embodiments, the contacts 20 are aligned along the first axis x, and along the second orthogonal axis y. In particular the contacts are formed at the intersection of rows and columns. Hence, contacts 20 are formed on intersections b1, c1, d1, a2, c2, a3, b3, d3, a4, b4, c4, and d4. However, not all intersections of rows and columns form a contact. For example, in
In various embodiments, the minimum spacing or vertical pitch py, for example, between rows is defined by a technology and/or process window of the lithography. In various embodiments, the contacts 20 comprise both contacts to the gate region as well as source/drain contacts. In some embodiments, the vias coupling different metallization levels are also formed on a grid array as described above.
Although not explicitly illustrated, in various embodiments, the grid extends over a large area of the semiconductor device. In particular, the same grid extends over a substantial portion of the circuitry. For example, in one embodiment all regions of the chip have a single grid. In another embodiment, the chip is divided into multiple regions with different contact grids. For example, the SRAM region comprises a first grid and the logic region comprises a second grid. In another embodiment, a system on a chip comprises a first grid over a first circuitry, for example, an analog or RF circuitry; a second grid over a second circuitry, for example, a logic circuitry; a third grid over a third circuitry, for example, over a volatile memory region; and a fourth circuitry over a non volatile memory.
In various embodiments, the contacts 20 can comprise any suitable shape, for example, based on performance or layout requirements. Similarly, contacts 20 may comprise other dimensions than a contact with minimum dimension. The minimum dimension for the contact is typically defined by the technology and includes minimization of electrical parameters such as resistance and area while maximizing the process window for the fabrication processes to maximize process yield.
In various embodiments, the contacts 20 described above are fabricated using three exposures with three masks: a first mask 30 (
Referring to
After forming a first plurality of features on a template layer under the first photo resist layer, a second photo resist layer is formed over the patterned template layer. Subsequently, a second exposure using the second mask 40 is performed to expose the second photo resist layer.
Referring to
After forming a third photo resist layer, a third exposure using the third mask 50 is performed. As illustrated in
Thus in various embodiments, the mask set avoids the problems with exposing through a small aperture mask as each individual mask level comprises a plurality of lines. The illumination conditions are selected to maximize the image quality, for example, minimize across chip line width variation, over a range of process window parameters such as depth of focus, exposure dose, and mask error factor. The mask design has been explained in terms of opaque and transparent regions to clearly describe the embodiments of the invention. However, actual mask design and materials can be chosen to incorporate modifications to improve the imaging system. For example, to improve image resolution, the mask design may comprise attenuated phase shifter materials and/or alternating mask materials in opaque regions 32 and transparent regions 31 of
The device is fabricated using conventional processing in front end of the line manufacturing, wherein active device regions are fabricated. During front end processing, device regions including isolation regions, gate electrode, gate dielectric, source/drain regions, source/drain extension regions, and channel regions are fabricated. After forming source/drain regions, a silicide region is formed over the source/drain regions, and optionally over the gate electrode regions.
A first photo resist layer 102 is deposited over a first layer 101 (layer to be patterned to form contact openings). Referring to
In various embodiments, the active devices are formed on the substrate 100 using conventional processing techniques. For example, in one embodiment, active regions including source/drain regions, source/drain extensions, channel regions, and gate regions of MOS transistors are fabricated on the substrate 100.
In various embodiments, the first layer 101 comprises an insulating layer. Further the first layer 101 is deposited over a etch stop liner (not shown). The etch stop liner is deposited over the substrate 100, for example. For example, a nitride film (e.g., silicon nitride) is deposited over the silicide regions. The first layer 101 preferably comprises insulating materials typically used in semiconductor manufacturing for inter-level dielectric (ILD) layers, such as SiO2, tetra ethyl oxysilane (TEOS), fluorinated TEOS (FTEOS), doped glass (BPSG, PSG, BSG), organo silicate glass (OSG), fluorinated silicate glass (FSG), spin-on glass (SOG), SiN, SiON, or low k insulating materials, e.g., having a dielectric constant of about 4 or less, or combinations or multiple layers thereof, as examples, although alternatively, the first layer 101 may comprise other materials. The first layer 101 may comprise a thickness of about 500 nm or less, for example, although alternatively, the first layer 101 may comprise other dimensions.
A frozen resist 103 is formed from the first photo resist layer 102 after patterning and freezing.
The first photo resist layer 102 is exposed with the first mask 30 shown in
As illustrated in
Referring to
Referring to
In one embodiment, contacts 20 comprise contacts plugs that couple conductive regions on substrate 100, for example silicide regions on substrate 100. In another embodiment, the contacts 20 comprise contact plugs to couple first metal lines in the metallization layers with gate electrodes of devices disposed on substrate 100. In various embodiments, the first layer 101 comprises multiple layers, for example, a liner followed by an interlevel dielectric layer. Subsequent processing continues as in conventional processing. For example, further levels of metallization comprising metal lines and vias are formed over the contacts 20.
Using the embodiments of
In
Although the contacts described above are for first metal levels, in various embodiments, vias coupling various metal levels can be formed using embodiments of the invention. Hence, in some embodiments some or all levels of vias are formed as gridded contacts.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A method of manufacturing a structural building block of a semiconductor device, the method comprising:
- coating a first photo resist layer over a substrate;
- using a first mask, patterning the first photo resist layer thereby forming first features, the first mask comprising a first plurality of lines oriented in a first direction;
- after patterning the first photo resist layer, coating a second photo resist layer;
- using a second mask, patterning the second photo resist layer thereby forming second features, wherein the second mask comprises a second plurality of lines oriented in a second direction orthogonal to the first direction;
- after patterning the second photo resist layer, coating a third photo resist layer; and
- using a third mask, patterning the third photo resist layer thereby forming third features, wherein the first, the second, and the third features comprise a pattern for forming contact holes.
2. The method of claim 1, further comprising:
- freezing the first features after patterning the first photo resist layer, wherein the second photo resist layer is coated after freezing the first features; and
- freezing the second features after patterning the second photo resist layer, wherein the third photo resist layer is coated after freezing the second features.
3. The method of claim 1, wherein the contact holes are formed in regions patterned by each of the first mask, the second mask, and the third mask.
4. The method of claim 1, wherein the contact holes are formed in regions exposed by each of the first mask, the second mask, and the third mask.
5. The method of claim 1, further comprising forming an insulating layer over the substrate, wherein the first photo resist layer is coated over the insulating layer.
6. The method of claim 5, further comprising etching the insulating layer using the first, the second, and the third features as a pattern.
7. The method of claim 1, wherein the first, the second, and the third photo resists are each a positive tone resist.
8. The method of claim 1, wherein the first photo resist and the second photo resist are each a negative tone resist.
9. A semiconductor device comprising:
- a first plurality of contacts disposed over a first region of a substrate, the first plurality of contacts being disposed as rows and columns on a first orthogonal grid, each row of the first plurality of contacts being spaced by a first distance, and each column of the first plurality of contacts being spaced by a second distance; and
- a second plurality of contacts disposed over a second region of a substrate, the second plurality of contacts being disposed as rows and columns on a second orthogonal grid, each row of the second plurality of contacts being spaced by a third distance, and each column of the second plurality of contacts being spaced by a fourth distance.
10. The device of claim 9, wherein the first region comprises a SRAM cell, and wherein the second region comprises a logic cell.
11. The device of claim 9, wherein the first region comprises analog circuitry, and wherein the second region comprises logic circuitry.
12. The device of claim 9, wherein the first distance and the third distance are different.
13. The device of claim 12, wherein the second distance and the fourth distance are different.
14. The device of claim 9, wherein the first distance is about the same as the second distance, and wherein the third distance is about the same as the fourth distance.
15. The device of claim 9, wherein the first and the second plurality of contacts couple semiconductor regions disposed over the substrate with metal lines disposed over the substrate.
16. The device of claim 9, wherein the first and the second plurality of contacts couple between metallization levels disposed over the substrate.
17. The device of claim 9, wherein a distance between adjacent contacts along each column of the first plurality of contacts is the first distance or an integer multiple of the first minimum distance.
18. The device of claim 9, wherein a distance between adjacent contacts along each row of the first plurality of contacts is the second distance or an integer multiple of the second distance.
19. The device of claim 9, wherein a distance between adjacent contacts along each column of the second plurality of contacts is the third distance or an integer multiple of the third minimum distance, wherein a distance between adjacent contacts along each row of the second plurality of contacts is the fourth distance or an integer multiple of the fourth distance.
20. The device of claim 9, wherein a length measured along the row of the first plurality of contacts follows the equation:
- length=n×length of individual contact+(n−1) second distance, wherein n is a positive integer.
21. The device of claim 9, wherein a width measured along the column of the first plurality of contacts follows the equation:
- width=n×width of individual contact+(n−1) first distance, wherein n is a positive integer.
22. A SRAM cell comprising:
- a first access transistor and a second access transistor;
- a first NMOS transistor and a second NMOS transistor; and
- a first PMOS transistor and a second PMOS transistor, wherein a first source/drain contact of the first access transistor, a first source/drain contact of the second PMOS transistor, and a first source/drain contact of the second NMOS transistor are disposed on a first row, wherein a gate contact of the first access transistor and a gate contact common to the second NMOS and the second PMOS transistors is disposed on a second row, wherein a second source/drain contact of the first access transistor, a first source/drain contact of the first PMOS transistor, a second source/drain contact of the second PMOS transistor, the second source/drain contact of the second NMOS transistor is disposed on a third row, wherein a gate contact common for the first NMOS and the first PMOS transistors and a gate contact of the second access transistor are disposed in a fourth row, wherein a second source/drain contact of the first NMOS transistor, a second source/drain contact of the first PMOS transistor, and a second source/drain of the second access transistor are disposed on a fifth row.
23. The SRAM cell of claim 22, wherein the second source/drain contact of the first access transistor comprises a first source/drain contact of the first NMOS transistor, wherein the second source/drain of the second NMOS transistor comprises the first source/drain of the second access transistor.
24. The SRAM cell of claim 22, wherein the first, the second, the third, the fourth, and the fifth rows are parallel to each other.
25. The SRAM cell of claim 22, wherein the first source/drain contact of the first access transistor, the second source/drain contact of the first access transistor, and the second source/drain contact of the first NMOS transistor are disposed in a first column, wherein the gate contact common to the second NMOS and the second PMOS transistors, the first and the second source/drain contacts of the first PMOS transistor are disposed in a second column, wherein the first source/drain contact of the second PMOS transistor, the second source/drain contact of the second PMOS transistor, and the gate contact common for the first NMOS and the first PMOS transistors are disposed in a third column, wherein the first and the second source/drain contacts of the second NMOS transistor and the second source/drain contact of the second access transistor are disposed in a fourth column.
26. The SRAM cell of claim 25, wherein the first, the second, the third, and the fourth columns are parallel to each other, and wherein the first, the second, the third, and the fourth columns are each perpendicular to the first, the second, the third, the fourth, and the fifth rows.
Type: Application
Filed: Jan 27, 2009
Publication Date: Jul 29, 2010
Inventors: Roberto Schiwon (Hopewell Junction, NY), Klaus Herold (Fishkill, NY), Jenny Lian (Walkill, NY), Sajan Marokkey (Wappingers Falls, NY), Martin Ostermayr (Beacon, NY)
Application Number: 12/360,599
International Classification: H01L 27/11 (20060101); H01L 21/04 (20060101); H01L 23/48 (20060101);