Pin Grid Type Patents (Class 257/697)
  • Patent number: 10332827
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 25, 2019
    Assignee: Volterra Semiconductor Corporation
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony J. Stratakos
  • Patent number: 10324500
    Abstract: A high strength hinge mechanism is described herein. In one or more implementations, a computing device includes a display portion which includes a display device, and a base portion which includes a keyboard. A hinge mechanism is attached to the display portion and the base portion to enable rotation of the display portion relative to the base portion. The hinge mechanism includes a friction element and a cylindrical shaft secured to the friction element and to a chassis of the display portion. The friction element is configured to apply friction to the shaft in a radial direction as the shaft is rotated. The rotation of the shaft enables the display portion to be rotated from a closed position to a fully-open position. The hinge mechanism also includes a frame structure to support the friction element and the shaft.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: June 18, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Christopher Alan Schafer, Prasad Raghavendra
  • Patent number: 10297582
    Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 21, 2019
    Assignee: Invensas Corporation
    Inventors: Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Reynaldo Co, Ellis Chau, Belgacem Haba
  • Patent number: 10269778
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Po-Hao Tsai
  • Patent number: 10262929
    Abstract: A semiconductor device and a semiconductor device manufacturing method that may prevent positional displacement of an electronic component mounted on a lead frame. The semiconductor device includes a lead frame, and an electronic component that has a protruding or recessed structure at a bonding face that bonds to the lead frame and is bonded to the lead frame, in a state in which a portion of the lead frame is fitted together with the protruding or recessed structure.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 16, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Yuuki Kodama
  • Patent number: 10242956
    Abstract: A semiconductor device is disclosed that may include a first semiconductor die comprising a copper pillar, a second semiconductor die comprising a copper pillar, and a conductive bump connecting the copper pillar of the first semiconductor die to the copper pillar of the second semiconductor die. The first semiconductor die may comprise a metal dam formed between the copper pillar and a bond pad on the first semiconductor die. The conductive bump may have a melting point lower than melting points of the copper pillar of the first semiconductor die and the copper pillar of the second semiconductor die. The first semiconductor die may be coupled to a substrate with a conductive wire coupled to the bond pad and to the substrate. The first semiconductor die may comprise a redistribution layer formed beneath the copper pillar on the first semiconductor die.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 26, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Dong Hee Lee, Min Yoo, Dae Byoung Kang, Bae Yong Kim
  • Patent number: 10168222
    Abstract: An apparatus is disclosed that comprises an integrated circuit and a thermal detector array configured to detect thermal radiation from the integrated circuit. A method is disclosed that comprises providing an integrated circuit and disposing a thermal detector array so as to detect thermal radiation from the integrated circuit. Another apparatus is disclosed that comprises means for processing and means for detecting thermal radiation from the means for processing.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Rama Rao Goruganthu, Ali Akbar Merrikh
  • Patent number: 10170434
    Abstract: A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Yu-Hsiang Hu, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10103627
    Abstract: A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 16, 2018
    Assignee: Altera Corporation
    Inventors: Teik Wah Lim, Ashraf W. Lotfi, Choong Kit Wong, John Weld
  • Patent number: 10090236
    Abstract: The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: October 2, 2018
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Nuwan S. Jayasena, David A. Roberts
  • Patent number: 10009992
    Abstract: A hybrid PCB system has a hybrid redistribution layer that redistributes a large pad-to-pad pitch to a smaller, finer pad-to-pad pitch and applies hybrid materials to balance the thermal-mechanical stress. The hybrid PCB system combines wafer level packaging, IC substrate and high density PCB technologies within a single hybrid PCB. The hybrid PCB system addresses the opportunity for interconnect reliability, design and assembly of a electronic components with pad pitches less than 400 microns directly to a PCB without need of an IC substrate or interposer.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: June 26, 2018
    Assignee: Multek Technologies Limited
    Inventors: Joan K. Vrtis, Michael James Glickman, Todd Robinson, Hollese Galyon
  • Patent number: 10002817
    Abstract: A power module includes: a ceramic substrate that includes a principal surface and a back surface, and is provided with a plurality of metal wirings on the principal surface; a semiconductor chip mounted on any metal wiring of the plurality of metal wirings; and a resin part disposed around each of the plurality of metal wirings. Further, side faces of the metal wirings each have: a first region in which a plating film is formed; a second region that is positioned above the first region and that is a non-plating region; and a third region that is positioned between the first region and the second region and in which metal particles are formed. The resin part is bonded to the metal particles, the plating film, and the principal surface of the ceramic substrate.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 19, 2018
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Osamu Ikeda, Takayuki Kushima, Shinji Okubo, Takaaki Miyazaki
  • Patent number: 9872409
    Abstract: The invention provides a device module including a base, a plastic part, and an external connection. The plastic part is provided on the base. The device is provided on the base and embedded in the plastic part. The device is a sensor, an electronic device, or a circuit board. The external connection includes an embedded portion and a lead-out portion. The embedded portion is connected to the device, extends along the base, and is embedded in the plastic part. The lead-out portion is contiguous with the embedded portion and led out of the plastic part.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: January 16, 2018
    Assignee: HOSIDEN CORPORATION
    Inventors: Takeshi Isoda, Koji Shinoda
  • Patent number: 9820389
    Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: November 14, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventor: Ban Pak Wong
  • Patent number: 9818680
    Abstract: Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 14, 2017
    Assignee: BroadPak Corporation
    Inventor: Farhang Yazdani
  • Patent number: 9793048
    Abstract: A capacitor arrangement structure includes a casing, a housing, and a heat sink. The casing accommodates a capacitor. The casing includes a casing bottom. The housing includes a bottom wall. The housing has a height from the bottom wall which includes an inner surface and an outer surface opposite to the inner surface in a height direction. The casing is mounted on the inner surface so that the casing bottom opposes a mounting surface in the inner surface. The heat sink includes a heat sink top. The heat sink is provided on the outer surface of the bottom wall not to overlap the casing viewed along the height direction. The heat sink top opposes the outer surface. A distance between the casing bottom and the mounting surface in the height direction is smaller than a distance between the heat sink top and the mounting surface in the height direction.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 17, 2017
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Tomoaki Ono, Shinnosuke Sato, Kosuke Nishiyama, Atsushi Amano
  • Patent number: 9761552
    Abstract: An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Shimizu, Seiki Sakuyama
  • Patent number: 9736967
    Abstract: Cooling apparatus cooling for an electrical or electronic device, comprising an at least partially hollow body containing a refrigerant and having a plurality of electrically conductive sections Each electrically conductive section has a respective coupling portion suitable to be operatively associated with a corresponding electrically conductive part of the electrical or electronic device, wherein the at least partially hollow body further comprises one or more electrically insulating sections. Each electrically insulating section is positioned between and electrically insulates from each other two adjacent electrically conductive sections.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: August 15, 2017
    Assignee: ABB S.P.A.
    Inventors: Francoise Molitor, Patrik Kaufmann, Tilo Buehler, Francesco Agostini, Thomas Gradinger, Federico Gamba
  • Patent number: 9735043
    Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Shih-Yen Lin
  • Patent number: 9673172
    Abstract: An integrated circuit device and a method of fabricating the same are presented. The integrated circuit device (1) includes two or more active components (30a, 30b), possibly fabricated by different semiconductor technologies, and an interposer structure (10) adapted for carrying the two or more active components such that at least one of the active components is carried on a top surface of the interposer structure. The integrated circuit device also includes at least one metal cap (40), furnished on the top surface of the interposer structure and encapsulating at least one of the active components. Some variants of the integrated circuit device of the invention are suited for operation under extreme conditions.
    Type: Grant
    Filed: November 24, 2013
    Date of Patent: June 6, 2017
    Assignee: ELTA SYSTEMS LTD.
    Inventors: Yaniv Maydar, Yohai Joseph
  • Patent number: 9659909
    Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: May 23, 2017
    Assignee: SK hynix Inc.
    Inventors: Hee Min Shin, Mi Young Kim
  • Patent number: 9645098
    Abstract: The invention relates to a detection system (1) for detecting a soldered joint (16, 17) of an electronic component (10), particularly an integrated circuit. The component comprises a cuboid enclosure. The detection system comprises a detection device (2) with an emitter (5) for electromagnetic radiation and a detector (6) for the electromagnetic radiation. The detection device is designed to generate electromagnetic radiation (18, 19) with the emitter and to transmit said radiation to the component. The detector is arranged and designed to detect electromagnetic radiation (18?, 19?) reflected by the component and to generate an image data set representing the reflected radiation.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: May 9, 2017
    Assignee: Robert Bosch GmbH
    Inventors: Stefan Scheller, Torsten Hundert, Marco Braun
  • Patent number: 9627291
    Abstract: A semiconductor device includes: a substrate; a semiconductor chip mounted over the substrate and having a solder bump coupled by soldering with an electrode over the substrate; and a heating unit for locally generating heat in a corner part within the horizontal plane of the semiconductor chip when an operating temperature of the semiconductor chip is equal to or less than a prescribed temperature.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 18, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Shinichiro Uekusa
  • Patent number: 9627337
    Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: April 18, 2017
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jung-Fu Hsu, Tai-Hung Lin, Chang-Tien Tsai
  • Patent number: 9607914
    Abstract: Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventor: Paul J. Gwin
  • Patent number: 9603264
    Abstract: The invention relates to a method for bonding stacked layers (19, 20) for making printed circuits, by electromagnetic induction. In particular, a magnetic flux is locally induced at a plurality of conducting spacers (25) provided along a peripheral area (22) of the multilayer stack (18). By this method, it is possible to induce magnetic fluxes with opposite sign in individual areas of the peripheral area, thus achieving the maximum energy efficiency during the bonding process. The invention further comprises an induction head and a bonding apparatus for performing the method.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: March 21, 2017
    Assignee: CEDAL EQUIPMENT S.R.L.
    Inventor: Bruno Ceraso
  • Patent number: 9600424
    Abstract: Semiconductor chips are provided. The semiconductor chip includes a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a command address pad in a first direction. In addition, the semiconductor chip includes a third data pad, a second data strobe pad and a fourth data pad sequentially arrayed from the command address pad in a second direction. Data are inputted and outputted through the first and fourth data pads or through the second and third data pads in a predetermined bit organization. Related semiconductor chip packages and semiconductor systems are also provided.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 21, 2017
    Assignee: SK hynix Inc.
    Inventors: Bok Rim Ko, Dong Kyun Kim
  • Patent number: 9541395
    Abstract: A sensor comprises a substrate (16) and a sensor element (20) anchored to the substrate (16), the substrate (16) and sensor element (20) being of dissimilar materials and having different coefficients of thermal expansion, the sensor element (20) and substrate (16) each having a generally planar face arranged substantially parallel to one another, the sensor further comprising a spacer (26), the spacer (26) being located so as to space at least part of the sensor element (20) from at least part of the substrate (16), wherein the spacer (26) is of considerably smaller area than the area of the smaller of face of the substrate (16) and that of the sensor element (20).
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 10, 2017
    Assignee: Atlantic Inertial Systems Limited
    Inventor: Christopher Paul Fell
  • Patent number: 9480172
    Abstract: A printed circuit board and a method for producing a printed circuit board consisting of at least two printed circuit board regions, wherein the printed circuit board regions each comprise at least one conductive layer and/or at least one conductive component, wherein printed circuit board regions to be connected to one another, in the region of in each case at least one lateral surface directly adjoining one another, are connected to one another by a mechanical coupling. At least one sub-region or connection port of the conductive layer, and/or a conductive element of the component are electrically conductively coupled to each other at the lateral surface.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 25, 2016
    Assignee: AT & S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventors: Volodymyr Karpovych, Johannes Stahr
  • Patent number: 9355969
    Abstract: A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package substrate; a second semiconductor chip on the conductive spacer and the first semiconductor chip; a molding unit that covers the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and an electromagnetic interference (EMI) shield that covers the molding unit.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-woo Park
  • Patent number: 9345137
    Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: May 17, 2016
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventor: Ban Pak Wong
  • Patent number: 9265177
    Abstract: Methods for fabricating a coolant-cooled component assembly are provided, which include providing a multi-component assembly and a module lid with openings aligned over respective electronic components. Thermally conductive elements are disposed within the openings, each including opposite coolant-cooled and conduction surfaces, with the conduction surface being thermally coupled to the respective electronic component. A manifold assembly disposed over the module lid includes inner and outer manifold elements, with the inner element configured to facilitate flow of coolant onto the coolant-cooled surfaces. The outer manifold element is disposed over the inner manifold element and coupled to the module lid, with the inner and outer manifold elements defining a coolant supply manifold, and the outer manifold element and module lid defining a coolant return manifold.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: February 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Amilcar R. Arvelo, Levi A. Campbell, Michael J. Ellsworth, Jr., Eric J. McKeever
  • Patent number: 9231351
    Abstract: A smart socket is provided. The smart socket has a set of power sockets, configured for a set of power pins of a smart plug to plug into, a driving pin and a set of detection pins, configured for forming a circuit with a set of feedback pins of a smart plug when the set of power pins is plugged into the power sockets, and an identification code module, configured for obtaining an identification code of an electric appliance, from the circuit, to which the smart plug belongs.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 5, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Shen-Ming Chung, Hsiao-Hui Lee, Chin-Chen Lee
  • Patent number: 9226398
    Abstract: In an embodiment, a printed circuit board includes a number of bond pads formed on a surface of the printed circuit board. At least a portion of the number of bond pads is arranged in an array of bond pads that includes a number of rows and a number of columns. A first portion of the number of rows include a number of adjacent rows having a first pitch and a second portion of the number of rows include at least one pair of adjacent rows having a second pitch different from the first pitch. In an embodiment, the second pitch is greater than 0.5 mm and less than 1.5 mm. In some embodiments, the array of bond pads can include at least one row of no-connect bond pads.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 29, 2015
    Assignee: Marvell International Ltd.
    Inventors: Steven M. Goss, Roger N. Switzer, Yinfei Song
  • Patent number: 9184153
    Abstract: A chip stack structure taking a wafer as a stacking base and stacking chips thereon is provided. The chip stack structure is capable of achieving high density electrode bonding and breaking the bottleneck of requiring interposer to serve as a transferring interface in three dimensional chip package. The chip stack structure is easily fabricated and compatible with wafer level process, so as to reduce processing time and manufacturing cost. A method for fabricating the chip stack structure is also provided.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: November 10, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Su-Tsai Lu, Jing-Ye Juang
  • Patent number: 9153520
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet Gandhi
  • Patent number: 9132494
    Abstract: A wiring board and a method for manufacturing the wiring board reinforced by means of a resin is provided. Embodiments of the wiring board allow for reliable attachment of a connection member, like a socket, to a terminal member. For example, a base of terminal pins is put on pin grid array (PGA) terminal pads, and a bonding material paste including solder and an electric insulation material made of a resin is placed on each of the PGA terminal pads. The bonding material paste is then heated to fuse the solder and soften the electric insulation material. Subsequently, the bonding material paste is cooled to solidify the solder and bond each of the bases to a corresponding PGA terminal pad and form an electric insulation surface layer on an exposed surface of each of solder junctions to which the respective bases are bonded.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 15, 2015
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Masahiro Inoue, Hajime Saiki, Atsuhiko Sugimoto
  • Patent number: 9111916
    Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: August 18, 2015
    Assignee: Intel Corporation
    Inventors: Mihir K. Roy, Mathew J. Manusharow
  • Patent number: 9106005
    Abstract: Disclosed is a surface mount device to be mounted on a base member, including plural lead units, each of the plural lead units including, a lead including a body portion and a foot formed at an end of the lead; a solder portion formed at the foot of the lead to protrude toward the direction of the base member to have a summit portion, and a diffusion prevention portion provided on the lead for preventing a diffusion of a solder along the body portion of the lead.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 11, 2015
    Assignee: FUJITSU COMPONENT LIMITED
    Inventors: Takeshi Okuyama, Toshihiro Kusagaya, Tohru Yamakami
  • Patent number: 9093435
    Abstract: A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: July 28, 2015
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Patent number: 9035472
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takaharu Nagasawa
  • Patent number: 9013032
    Abstract: A plastic SON/QFN package for high power has a pair of oblong metal pins exposed from a surface of the plastic, the pins straddling a corner of the package; each pin has a long axis, the long axes of the pair forming a non-orthogonal angle.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Patent number: 8994165
    Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Oi, Seiji Oka, Yoshiko Obiraki, Osamu Usui, Yasushi Nakayama
  • Patent number: 8955219
    Abstract: The invention relates to a method for fabricating a bond by providing a body including a metallic surface provided with an inorganic, dielectric protective layer. The protective layer covers at least one surface zone of the metallic surface in which the metallic surface is to be electrically conductive bonded to a contact conductor. To fabricate the bond, a portion of a provided contact conductor above the surface zone is pressed on to the protective layer and the body so that the protective layer is destroyed above the surface zone in achieving an electrically conductive bond between the metallic surface and the contact conductor.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Roman Roth, Dirk Siepe
  • Patent number: 8952520
    Abstract: A power semiconductor device with improved productivity, reduced size and reduction of amounting area therefore is provided. In the provided power semiconductor device, an external terminal does not limit an increase in current. The power semiconductor device is sealed with transfer molding resin. In the power semiconductor device, a cylindrical external terminal communication section is arranged on a wiring pattern so as to be substantially perpendicular to the wiring pattern. An external terminal can be inserted and connected to the cylindrical external terminal communication section. The cylindrical external terminal communication section allows the inserted external terminal to be electrically connected to the wiring pattern. A taper is formed at, at least, one end of the cylindrical external terminal communication section, which one end is joined to the wiring pattern.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: February 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshiko Obiraki, Seiji Oka, Osamu Usui, Yasushi Nakayama, Takeshi Oi
  • Patent number: 8922011
    Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: December 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Takatoshi Osumi, Daisuke Sakurai
  • Patent number: 8907481
    Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Patent number: 8841559
    Abstract: To prevent the breakage of the joint between a ceramic substrate and a glass epoxy substrate. The copper column is formed by a wiredrawing step for drawing a copper wire formed linearly to a predetermined diameter; a cutting step for cutting the copper wire, which has been drawn in the wire drawing step, in a predetermined length; a pressing step for pressing one end of the copper wire, which has been cut in the cutting step, in a longitudinal direction to form a copper column member; and an annealing step for annealing the copper column member, which has been formed in the pressing step, by maintaining a heating period of 60 minutes or longer at 600° C. or higher. Thereby, the Vickers hardness of the copper column becomes is 55 HV or less and the copper column is softened.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: September 23, 2014
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Yutaka Chiba, Shinichi Nomoto, Koji Watanabe
  • Patent number: 8836107
    Abstract: A plastic SON/QFN package (300) for high power has a pair of oblong metal pins (320, 321) exposed from a surface of the plastic (301), the pins straddling a corner (302) of the package; each pin has a long axis (320a, 321a), the long axes of the pair forming a non-orthogonal angle. Package (300) further includes a chip assembly pad (310), acting as a thermal spreader.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Patent number: 8823170
    Abstract: A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Pei-Chun Tsai, Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen