Methods and structures for discharging plasma formed during the fabrication of semiconductor device
Methods and structures for discharging plasma formed during the fabrication of semiconductor device are disclosed. The semiconductor device includes a wordline, a common ground line and a fuse structure for electrically coupling the wordline and the common ground line until a break signal is applied via the fuse structure.
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This application claims priority from Japanese patent application 2006-353414 filed on Dec. 27, 2006.FIELD OF TECHNOLOGY
The present invention relates to methods and structures for discharging plasma formed during the fabrication of semiconductor device.BACKGROUND
In a non-volatile memory, such as a flash memory, a transistor which constitutes a memory cell has a floating gate or an insulating film which is called a charge storage layer. Data is stored by accumulating electric charges in the charge storage layer, which is based on a silicon-oxide-nitride-oxide-silicon (SONOS) structure.
U.S. Pat. No. 6,011,725 discloses an exemplary SONOS flash memory based on a virtual ground memory, which is operated by switching between a source and a drain.
Electric charges can be accumulated in two charge storage regions of C1 and C2 in the trapping layer 16 above the regions adjacent to the bit lines 12.
The accumulation of electric charges to the trapping layer is made, if the gate electrode 22a is kept at a positive voltage and the trapping layer 16 is infused with high energy electrons energized by another voltage applied between the bit lines 12. Meanwhile, the erasure of electric charges in the trapping layer 16 is made, if the gate electrode 22a is kept at a negative voltage and the trapping layer 16 is infused with holes (e.g., of electrons and holes ionized by high energy electrons) energized by another voltage applied between the bit lines 12. By switching between the source and drain, electric charges at the right and left side of the charge storage regions can be accumulated and erased.
In a non-volatile memory having a charge storage layer, there have been cases of electric charges being accumulated in the charge storage layer during manufacturing. Electric charges may be accumulated and erased when the trapping layer 16 is infused with high energy electrons and holes between the bit lines 12 during the manufacturing of a memory device.
The unintended trapping becomes problematic when the electric charges 62 remain in the vicinity of the center of a semiconductor substrate 10 between the bit lines 12 since the electric charges cannot be easily erased during the normal operation of the memory.SUMMARY
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
An embodiment described in the detailed description is directed to a semiconductor device comprising a wordline, a common ground line and a fuse structure for electrically coupling the wordline and the common ground line until a break signal is applied via the fuse structure.
In another embodiment described in the detailed description is directed to a semiconductor device comprising a wordline formed on a portion of a silicon substrate, an interlayer insulating film formed above the wordline and the silicon substrate, an interconnect formed above the interlayer insulating film, a metal plug formed via the interlayer insulating film for electrically coupling the interconnect layer and the wordline, and a thermal variable resistor formed via the interlayer insulating film for controlling an electrical connection between the interlayer insulating film and the silicon substrate.
As illustrated in the detailed description, other embodiments pertain to methods and structures that provide an improved dissipation of electrical charges formed during the fabrication of semiconductor chips. By using a fuse or thermally variable resistor, the embodiments provide semiconductor devices with an improved plasma dissipation technology.
Example embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.DETAILED DESCRIPTION
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the claims. Furthermore, in the detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is herein, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Unless specifically stated otherwise as apparent from the following discussions, is appreciated that throughout the present application, discussions utilizing terms such as “forming,” “performing,” “producing,” “depositing,” or “etching,” or the like, refer to actions and processes of semiconductor device fabrication.
Briefly stated, embodiments efficiently discharge electrical charges formed during the manufacturing of a semiconductor device, such as a flash memory device. By forming structures that aid the dissipation of electrical charges accrued during the formation of various layers or components of the semiconductor device to either an electrical ground or to a silicon substrate of the semiconductor device, programming errors can be reduced. This is made possible by implementing a fuse structure or a thermally variable resistor structure within the semiconductor device.First Embodiment
A first embodiment of the present invention pertains to a fuse structure that is coupled with a gate electrode during the manufacturing of a flash memory but is physically cut off when the flash memory is in use.
In one example embodiment, the flash memory has the fuse 40 which is coupled with the word line 22 (e.g., gate electrode), and the fuse 40 is grounded to the semiconductor substrate 10 during the manufacturing process. Consequently, as illustrated in
As illustrated in
Furthermore, as illustrated in
The conductive layer formed above the polysilicon layer 44 can be of any conductive materials and not limited to the metal silicide layer 46. As illustrated in
A second embodiment of the present invention pertains to a thermally variable resistive structure that is conductive with a gate electrode during the manufacturing of a flash memory but becomes non-conductive when the flash memory is in use.
The TVRS 56 contains a material which is non-conductive at a temperature maintained during the operation of the flash memory (e.g., when a voltage is applied to the gate electrode), but becomes conductive at a higher temperature than the operational temperature. For example, flash memories generally operate at a temperature below 150 degrees Celsius. the manufacturing process, A wafer is usually processed at approximately 400 degrees Celsius during the manufacturing stage. Oxidized nickel (NiO) and cobalt oxide (CoO) are non-conductive at a resistivity of 104 ohms-cm at temperatures below 150 degrees Celsius, but become conductive as phase displacements occur at 247 degrees Celsius. Therefore, a material which contains NiO or CoO may be used for the TVRS 56.
A dry etching process of the interconnection layer 30 is illustrated in
The flash memory in accordance with the second embodiment, as illustrated in
In an alternative embodiment, the TVRS 56 may be directly coupled with the word line 22. However, it is preferable to connect the TVRS 56 between the interconnection layer 30 and the semiconductor substrate 10 in parallel with the metal plug 26. Since the TVRS 56 is formed longitudinally, the size of the flash memory chip may be reduced.
As illustrated in
As described herein, the TVRS 56 may be formed in the shape of the upside down trapezoid inside the contact hole 54. Alternatively, the shape of the TVRS 56 may be a rectangle. The rectangular fuse may work better when the voltage or current flowing through it is large. Since the TVRS 56 is closer to the surface of the interlayer insulating film 24 which is exposed to plasma and whose temperature tends to raise easily, the TVRS 56 is sure to become conductive.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
1. A semiconductor device comprising:
- a wordline;
- a common ground line; and
- a fuse structure directly contacting the wordline and the common ground line to electrically couple the wordline and the common ground line, wherein the wordline and the common ground line are electrically uncoupled when the fuse structure receives a break signal.
2. The semiconductor device of claim 1, wherein the fuse structure comprises a non-doped silicon layer and a metal silicide formed on the non-doped silicon layer.
3. The semiconductor device of claim 2, wherein the metal silicide comprises one of cobalt silicon and titanium silicon.
4. The semiconductor device of claim 1, wherein the common ground line comprises a doped-silicon layer and a metal silicide formed above the doped-silicon.
5. The semiconductor device of claim 1, wherein the wordline is coated with a metal silicide.
6. The semiconductor device of claim 1, further comprising:
- an interlayer insulating layer formed above the wordline, the fuse structure, and the common ground line;
- an interconnect layer formed above the interlayer insulating layer; and
- a metal plug electrically coupling the interconnect layer with the wordline, the fuse structure and the common ground.
7. The semiconductor device of claim 1, wherein the break signal comprises a voltage signal between 2.5 volts and 5 volts or a current signal between 10 mA and 20 mA.
International Classification: H01L 31/058 (20060101);