FET structures with trench implantation to improve back channel leakage and body resistance
A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.
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This application is a divisional of U.S. patent application Ser. No. 12/899,635 entitled “FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE”, filed Oct. 7, 2010, the disclosure of which is incorporated by reference herein.
BACKGROUNDThe present invention relates to the field of improving the parasitic leakage of MOSFET (metal oxide semiconductor field effect transistor) structures for semiconductors and, more particularly, relates to FET (field effect transistor) structures and processes having features to reduce leakage in the back channel of the FET, to reduce leakage under the source/drain junction and to reduce FET body resistance without interfering with the threshold voltage of the FET structure.
In present day semiconductor technology and beyond, high peak junction field, back channel leakage, and under junction leakage are impacting semiconductor reliability. This is particularly true for eDRAM which need back gating or side gating well controlled for high retention and yield and SRAM semiconductor structures. This is also true for analog devices which need low body resistance but the low body resistance may interfere with threshold voltage.
BRIEF SUMMARYThe various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing, according to a first aspect of the exemplary embodiments, a field effect transistor (FET) structure on a semiconductor substrate including a gate structure having a spacer on a semiconductor substrate wherein the semiconductor substrate is a semiconductor on insulator substrate comprising a semiconductor layer on a buried oxide layer; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material such that a dopant concentration of the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain; and halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack and being in contact with the buried oxide layer.
According to a second aspect of the exemplary embodiments, there is provided a field effect transistor (FET) structure on a semiconductor substrate including a gate structure having a spacer on a semiconductor substrate wherein the semiconductor substrate is a semiconductor on insulator substrate comprising a semiconductor layer on a buried oxide layer; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material, the FET structure having a body portion underneath the gate structure and between the recessed source and drain; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack and in a bottom part of the body portion and being in contact with the buried oxide layer; and implanted junction butting underneath the bottom of each of the recessed source and drain and the junction butting being in contact with the buried oxide layer, the junction butting being separate and distinct from the halo implanted regions.
According to a third aspect of the exemplary embodiments, there is provided a field effect transistor (FET) structure on a semiconductor substrate including a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material, the FET structure having a body portion underneath the gate structure and between the recessed source and drain; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack and in a bottom part of the body portion; and implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions.
The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
Referring to the Figures in more detail, and particularly referring to
The semiconductor material that makes up semiconductor substrate 104 if it is a bulk semiconductor may include but not be limited to group IV semiconductors such as silicon, silicon germanium or germanium, a III-V compound semiconductor, or a II-VI compound semiconductor. Similarly, in the preferred exemplary embodiment, semiconductor layer 114 and semiconductor wafer 110 may include but not be limited to group IV semiconductors such as silicon, silicon germanium or germanium, a III-V compound semiconductor, or a II-VI compound semiconductor. Buried oxide layer 112 may be silicon oxide or other dielectric materials.
The remainder of the discussion will focus on the SOI structure shown in
Gate structure 102 includes a gate stack 106 and first spacers 108. In an exemplary embodiment, the gate stack 106 may comprise a high k dielectric material in contact with SOI layer 114, metal gate material in contact with the high k dielectric material and polysilicon material in contact with the metal gate material. The gate stack 106 may be formed by blanket depositing layers of high k dielectric material, metal gate material and polysilicon material and then defining the gate stack 106 by etching away the portions of the layers that are not needed for the gate stack 106. The etching may be done by reactive ion etching. The materials for gate stack 106 and the method for forming the gate stack 106 are conventional. For purposes of illustration and not limitation, the high k dielectric material may include but not be limited to nitride hafnium silicate, hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide. For purpose of illustration and not limitation, the metal gate materials may include but not be limited to metals such as tungsten, nickel, cobalt and copper; carbides such as titanium carbide, zirconium carbide, tantalum carbide and tungsten carbide; and nitrides such as titanium nitride and tantalum nitride.
An insulating material, such as silicon nitride is deposited, defined and then reactive ion etched to form first spacers 108.
Referring now to
Referring now to
Halo implants 126 are done by tilt angle implanting at about 0 to 45 degrees, typically 15 to 30 degrees, of, for example, boron or boron difluoride for an NFET or arsenic or phosphorus for a PFET, into the bottom of source recess 122 and drain recess 124. The halo implants 126 through the source recess 122 and drain recess 124 shut off back gating leakage (back channel leakage) or side gating leakage, such as that from adjacent node gating, which is critical for high performance, long retention devices such as DRAM. As shown in
Junction butting implants 130 are done by vertical implanting 132 of, for example, arsenic or phosphorus for an NFET or boron or boron difluoride for a PFET, at the bottom of source recess 122 and drain recess 124. In a preferred exemplary embodiment, junction butting implants 130 are in contact with BOX layer 112. As shown in
Referring now to
The semiconductor structure 100 then undergoes dose activation at about 800 to 1000° C. for about 1 millisecond to result in the structure shown in
Processing of the semiconductor structure 100 then continues with further integrated circuit formation processing and back end of the line processing to form completed semiconductor devices.
It will be apparent to those skilled in the art having regard to this disclosure that other modifications of the exemplary embodiments beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.
Claims
1. A field effect transistor (FET) structure on a semiconductor substrate comprising:
- a gate structure having a spacer on a semiconductor substrate wherein the semiconductor substrate is a semiconductor on insulator substrate comprising a semiconductor layer on a buried oxide layer;
- an extension implant underneath the gate structure;
- a recessed source and a recessed drain filled with a doped epitaxial material such that a dopant concentration of the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain; and
- halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack and being in contact with the buried oxide layer.
2. The FET structure of claim 1 further comprising implanted junction butting underneath the bottom of each of the recessed source and drain and the junction butting being in contact with the buried oxide layer, the junction butting being separate and distinct from the halo implanted regions.
3. The FET structure of claim 1 wherein the doped epitaxial material in each of the recessed source and drain comprises a plurality of doped epitaxial layers.
4. The FET structure of claim 3 wherein a dopant concentration of the plurality of doped epitaxial layers varies from layer to layer.
5. The FET structure of claim 2 wherein the junction butting comprises arsenic, phosphorus, boron or boron difluoride.
6. The FET structure of claim 1 having a body portion underneath the gate structure and between the recessed source and drain and having the halo implants in a low part of the body portion so that body resistance is reduced without increasing threshold voltage.
7. The FET structure of claim 6 wherein the halo implanted regions are wholly within the body portion.
8. A field effect transistor (FET) structure on a semiconductor substrate comprising:
- a gate structure having a spacer on a semiconductor substrate wherein the semiconductor substrate is a semiconductor on insulator substrate comprising a semiconductor layer on a buried oxide layer;
- an extension implant underneath the gate structure;
- a recessed source and a recessed drain filled with a doped epitaxial material, the FET structure having a body portion underneath the gate structure and between the recessed source and drain;
- halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack and in a bottom part of the body portion and being in direct contact with the buried oxide layer; and
- implanted junction butting underneath the bottom of each of the recessed source and drain and the junction butting being in contact with the buried oxide layer, the junction butting being separate and distinct from the halo implanted regions.
9. The FET structure of claim 8 wherein the doped epitaxial material in each of the recessed source and drain comprises a plurality of doped epitaxial layers.
10. The FET structure of claim 9 wherein a dopant concentration of the plurality of doped epitaxial layers varies from layer to layer.
11. The FET structure of claim 9 wherein a dopant concentration of the plurality of doped epitaxial layers is graded from a lower dopant concentration at a side of the source and drain recesses to a higher dopant concentration at a center of the source and drain recesses.
12. The FET structure of claim 8 wherein a dopant concentration of the doped epitaxial material in each of the source and drain recesses is graded from a lower dopant concentration at a side of the source and drain recesses to a higher dopant concentration at a center of the source and drain recesses.
13. The FET structure of claim 8 wherein the junction butting comprises arsenic, phosphorus, boron or boron difluoride.
14. The FET structure of claim 8 wherein the halo implanted regions are wholly within the body portion.
15. A field effect transistor (FET) structure on a semiconductor substrate comprising:
- a gate structure having a spacer on a semiconductor substrate;
- an extension implant underneath the gate structure;
- a recessed source and a recessed drain filled with a doped epitaxial material, the FET structure having a body portion underneath the gate structure and between the recessed source and drain;
- halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack and in a bottom part of the body portion and being in direct contact with a buried oxide layer; and
- implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions.
16. The FET structure of claim 15 wherein the doped epitaxial material in each of the source and drain recesses comprises a plurality of doped epitaxial layers.
17. The FET structure of claim 16 wherein a dopant concentration of the plurality of doped epitaxial layers varies from layer to layer.
18. The FET structure of claim 16 wherein a dopant concentration of the plurality of doped epitaxial layers is graded from a lower dopant concentration at a side of the source and drain recesses to a higher dopant concentration at a center of the source and drain recesses.
19. The FET structure of claim 15 wherein a dopant concentration of the doped epitaxial material in each of the source and drain recesses is graded from a lower dopant concentration at a side of the source and drain recesses to a higher dopant concentration at a center of the source and drain recesses.
20. The FET structure of claim 15 wherein the halo implanted regions are wholly within the body portion.
8236632 | August 7, 2012 | Fried et al. |
20090256201 | October 15, 2009 | Yang et al. |
Type: Grant
Filed: Mar 21, 2012
Date of Patent: Aug 19, 2014
Patent Publication Number: 20120187490
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: David M. Fried (Brewster, NY), Jeffrey B. Johnson (Essex Junction, VT), Kevin McStay (Hopewell Junction, NY), Paul Parries (Wappingers Falls, NY), Chengwen Pei (Danbury, CT), Gan Wang (Fishkill, NY), Geng Wang (Stormville, NY), Yanli Zhang (San Jose, CA)
Primary Examiner: Seahvosh Nikmanesh
Application Number: 13/426,547
International Classification: H01L 29/78 (20060101);