Semiconductor module
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Description
The broken lines shown in the drawings represent portions of the semiconductor module that form no part of the claimed design.
Claims
The ornamental design for a semiconductor module, as shown and described.
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Patent History
Patent number: D810036
Type: Grant
Filed: Mar 27, 2017
Date of Patent: Feb 13, 2018
Assignee: FUJI ELECTRIC CO., LTD. (Kawasaki)
Inventors: Satoshi Sawayanagi (Matsumoto), Masahiro Taoka (Matsumoto), Tomofumi Oose (Matsumoto), Hideaki Takahashi (Omachi)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/598,481
Type: Grant
Filed: Mar 27, 2017
Date of Patent: Feb 13, 2018
Assignee: FUJI ELECTRIC CO., LTD. (Kawasaki)
Inventors: Satoshi Sawayanagi (Matsumoto), Masahiro Taoka (Matsumoto), Tomofumi Oose (Matsumoto), Hideaki Takahashi (Omachi)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/598,481
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)