Semiconductor module
Description
The ornamental design of the present disclosure is a semiconductor module on which power semiconductor elements and the like may be mounted. A plurality of pin-shaped terminals protrudes from the top surface. Each end in a longitudinal direction includes a mounting hole.
Claims
The ornamental design for a semiconductor module, as shown and described.
Referenced Cited
U.S. Patent Documents
| 5408128 | April 18, 1995 | Furnival |
| 5410450 | April 25, 1995 | Iida et al. |
| D364383 | November 21, 1995 | Yamada et al. |
| D364384 | November 21, 1995 | Shimizu et al. |
| D364385 | November 21, 1995 | Shimizu et al. |
| 6078501 | June 20, 2000 | Catrambone et al. |
| D441726 | May 8, 2001 | Sofue et al. |
| D441727 | May 8, 2001 | Sekimoto |
| 6521983 | February 18, 2003 | Yoshimatsu et al. |
| D476959 | July 8, 2003 | Yamada et al. |
| D525215 | July 18, 2006 | Hisaishi et al. |
| D539761 | April 3, 2007 | Takahashi et al. |
| D548202 | August 7, 2007 | Takahashi et al. |
| D548203 | August 7, 2007 | Takahashi et al. |
| D587662 | March 3, 2009 | Soutome et al. |
| D589012 | March 24, 2009 | Soyano et al. |
| D606951 | December 29, 2009 | Soyano et al. |
| D653633 | February 7, 2012 | Soyano |
| D653634 | February 7, 2012 | Soyano |
| D674760 | January 22, 2013 | Mochizuki et al. |
| D686174 | July 16, 2013 | Soyano |
| D689446 | September 10, 2013 | Soyano |
| 8526199 | September 3, 2013 | Matsumoto et al. |
| D699693 | February 18, 2014 | Otsuka et al. |
| D703625 | April 29, 2014 | Lim et al. |
| D704670 | May 13, 2014 | Chen et al. |
| D704671 | May 13, 2014 | Chen et al. |
| D705184 | May 20, 2014 | Takahashi et al. |
| D706232 | June 3, 2014 | Nakamura |
| D710317 | August 5, 2014 | Chen et al. |
| D710318 | August 5, 2014 | Chen et al. |
| D710319 | August 5, 2014 | Chen et al. |
Patent History
Patent number: D721340
Type: Grant
Filed: Jun 21, 2013
Date of Patent: Jan 20, 2015
Assignee: Fuji Electric Co., Ltd. (Kawasaki-shi, Kanagawa)
Inventor: Hideyo Nakamura (Kawasaki)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/458,667
Type: Grant
Filed: Jun 21, 2013
Date of Patent: Jan 20, 2015
Assignee: Fuji Electric Co., Ltd. (Kawasaki-shi, Kanagawa)
Inventor: Hideyo Nakamura (Kawasaki)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/458,667
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)