Voidless (e.g., Solid) Patents (Class 174/264)
  • Patent number: 6972383
    Abstract: A multilayered circuit board has good imbedding properties for circuit patterns, and an interlayer insulating material having superior adhesive force and interlayer insulating properties. In a multilayered circuit board wherein interlayer connection is achieved by the contact of minute pointed protrusions, provided on a first conductive circuit layer, with a second conductive circuit layer, interlayer insulation is achieved by a film having a three-layer structure, comprising a thermoplastic film inserted between a pair of thermosetting adhesive layers.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: December 6, 2005
    Assignee: Nippon Mektron, Ltd.
    Inventor: Fumio Akama
  • Patent number: 6972070
    Abstract: A heated and pressed printed wiring board is made by filling via holes formed in layers of insulating film of the wiring board with an interlayer conducting material. The insulating film is stacked with conductor patterns, and each conductor pattern closes a via hole. The interlayer conducting material forms a solid conducting material in the via holes after a heating a pressing procedure. The solid conducting material includes two types of conducting materials. The first type of conducting material includes a metal, and the second type of conductive material includes an alloy formed by the metal and conductor metal of the conductor patterns. The conductor patterns are electrically connected reliably without relying on mere mechanical contact.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: December 6, 2005
    Assignee: Denso Corporation
    Inventors: Yoshitaro Yazaki, Yoshihiko Shiraishi, Koji Kondo, Toshikazu Harada, Tomohiro Yokochi
  • Patent number: 6936769
    Abstract: An infrared emissive first insulating portion, which radiates heat transferred from a WCSP corresponding to an electronic part to a first conductive portion as infrared radiation with high efficiency, is formed on the first conductive portion lying in a through hole provided in a printed wiring board with the WCSP mounted thereon.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: August 30, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takashi Noguchi, Masahiro Machida, Makoto Terui, Yuichi Deushi
  • Patent number: 6933450
    Abstract: Signal wiring conductors are provided at opposing positions on the upper surface of the uppermost dielectric layer and on the lower surface of the bottommost dielectric layer, and grounding conductors surrounding grounding-conductor non-forming areas are provided on the upper surfaces of intermediate dielectric layers and the bottommost dielectric layer. These grounding conductors form an electromagnetically shielded space by being connected by grounding-conductor via conductors vertically penetrating the respective dielectric layers around the grounding-conductor non-forming areas, and signal via conductors are so provided in the respective dielectric layers as to penetrate this electromagnetically shielded space.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: August 23, 2005
    Assignee: Kyocera Corporation
    Inventors: Takehiro Okumichi, Hiroyuki Tanaka, Yuji Kishida
  • Patent number: 6930257
    Abstract: An integrated circuit substrate having laminated laser-embedded circuit layers provides a multi-layer high-density mounting and interconnect structure for integrated circuits. A prepared substrate, which may be a rigid double-sided dielectric or film dielectric with conductive patterns plated, etched or printed on one or both sides is laminated with a thin-film dielectric on one or both sides. The thin-film is laser-ablated to form channels and via apertures and conductive material is plated or paste screened into the channels and apertures, forming a conductive interconnect pattern that is isolated by the channel sides and vias through to the conductive patterns on the prepared substrate. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: August 16, 2005
    Assignee: Amkor Technology, Inc.
    Inventors: David Jon Hiner, Ronald Patrick Huemoeller, Sukianto Rusli
  • Patent number: 6930258
    Abstract: Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: August 16, 2005
    Assignee: Ibiden Co., Ltd.
    Inventors: Yogo Kawasaki, Hiroaki Satake, Yutaka Iwata, Tetsuya Tanabe
  • Patent number: 6915566
    Abstract: A method for the fabrication of a double-sided electrical interconnection flexible circuit (200) particularly useful as a substrate for an area array integrated circuit package. A copper matrix with studs (203) is pressed through a dielectric film (201) having a copper layer on the opposite surface, thereby forming an intermediate structure for a flex circuit with self-aligned solid copper vias in a one step process. The contacts are reinforced by plating both surfaces with a layer of copper, and conventional processes are used to complete the circuit patterning.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: July 12, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, John E. Cotugno, Robert M. Fritzsche, Robert A. Sabo, Christopher M. Sullivan, David W. West
  • Patent number: 6914199
    Abstract: A multilayer wiring board assembly, a multilayer wiring board assembly component, and a method of manufacture thereof. The multilayer wiring board assembly is formed by laminating together a plurality of multilayer wiring board assembly components having a flexible resin film with a copper foil bonded to one surface and an adhesive layer bonded to the other surface, opening a through hole in the copper plated resin film through the copper foil, resin film, and the adhesive layer, filling the through hole with a conductive paste projecting from the adhesive layer and laterally extending beyond through hole opening of the copper foil.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: July 5, 2005
    Assignee: Fujikura Ltd.
    Inventors: Reiji Higuchi, Shouji Itou, Osamu Nakao
  • Patent number: 6904674
    Abstract: A printed wiring board, particularly, an interposer 20 for a chip scale package, comprising an outer insulator layer 22 having outer electrodes 31, a conductor layer 21, and an inner insulator layer 23 having inner electrodes 27, the electrodes 31 and/or 27 having been formed by electroplating using, as a negative electrode, a metal plate 32 that has been provided on the outer insulator layer 22 and removed after the electroplating. Having no plating leads, the printed wiring board has the electrodes in an orderly array at a fine pitch and a high density.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: June 14, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Kazunori Mune, Hirofumi Fujii, Satoshi Tanigawa
  • Patent number: 6900395
    Abstract: Replacements of thick film pads with smaller, thinner, metal contacts or straps are used to eliminate many of the stress-related failure modes associated with the larger contact pads. These straps allow for a more simplified manufacturing process than that associated with an anchored I/O pad configuration. A single via, electrically connected to a plurality of vias in a substrate layer above, is introduced to enhance the reliability of the signal net, and provides for higher frequency applications through reduction in parasitic capacitance and electrical leakage. The straps are directionally located toward the substrate center. Once the locations of the internal strap vias are redirected to lower local distance-to-neutral points, still within the same I/O capture pad, and directed towards the center of the substrate, single vias are then placed at the strap end closest the substrate center.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 31, 2005
    Assignee: International Business Machines Corporation
    Inventors: Janet L. Jozwiak, Gregory B. Martin, Linda L. Rapp, Srinivasa S. Reddy
  • Patent number: 6890617
    Abstract: A porous adhesive sheet 1 having plural through holes 2 running in about parallel with each other in the thickness direction A of an adhesive organic film 3, wherein the through holes have about congruent sections in the diameter direction from one opening 2a to the other opening 2b and a production method thereof, and a semiconductor wafer with a porous adhesive sheet 31, which includes a semiconductor wafer 32 having an electrode 33, the porous adhesive sheet 1 adhered to the semiconductor wafer, and a conductive part 34 formed by filling a through hole 2 located on the electrode 33 with a conductive material, and a production method thereof are provided.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: May 10, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Miho Yamaguchi, Yuji Hotta
  • Patent number: 6884945
    Abstract: A multi-layer printed circuit board on which insulation resin layers and circuit pattern layers are alternatively stacked to form multiple layers, including: an insulation resin layer; a circuit pattern formed at the upper surface of the insulation resin layer; a blind via hole formed penetrating the insulation resin layer and the circuit pattern; a plated layer formed at the upper surface of the circuit pattern, at the inner wall face and the bottom of the blind via hole; an inner lead bump pad formed at the surface of the plated layer which is exposed to the lower surface of the insulation resin layer; and an outer lead bump pad formed on the circuit pattern which is formed at the upper surface of the insulation resin layer, whereby the problem of defective attachment of a bump due to a void present in a blind via hole is eliminated.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: April 26, 2005
    Assignee: LG Electronics Inc.
    Inventors: Dock-Heung Kim, Yong-Il Kim
  • Patent number: 6878305
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Patent number: 6879492
    Abstract: A method and structure for forming an electronic structure that comprises a redistribution structure on a circuitized substrate. The redistribution structure includes N dielectric layers (N ?2) and N metal planes formed in the following sequence: dielectric layer 1 on a metallic plane that exists on a surface of the substrate, metal plane 1 on dielectric layer 1, dielectric layer 2 on dielectric layer 1 and metal plane 1, metal plane 2 on the dielectric layer 2, . . . , dielectric layer N on dielectric layer N-1 and metal plane N-1, and metal plane N on the dielectric layer N. Metal planes or metallic planes may include signal planes, power planes, ground planes, etc. A microvia structure, which is formed through the N dielectric layers and electrically couples metal plane N to the metallic plane, includes a microvia or a portion of a microvia through each dielectric layer.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: April 12, 2005
    Assignee: International Business Machines Corporation
    Inventors: David J. Alcoe, Kim J. Blackwell
  • Patent number: 6872894
    Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: March 29, 2005
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
  • Patent number: 6864435
    Abstract: A flexible electronic, Radio Frequency Identification (RF ID) or display device and methods of making the same. The flexible electronic, Radio Frequency Identification (RF ID) or display device comprises a flexible substrate having a top surface and a bottom surface. The top surface comprises electrical components. The flexible substrate comprises openings cutting therethrough from the top surface to the bottom surface. A conductive layer is coupled to the flexible substrate wherein the openings expose at least a portion of the conductive layer. The openings are filled with conductive elements to make first electrical contacts to at least a portion of the conductive layer and second electrical contacts to the electrical components on the flexible substrate.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: March 8, 2005
    Assignee: Alien Technology Corporation
    Inventors: Anno Hermanns, Randolph W. Eisenhardt, Glenn W. Gengel
  • Patent number: 6855625
    Abstract: Single-sided conductor patterned films are prepared, each of which has a conductor pattern formed only one side of a resin film and via hole filled with conductive paste. A single-sided conductor patterned film which has a conductor pattern formed only one side of a resin film and an opening formed in the resin film so as to expose an electrode is laminated on the single-sided conductor patterned films. Moreover, a cover layer with an opening to expose an electrode is laminated on a bottom surface of the single-sided conductor patterned films to form a laminate. Then, by pressing while heating the laminate, a multilayer substrate having the electrodes at both sides thereof can be produced.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: February 15, 2005
    Assignee: Denso Corporation
    Inventors: Koji Kondo, Tetsuaki Kamiya, Toshikazu Harada, Ryuichi Onoda, Yasutaka Kamiya, Gentaro Masuda, Yoshitaro Yazaki, Tomohiro Yokochi
  • Patent number: 6855892
    Abstract: An insulation sheet for use in producing a wiring substrate comprises, as via bole conductors, conductive paste filled in via holes formed through the insulation sheet, and a curing-starting temperature of the conductive paste is lower than a melting-starting temperature of the insulation sheet. A wiring substrate is produced by laminating such insulation sheets, that have conductive paste in via holes, and subjecting this laminate to thermo-compression bonding, wherein deformation of via holes and dislocation of the via holes, because of a molten insulation sheet, does not occur.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: February 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shingo Komatsu, Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Yoshiyuki Yamamoto
  • Patent number: 6839965
    Abstract: A method for making electrical interposers which includes the use of a stencil which is thicker than designated lower contact pads and which defines a stencil passage corresponding to each lower contact pad of each interposer. The stencil is attached to a bottom surface of an insulative layer and a conductive elastomeric material is applied to the stencil, so that the stencil passages are filled with said conductive elastomeric material. When this material has been adequately placed within the stencil passages the stencil is removed thus leaving each lower conductive pad with an attached conductive elastomeric pad.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: January 11, 2005
    Assignee: R-TEC Corporation
    Inventors: Scott Patrick Terrell, Clifton Jay Seusy, Robert Calhoun Cannon, Darrell Kent Mason, Brandon Chad Bailey, Douglas G. Hastings
  • Publication number: 20040262039
    Abstract: A wire-bonding substrate is disclosed. The wire-bonding substrate includes a first wire-bond pad and a first via that is disposed directly below the first wire-bond pad in the in the wire-bonding substrate. A package is also disclosed that includes a die that is coupled to the first wire-bonding pad. The package can include a larger substrate that is coupled to the wire-bonding substrate through an electrical connection such as a solder ball. A process of forming the wire-bonding substrate is also disclosed. The process includes via formation to stop on the wire-bond pad. A method of assembling a microelectronic package is also disclosed that includes coupling the die to the wire-bond pad. A computing system is also disclosed that includes the wire-bonding substrate.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Brian Taggart, Ronald L. Spreitzer, Robert Nickerson
  • Patent number: 6835895
    Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: December 28, 2004
    Assignee: IBIDEN Co., Ltd.
    Inventors: Motoo Asai, Yasuji Hiramatsu
  • Patent number: 6831371
    Abstract: An integrated circuit substrate having embedded wire conductors provides high-density interconnect structure for integrated circuits. Wires are shaped to form a conductive pattern and placed atop a dielectric substrate layer. Additional dielectric is electro-deposited over the wires to form an insulating layer that encapsulates the wires. One or more power planes may be embedded within the substrate and wires within the conductive pattern may be laser-welded to vertical wire stubs previously attached to a power plane. Vias may be formed by mechanically or laser drilling (or plasma or chemical etching) through any power planes and screening a copper paste into the drilled holes to form conductive paths through the holes. Via conductors may then be exposed by a plasma operation that removes dielectric, leaving the ends of the via conductors exposed. Wires within the conductive pattern may then be laser-welded to the via conductor ends.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: December 14, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli
  • Patent number: 6831236
    Abstract: A multilayer wiring board assembly, a multilayer wiring board assembly component, and a method of manufacture thereof. The multilayer wiring board assembly is formed by laminating together a plurality of multilayer wiring board assembly components, having a flexible resin film with a copper foil bonded to one surface and an adhesive layer bonded to the other surface, opening a through hole in the copper plated resin film through the copper foil, resin film, and the adhesive layer, and filling the through hole with a conductive paste projecting from the adhesive layer and laterally extending beyond through hole opening of the copper foil.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: December 14, 2004
    Assignee: Fujikura Ltd.
    Inventors: Reiji Higuchi, Shouji Itou, Osamu Nakao
  • Publication number: 20040238209
    Abstract: A multilayer wiring board comprises a metal substrate having first and second main surfaces, a copper coating applied to at least one of the first and second main surfaces of the metal substrate and having a roughened surface, and an insulating resin layer formed on the roughened surface of the copper coating. The multilayer wiring board may further comprises a wiring layer arranged on the insulating resin layer and a via extending through the insulating resin layer between the copper coating and the wiring layer.
    Type: Application
    Filed: June 26, 2003
    Publication date: December 2, 2004
    Applicant: NGK SPARK PLUG CO., LTD
    Inventors: Shinji Yuri, Tomoe Suzuki, Kazuhisa Sato, Kozo Yamazaki
  • Publication number: 20040238211
    Abstract: A through hole 2 in a circuit board 1 and to be joined to a lead 5 in a surface mounting component 6 is prepared from a material such as nickel, and palladium having a thermal conductivity equal to or less than 100 W/m.K, the circuit board 1 involving a alloy layer composed of at least a member selected from elements of solder 8, a pad 7, and the lead 5 in a solder joined site of the lead 5 and the pad 7, whereby a quantity of heat transmitted to the joined site via the through hole 2 is reduced at the time when wave-soldering is applied to the back of the circuit board 1 after the surface mounting component 6 was mounted, so that the joined site is maintained at a temperature equal to or less than a melting point of the alloy layer, and hence, exfoliation in an interface of the joined site is prevented, and reliability in the joint of the lead 5 and the pad 7 is elevated.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 2, 2004
    Inventors: Yuki Momokawa, Eiichi Kono, Masaru Saitou, Kazuhiko Tanabe
  • Patent number: 6825555
    Abstract: An object of the present invention is to provide a hot plate which is superior in thermal conductivity, is superior in temperature-rising/dropping property, particularly in temperature-dropping property, and has high cooling thermal efficiency at the time of cooling. The hot plate of the present invention is a hotplate comprising: a ceramic substrate; and a resistance heating element formed on the surface of said ceramic substrate or inside said ceramic substrate, wherein said ceramic substrate has a leakage quantity of 10−7 Pa·m3/sec (He) or less by measurement with a helium leakage detector.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: November 30, 2004
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasuji Hiramatsu, Yasutaka Ito
  • Publication number: 20040226745
    Abstract: The objective of present invention is to provide an electroplating solution capable of forming the upper face of a via-hole and the upper face of a conductor circuit in the same layer in approximately the same plane at the time of manufacturing a multilayer printed circuit board. The electroplating solution of the present invention is characterized by containing 50 to 300 g/L of copper sulfate, 30 to 200 g/L of sulfuric acid, 25 to 90 mg/L of chlorine ion, and 1 to 1000 mg/L of an additive comprising at least a levelling agent and a brightener.
    Type: Application
    Filed: June 10, 2004
    Publication date: November 18, 2004
    Applicant: IBIDEN CO., LTD.
    Inventor: Honchin En
  • Patent number: 6818836
    Abstract: A conductor pattern is formed on a resin film which is made of a thermoplastic resin. Each single-sided conductor pattern film has via-holes filled with an electrically conductive paste. A printed conductor pattern and a printed resistor are formed on a ceramic substrate. The single-sided conductor pattern films are laminated on the ceramic substrate. Then, the multilayered assembly is heated and pressed from both sides thereof to obtain a printed circuit board. During the heat and press treatment, respective single-sided conductor pattern films and the ceramic substrate bond together while the interlayer connection is obtained between the conductor patterns as well as between the conductor pattern and the printed conductor pattern.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: November 16, 2004
    Assignee: Denso Corporation
    Inventors: Yoshihiko Shiraishi, Koji Kondo
  • Patent number: 6812412
    Abstract: A multi-layer wiring board is produced by laminating a plurality of insulating layers having conductor circuits, wherein the conductor circuits of the insulating layers are electrically connected together through via-holes in insulating connection layers having no conductor circuit, and the regions other than the conductor circuits of the insulating layers and the regions other than the via-holes of the connection layers are directly joined together by press-adhering the insulating resins that constitute the respective layers.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 2, 2004
    Assignee: Fujitsu Limited
    Inventors: Souichi Obata, Kazuhiko Iijima, Yasutomo Maehara
  • Publication number: 20040211594
    Abstract: A vertical routing structure for a multi-layered substrate having a lamination structure therein. The lamination structure has at least a through hole that links up both surfaces of the lamination structure. The vertical routing structure comprises a conductive rod and a conductive layer. The conductive rod is formed inside the through-hole with the ends protruding above the respective upper and lower surface of the lamination structure. The conductive layer is positioned in the space between the interior sidewall of the through-hole and the conductive rod. The vertical routing structure on the substrate is able to reduce the area for laying the required circuits or increase the wiring density in a given area.
    Type: Application
    Filed: December 15, 2003
    Publication date: October 28, 2004
    Inventors: Kwun-Yao Ho, Moriss Kung
  • Patent number: 6809269
    Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: October 26, 2004
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
  • Patent number: 6799369
    Abstract: A printed circuit board of the present invention is formed of an electrical insulating base material with through holes that are formed in a thickness direction of the electrical insulating base material and are filled with an electrical conductor; the electrical insulating base material including a core layer formed by impregnating a holder with a resin and resin layers formed on both sides of the core layer; and wiring layers that are formed on both surfaces of the electrical insulating base material into a predetermined pattern and are electrically connected to each other by the electrical conductor. The wiring layer is embedded in at least one of the resin layers. The resin layers on the both sides have different thicknesses from each other, and a thinner layer out of the resin layers has a thickness equal to or smaller than a mean particle diameter of an electrically conductive filler contained in the electrical conductor.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shozo Ochi, Fumio Echigo, Yoji Ueda
  • Patent number: 6797367
    Abstract: A multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring, can be ideally applied to low volume high mix manufacturing configurations, and also has little impact on the environment is provided, together with a semiconductor device mounting board using such a multilayer wiring board, and a method of manufacturing such a multilayer wiring board. In the multilayer wiring board, grooves for forming a wiring circuit and via holes are formed in an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: September 28, 2004
    Assignees: Sony Corporation, Mitsubishi Plastics, Inc.
    Inventors: Minoru Ogawa, Masahiro Izumi, Shigeyasu Itoh, Shingetsu Yamada, Shuuji Suzuki, Hiroo Kurosaki
  • Publication number: 20040182603
    Abstract: The present invention provides an inner layer structure of a circuit board. The inner layer structure of the present invention uses column-shaped or conned-shaped bumps to replace the conventional PTH process, and uses the bumps as media to electrically connect two adjacent patterned conducting layers. Hence, inner layer structure of the present invention can effectively simplify the layout design and the fabrication complexity, and increase the layout density of the circuit board.
    Type: Application
    Filed: July 24, 2003
    Publication date: September 23, 2004
    Inventors: Tz-Jang Tseng, Tsung-Chin Chiu
  • Patent number: 6794585
    Abstract: A method includes the steps of forming a first metal foil (82) on a surface of an insulator substrate (1a), drilling, with a thermosetting resin film (84) temporarily fixed to an opposite surface of the substrate, a through hole (86) simultaneously in the first foil, the substrate, and the resin film, simultaneously heating and vacuum-pressing the first foil, the substrate, the resin film, and a second metal foil (87) brought into contact with the resin film to obtain an intermediate board in which a bottom of the through hole is covered with the second foil and has a corner with a corner rounded portion (93) formed by the resin film, and forming a metal plating layer (95) on the first and the second foils, on the bottom and an inner wall of the through hole, and on the corner rounded portion to obtain a final printed wiring board.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: September 21, 2004
    Assignee: Japan Radio Co., LTD
    Inventors: Shigetoshi Abe, Tomoko Kato, Yasuo Sato, Takashi Itagaki, Kenji Matsumoto
  • Publication number: 20040178000
    Abstract: A standardized or partial standardized circuit board core comprises at least a dielectric core layer and a plurality of conductive posts, in which the dielectric layer has a first surface and a related second surface. The conductive posts pass through the dielectric core layer and connect to the first and second surfaces of the dielectric layer respectively. The conductive posts are array arranged or arranged in a constant distance form in the dielectric core layer. Moreover, the standardized or partial standardized circuit board core further includes two conductive layers, which are covered on the first and second surfaces of the dielectric core layer.
    Type: Application
    Filed: September 4, 2003
    Publication date: September 16, 2004
    Inventor: Tzyy-Jang Tseng
  • Patent number: 6791035
    Abstract: An interposer to couple a microelectronic device package to a motherboard is formed from a PCB substrate. Multiple via holes are drilled through a copper-clad PCB substrate and then coated inside with copper. The copper surface coating is etched to form multiple traces. In one embodiment, the substrate is cut through each row of via holes and between each row of via holes to produce multiple individual beam-and-trace interposers. Two or more such interposers may be affixed together to form a beam-and-trace interposer array. Alternatively, the substrate is not cut into strips, and each via hole is filled completely with a conductive material to form an array of solid conductive columns through the substrate.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Thomas E. Pearson, George L. Arrigotti, Raiyomand F. Aspandiar, Christopher D. Combs
  • Patent number: 6780493
    Abstract: In a wiring board, predetermined wiring patterns which are formed on both sides of an insulation substrate are electrically connected by an electrically conductive material provided in through holes formed through the insulation substrate. The insulation substrate is composed of a resin impregnated fibrous sheet and a heat resistant film. The present invention solves the problems of the wiring board which are caused by irregularities on the surface of the resin impregnated fibrous sheet. The problems include insufficient adhesion strength between the wiring pattern and the insulation substrate or the limitation of fineness of the wiring pattern due to the irregularities on the surface of the printed wiring board which are formed upon the thermocompression bonding process.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: August 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Osamu Noda, Hideo Hatanaka, Kazunori Sakamoto, Masanaru Hasegawa
  • Patent number: 6777620
    Abstract: A substrate of the present invention includes pads which are provided on the surface of said substrate; and surface layers which are kept to the ground potential and cover the surface of said substrate except said pads and their peripheral. Another substrate of the present invention includes a part of circuit which is provided on the surface of said substrate; and a surface layers which are kept to the ground potential and cover the surface of said substrate except said part of circuit and its peripheral.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: August 17, 2004
    Assignee: NEC Corporation
    Inventor: Takashi Abe
  • Publication number: 20040154830
    Abstract: In the ceramic circuit board, within the through hole of the ceramic substrate is arranged the metal column which is 0 to 150 &mgr;m shorter relative to the thickness of the ceramic substrate; the metal circuit plates are attached to both surfaces of the ceramic substrate to stop up the through hole; and the metal column and the metal circuit plate are bonded together via the brazing material. For its manufacture, the metal column with brazing material is used that is made 40 to 140 &mgr;m longer relative to the thickness of the ceramic substrate by being formed of the metal column which is 0 to 150 &mgr;m shorter relative to the thickness of the ceramic substrate and has its both ends coated with the brazing material.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 12, 2004
    Applicant: KYOCERA CORPORATION
    Inventor: Ken Furukuwa
  • Patent number: 6770822
    Abstract: A high frequency device packing method and package are described wherein coaxial structures are formed from the high frequency device to the via. A coaxial via structure and a micro-coaxial bonding wire are described.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: August 3, 2004
    Assignee: Bridgewave Communications, Inc.
    Inventors: Eliezer Pasternak, Sean Cahill, Bance Hom
  • Patent number: 6768189
    Abstract: A packaged die (112) for an integrated circuit (62) that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit (62) is still in a wafer format. A wafer substrate (64) on which the integrated circuits (62) have been fabricated is patterned and etched to form signal and ground vias (74, 72) through the substrate (64). A back-side ground plane (82) is deposited in contact with the ground vias (72). A protective layer (90) is formed on the top surface (76) of the substrate (64), and a protective layer (98) is formed on the bottom surface (84) of the substrate (64), where the bottom protective layer (98) fills in removed substrate material between the integrated circuits (62). Vias (106) are formed through the bottom protective layer (98), and the wafer substrate (64) is diced between the integrated circuits (62).
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: July 27, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: James Anderson, Gershon Akerling
  • Patent number: 6768061
    Abstract: A multilayer circuit board that has electrodes only on one surface is manufactured as follows. A plurality of conductor layers are formed on a resin film made of thermoplastic resin to form a single-sided conductor layer film. Then, a plurality of via-holes 24, which are bottomed by the conductor layers, are formed in the resin film. Then interlayer connecting material is packed in the via-holes 24 to form a single-sided conductor layer film having the interlayer connecting material. A plurality of single-sided conductor layer films are formed and stacked such that surfaces having the conductor layers face in the same direction. Then, the single-sided conductor layer films are pressed and heated to complete the multilayer circuit board. The multilayer circuit board is formed by using only the single-sided conductor layer films and pressing once, so the manufacturing process is simplified.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: July 27, 2004
    Assignee: Denso Corporation
    Inventor: Koji Kondo
  • Patent number: 6767616
    Abstract: A metal core substrate comprises a core layer (10) consisting of first and second metal plates (11, 12) layered with a third insulating layer (13) interposed therebetween; first and second insulating layers (20, 21) formed on the first and metal plates, respectively; first and second wiring patterns (45, 46) formed on the first and second insulating layers, respectively. A conductive layer (40) formed in a through-hole (22) penetrates the first insulating layer, the first metal plate, the third insulating layer, the second metal plate and the second insulating layer for electrically connecting the first wiring pattern with the second wiring pattern. The first metal plate (11) is electrically connected with the first wiring pattern (45) and the second wiring pattern (46), respectively, by means of a via (44) and by means a via (43).
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: July 27, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiko Ooi, Masaru Yamazaki, Yukiji Watanabe, Takaaki Yazawa
  • Publication number: 20040142161
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 22, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Patent number: 6762367
    Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet
  • Patent number: 6762369
    Abstract: A multilayer ceramic substrate includes a glass ceramic body, a conductive pattern, and a via conductor. The conductive pattern is formed in the glass ceramic body and on at least one principal surface of the glass ceramic body. The via conductor makes a connection between the predetermined conductive patterns. The via conductor includes a conductive material and a Mo compound or a Mo metal. The conductive material includes at least one selected from the group consisting of Ag, Au, Pt and Pd as a main component. The amount of Mo compound or Mo metal is in the range of 0.05 to 10 parts by weight in terms of Mo metal with respect to 100 parts by weight of the conductive material. This multilayer ceramic substrate can achieve sufficient flatness and high dimensional accuracy, while preventing defects that occurs in the vicinity of electrodes after firing.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: July 13, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryuichi Saito, Hidenori Katsumura, Hiroshi Kagata
  • Publication number: 20040118596
    Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: James W. Fuller, John M. Lauffer, Voya R. Markovich
  • Publication number: 20040118598
    Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.
    Type: Application
    Filed: March 6, 2003
    Publication date: June 24, 2004
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: James W. Fuller, John M. Lauffer, Voya R. Markovich
  • Publication number: 20040112637
    Abstract: Disclosed herein is a built-up printed circuit board with stacked micro via-holes, each of which is provided for interconnection between layers in the printed circuit board, and in each of which a filling material, such as liquefied resin or conductive paste, is filled using a poly screen of a general screen printing machine, and a method for manufacturing the same. The method comprises the steps of (a) forming a first via-hole through a first laminated copper sheet by means of a laser drill, (b) forming a first plated layer on the first via-hole and the first laminated copper sheet, (c) filling the first plated via-hole with a via-hole filling material, (d) forming a second plated layer on the first filled via-hole and the first plated layer to cover the first filled via-hole, (e) forming a second plated layer on the first filled via-hole and the first plated layer to cover the first filled via-hole, and (f) disposing a second laminated copper sheet on the second plated layer.
    Type: Application
    Filed: June 26, 2003
    Publication date: June 17, 2004
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Bong-Suck Kim, Gye-Soo Kim, Jong-Hyung Kim, Il-Woon Shin