Voidless (e.g., Solid) Patents (Class 174/264)
  • Patent number: 7377032
    Abstract: A printed wiring board for mounting electronic components includes an insulating layer and a wiring pattern formed on one surface of the insulating layer, wherein one end portion of a filled via 4 is connected with the wiring pattern and the other end portion is overlaid with a covering layer 9 obtained by applying a conductive paste to cover at least the boundary between the filled via 4 and the insulating layer 2; alternatively, a plating resist 7 is formed at the other end portion to cover at least the boundary between the filled via 4 and the insulating layer 2, and is removed after an end portion of the filled via 4 enclosed within the plating resist 7 is plated to produce a terminal layer, thereby preventing a wet processing liquid such as a tin plating solution from leaking in between the filled via 4 and the insulating layer 2.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: May 27, 2008
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Shinichi Sumi, Yutaka Iguchi
  • Patent number: 7378602
    Abstract: A multilayer core board 10 includes tapered first via hole conductors 51 extending from the outer surface of a first insulating layer 24 to conductive portions 42a of a power source layer 42, second via hole conductors 52 extending from the outer surface of a second insulating layer 26 to the conductive portions 42a of the power source layer 42, tapered third via hole conductors 53 extending form the outer surface of the second insulating layer 26 to conductive portions 40a of a ground layer 40, and fourth via hole conductors 54 extending from the outer surface of a center insulating layer 22 to the conductive portions 40a of the ground layer 40. The first via hole conductors 51 are tapered, and thus the interval distance to the adjacent first via hole conductor 51 is shorter than straight-shaped first via hole conductors, and thus the pitch of the first via hole conductor 51 at the positive pole side and the fourth via hole conductor 54 at the negative pole side can be sufficiently reduced.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: May 27, 2008
    Assignee: Ibiden Co., Ltd.
    Inventor: Tomoyuki Ikeda
  • Patent number: 7375290
    Abstract: A printed circuit board with vias that reduce or eliminate radio frequency interference and method of forming the same. The printed circuit board includes non-conductive layers, conductive-layers interspersed between the non-conductive layers, vias extending through the non-conductive layers and the conductive layers, radio frequency absorbing material within each of the vias, where the radio frequency absorbing material is at a conductive layer within the printed circuit board at which a conductive trace is not connected to a via, an insulating layer over each radio frequency absorbing material, and a cylindrical conductive material within via and over each insulating layer.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: May 20, 2008
    Inventors: Young Hoon Kwark, Christian Schuster
  • Patent number: 7374811
    Abstract: A method for manufacturing a ceramic device is provided. The ceramic device comprises a ceramic layer. A polyimide layer is on the ceramic layer. The polyimide layer has disposed therein a plurality of copper vias. Each copper via is in physical contact with the ceramic layer. A plurality of pads are formed on the polyimide layer. Each of the plurality of pads is in physical contact with a copper via of the plurality of copper vias. In this way, the pads are supported by a continuous copper arrangement, thereby providing greater support for the probe pads than if the probe pads were supported by the polyimide layer, as the mechanical strength of polyimide layer is lower than the mechanical strength of copper.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: May 20, 2008
    Assignee: SV Probe Pte Ltd.
    Inventors: Chi Shih Chang, Bahadir Tunaboylu
  • Patent number: 7368666
    Abstract: A surface-mounting type electronic circuit unit includes pedestal bases. The pedestal bases are attached to first lands provided on the bottom surface of an insulating substrate and are made of plate-shaped metal material having a solder film on the outer surface thereof. Solder bumps are provided on second lands. Since the pedestal bases used as the mounting reference of the insulating substrate is formed in a plate shape and is placed on the same plane as the first lands and the mother board, the contact state between the first lands a the mother board is effectively stabilized. In addition, since the solderable amount is more than that of a conventional invention, the solder is not detached due to an impact.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: May 6, 2008
    Assignee: Alps Electric Co., Ltd
    Inventor: Shuichi Takeda
  • Publication number: 20080099237
    Abstract: A base material in which a base insulating layer and a metallic layer are laminated is prepared. The metallic layer is processed into a predetermined pattern to form conductor patterns including terminal parts. A hole is formed in a region under a predetermined terminal part where the base insulating layer is formed by directing a laser beam from below. A reinforcing board having a through hole is attached to the lower surface of the base insulating layer by a sheet-like adhesive having a through hole, with the holes being aligned with one another. An opening space formed by the holes is filled with metallic paste by screen printing. In this way, a printed circuit board is fabricated. An electronic component is mounted on this printed circuit board.
    Type: Application
    Filed: October 11, 2007
    Publication date: May 1, 2008
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kensuke NISHI, Akinori ITOKAWA, Visit THAVEEPRUNGSRIPORN
  • Publication number: 20080098595
    Abstract: A method of making a circuitized substrate in which pairs of vertically oriented though holes are formed such that at least one of the through holes is partially embedded within a lower one, thus assuring a sound connection following subsequent lamination or other steps the substrate including such holes is subjected to during manufacture. An electrical assembly including a substrate with such features is also provided.
    Type: Application
    Filed: November 1, 2006
    Publication date: May 1, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: John S. Kresge, Cheryl L. Palomaki
  • Patent number: 7365272
    Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: April 29, 2008
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Shih-Ping Hsu, Shang-Wei Chen, Suo-Hsia Tang, Chao-Wen Shih
  • Patent number: 7350296
    Abstract: Disclosed is a method of fabricating a PCB including an embedded passive component and a method of fabricating the same and a method of fabricating the same. The PCB includes at least two circuit layers in which circuit patterns are formed. At least one insulating layer is interposed between the circuit layers. A pair of terminals is vertically formed through the insulating layers, plated with a first conductive material, and separated from each other by a predetermined distance. The embedded passive component is interposed between the terminals and has electrodes formed on both sides thereof. The electrodes are separated from the terminals by a predetermined distance and electrically connected to the terminals through a second conductive material.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: April 1, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chang Sup Ryu, Myung Sam Kang
  • Patent number: 7342802
    Abstract: To provide a multilayer wiring board mainly used for an electronic device, in which a bump passing through an interlayer insulating film allows for interlayer connection between plural wiring films insulated from one another with plural interlayer insulating layers. In the multilayer wiring board, a circuit element such as an electronic part, a semiconductor chip, or a passive element is accommodated in the interlayer insulating films so as to connect its terminal with the corresponding wiring film. In particular, the semiconductor chip is polished to a thickness of 50 ?m or smaller, and the multilayer wiring board itself for the electronic device has the flexibility.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: March 11, 2008
    Assignee: Tessera Interconnect Materials, Inc.
    Inventors: Tomoo Iijima, Yoshitaka Fukuoka
  • Publication number: 20080035368
    Abstract: A chip holder board for carrying chips for covering with a silver glue is disclosed to have a metal board, which has arrays of transversely longitudinally aligned through holes cutting through the top and bottom walls thereof, and a flexible polymeric covering material covered over the top and bottom walls and the periphery of the inner diameter of each of the through holes of the metal board.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 14, 2008
    Inventor: Sen-Sung Lin
  • Publication number: 20080029297
    Abstract: A wiring substrate includes a first insulation layer, a connection terminal, a second insulation layer, a via, and a wiring pattern. The connection terminal is disposed in the first insulation layer so as to be exposed from a first main surface of the first insulation layer, and is electrically connected with a semiconductor chip. The second insulation layer is disposed on a second main surface of the first insulation layer situated on the opposite side from the first main surface. The via is disposed in the second insulation layer, and is electrically connected with the connection terminal. The via is separated from the connection terminal. The wiring pattern is disposed on the second main surface of the first insulation layer and electrically connects the connection terminal and the via.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 7, 2008
    Inventor: Junichi Nakamura
  • Publication number: 20080000680
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same, which can achieve reliable heat resistance because heat radiation characteristics are improved, and processing costs of which are reduced because processing times are shortened.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 3, 2008
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Suk Hyeon Cho, Byoung Youl Min, Je Gwang Yoo, Hae Nam Seo, Byung Moon Kim, Ji Hong Jo, Han Seo Cho
  • Patent number: 7312400
    Abstract: A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode pattern; an adhesive layer 113 formed on the other surface of said insulating substrate component 111; and a conductive resin composition 115 with which is filled a through hole passing through said insulating substrate component 111, said adhesive layer and said conductive layer in order to make interlayer interconnection. The bore diameter of the conductive layer portion 114b of the through hole 114 is smaller than the bore diameter of the insulating resin layer portion and the adhesive layer portion 114a to establish electrical connection between the conductive resin composition 115 and the conductive layer 112 by the rare surface 112a of the conductive layer 112.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: December 25, 2007
    Assignee: Fujikura Ltd.
    Inventors: Shoji Ito, Osamu Nakao, Reiji Higuchi, Masahiro Okamoto
  • Patent number: 7309838
    Abstract: A circuit board assembly includes an electrical component mounted on or in the assembly; a conductive layer, which is electrically connected to the electrical component; a high-temperature dissipation resin, which is of insulating material and is arranged so as to dissipate heat generated in the assembly; and a molding resin surrounding the electrical component. Heat, generated at electrical components in a circuit board assembly, is transferred and dispersed through the high-temperature dissipation material all over the assembly. Further, since the high-temperature dissipation resin is of an insulating material, it is unnecessary to consider a short-circuit problem in the assembly.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: December 18, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takashi Noguchi
  • Patent number: 7303639
    Abstract: A method of forming a member for joining to form a composite wiring board. The member includes a dielectric substrate. Adhesive tape is applied to at least one face of said substrate. At least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Curcio, Donald S. Farquhar, Lisa J. Jimarez, Keith P. Brodock
  • Patent number: 7297878
    Abstract: The present invention relates to a high frequency laminated component, which is used in a high frequency apparatus such as a radio communication apparatus, and its manufacturing method. An object thereof is to downsize the high frequency laminated component. To achieve the object, according to the high frequency laminated component of the present invention, dielectric layer (4) whose dielectric constant is lower than that of other areas is formed around via-hole electrode (3) in a dielectric. By forming dielectric layer (4) having a low dielectric constant, electric interference between via-hole electrode (3) and circuit electrode (22) is restrained, so that the circuit electrode and the via-hole electrode can be formed more closely each other compared with a conventional one. As a result, the high frequency laminated component can be downsized.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: November 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Kushitani, Ichiro Kameyama
  • Patent number: 7292452
    Abstract: A component having reference layer openings to contribute towards achieving a differential impedance in a circuit, is described herein.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: November 6, 2007
    Assignee: Intel Corporation
    Inventors: Kok-Siang Ng, King Keong Wong, Michael E. Ryan
  • Patent number: 7292448
    Abstract: A circuit substrate includes a first rigid substrate having a plurality of land portions located at a predetermined interval on one surface, a second rigid substrate having a plurality of second land portions located at a predetermined interval on one surface and a flexible wiring board sandwiched by the first and second rigid substrates and which has a plurality of third land portions corresponding to the first land portions on one surface and a plurality of fourth land portions corresponding to the second land portions on the other surface. In this circuit substrate, the second and fourth land portions are displaced from each other relative to the first and third land portions and at least part of the first and third land portions and at least part of the second and fourth land portions are electrically connected to each other, respectively.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 6, 2007
    Assignee: Sony Corporation
    Inventors: Toshichika Urushibara, Koji Shiozawa, Masakazu Okabe, Yukiko Hyodo, Yusuke Masuda, Tadayuki Miyamoto
  • Patent number: 7287323
    Abstract: A ceramic circuit structure comprising a plurality of ceramic layers and at least one electronic component embedded within the plurality of ceramic layers. Within a first one of the ceramic layers is a via that passes through the ceramic layer. A contact pad is formed on a surface of the ceramic layer. A barrier cap is formed between the via and the contact pad. A dielectric ring covers a peripheral portion of the contact pad and an adjacent portion of the dielectric material layer surface immediately surrounding the contact pad, such that any solder that is applied to the contact does not contact the peripheral portion of the contact pad or the ceramic material.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 30, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Michael Richard Ehlert, William Jeffrey Schaefer
  • Publication number: 20070246254
    Abstract: Printed circuit boards having circuit layers laminated with stacked (or staggered) micro via(s) and methods of manufacturing the same. Aspects of embodiments of the present invention are directed to a printed circuit board with Z-axis interconnect(s) or micro via(s) that can eliminate a need for plating micro vias and/or eliminate a need for planarizing plated bumps of a surface, that can be fabricated with one or two lamination cycles, and/or that can have carrier-to-carrier (or substrate-to-substrate) attachments with conductive vias, each filled with a conductive material (e.g., with a conductive paste) in the Z-axis. In one embodiment, a printed circuit board having a plurality of circuit layers with at least one z-axis interconnect can be fabricated using a single lamination cycle.
    Type: Application
    Filed: February 14, 2007
    Publication date: October 25, 2007
    Inventors: Raj Kumar, Monte Dreyer, Michael J. Taylor
  • Publication number: 20070227768
    Abstract: A flexible printed circuit board has a flexible dynamic region, and relatively rigid static regions between which the dynamic region extends. Portions of a base layer, a patterned conductive layer extending on the base layer, and a cover layer covering the conductive layer make up the dynamic region. Extensions of the base layer, the conductive layer, and the cover layer, and portions of a metal layer to which the base layer is attached make up each of the static regions. The metal layer enhances the rigidity of the flexible printed circuit board at the static regions. The metal layer also has rounded corners at sides of each of the boundaries between the dynamic region and each of the static regions to minimize stress concentrations at the boundaries. The conductive layer is made up of real traces through which electrical signals are transmitted, and dummy traces.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 4, 2007
    Inventor: Sang-chul Shin
  • Publication number: 20070215382
    Abstract: A coupling structure between a circuit board and a frame member according to the present invention includes: the frame member made of a metal material; and the circuit board set in the frame member and having a land portion soldered to the frame member, in which a solder reinforcing member that is put on the land portion and is solderable is provided at a corner formed by the frame member and the circuit board, and the frame member, the land portion, and the solder reinforcing member are soldered at the corner.
    Type: Application
    Filed: March 5, 2007
    Publication date: September 20, 2007
    Inventor: Masaki Yamamoto
  • Publication number: 20070199735
    Abstract: An aspect of the present invention features a printed circuit board. The board can comprise a core layer in which an inner via hole (IVH) is formed, a first plating layer that closes one entrance of the inner via hole, leaving a remaining space in the inner via hole unfilled; and a second plating layer that closes the other entrance of the inner via hole, filling the remaining space. Also, the present invention provides a printed circuit board and a manufacturing method thereof that do not require filling an inner via hole with an insulating ink, and forming a conductive layer on the insulating ink. Therefore, the present invention can increase productive capacity and reduce manufacturing cost by simplifying the manufacturing process and reducing the lead time.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 30, 2007
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chi-Seong Kim, Hyo-Seung Nam, Seok-Hwan Ahn, Kwang-Ok Jeong, Kyung-Hwan Ko
  • Patent number: 7251885
    Abstract: In order to improve the adhesion of a circuit to a circuit forming board, a separation film including a base film and a coating layer formed on the base film is joined to both the sides of the board. When a laser beam is applied to form a throughhole in the board, a unified portion of the board and the separation film is formed around the throughhole. An energy beam is applied to the whole or a part of the surface of a circuit formed at a circuit forming step to transfer a part of the separation film. Thus, a high density board where the circuit strongly adheres to the board can be realized in the manufacturing process of the circuit forming board.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: August 7, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshihiro Nishii
  • Patent number: 7242592
    Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: July 10, 2007
    Assignee: Amphenol Corporation
    Inventors: Jason J. Payne, Mark W. Gailus, Leon M. Khilchenko, Huilin Ren
  • Patent number: 7226654
    Abstract: A laminated wiring board comprising: a first wiring board forming wiring layers on the upper surface and on the lower surface of a first ceramic insulated substrate; and a second wiring board forming wiring layers on the upper surface and on the lower surface of a second ceramic insulated substrate; the wiring layer on the lower surface of the first wiring board and the wiring layer on the upper surface of the second wiring board being connected together through connecting electrodes; wherein a coefficient ?1 of thermal expansion of the first ceramic insulated substrate at 0 to 150° C. and a coefficient ?2 of thermal expansion of the second ceramic insulated substrate at 0 to 150° C. are satisfying the following conditions: ?1<?2 ?2??1?9×10?6/° C.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: June 5, 2007
    Assignee: Kyocera Corporation
    Inventors: Shinya Kawai, Masanari Kokubu, Youji Furukubo
  • Patent number: 7221050
    Abstract: A substrate and a method of making a substrate having a functionally gradient coefficient of thermal expansion are described herein. A system having a silicon die, an organic package substrate, and a substrate having a functionally gradient coefficient of thermal expansion, connecting the silicon die and the organic substrate is also described. The coefficient of thermal expansion at the upper surface of the substrate matches the coefficient of thermal expansion of the die, the coefficient of thermal expansion at the lower surface of the substrate matches the coefficient of thermal expansion of the package substrate, and the substrate has one or more coefficients of thermal expansion between the coefficients of thermal expansion of the upper and lower surfaces.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventor: A. Cengiz Palanduz
  • Patent number: 7217890
    Abstract: A blind hole (3) is formed on a substrate (1) from a first side of the substrate toward a second side of the substrate (1). A conductor (11) is filled in the blind hole (3). The substrate (1) is removed from the opposite side to expose the conductor (13) filled in the blind hole (3).
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: May 15, 2007
    Assignee: Fujikura, Ltd.
    Inventors: Tatsuo Suemasu, Takashi Takizawa
  • Patent number: 7214419
    Abstract: A conductive paste is provided, which has good conductivity and good adhesiveness to substrates and has good long-lasting stability of these properties, and which, when applied to a through-hole of a multi-layered substrate, ensures improved reliability of bonding to the end faces of conductive layers in the through-hole. Therefore, the paste does not require through-hole plating. The conductive paste comprises (A) 100 parts by weight of a resin component that contains an acrylate resin and an epoxy resin, (B) from 200 to 1800 parts by weight of a metal powder of at least two metals that contain at least one low-melting-point metal having a melting point of not higher than 180° C. and at least one high-melting-point metal having a melting point of not lower than 800° C., (C) from 0.5 to 40 parts by weight of a curing agent that contains from 0.3 to 35 parts by weight of a phenol-type curing agent, and (D) from 0.3 to 80 parts by weight of a flux.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: May 8, 2007
    Assignee: Tatsuta Electric Wire & Cable Co., Ltd.
    Inventors: Hiroaki Umeda, Hisatoshi Murakami, Kiyoshi Iwai
  • Patent number: 7183497
    Abstract: A multilayer wiring board (11) is provided which includes a core substrate (12) including a plurality of through-holes (15). The through-holes (15) include through-hole conductors (17) on the inner walls of corresponding penetration holes (16) of a diameter of 200 ?m or less. Interlayer insulating layers (31, 32) are disposed on opposite sides of the principal planes (13, 14) of the core substrate (12). Wiring layers (23, 24) are disposed on the surface of interlayer insulating layers (31, 32). The through-holes (15) are filled with a hardened filling material (18). Lid conductors (21, 22) close the openings of the through-holes (15). The value of linear expansion of the hardened filling material (18) is 1.2% or less in the temperature region from room temperature to the solder reflow temperature. The board has excellent connection reliability and exhibits little or no cracking or delamination in the lid conductor closing the openings of the through-holes and in the surrounding conductor area.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: February 27, 2007
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Toshifumi Kojima, Makoto Wakazono
  • Patent number: 7174632
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Patent number: 7165321
    Abstract: A manufacturing method of a printed wiring board having an embedded electric device is as follows. A first resin film having an opening or a sheet member having a recess is piled with a plurality of second resin films, on which a plurality of conductive layers is formed. The first and second resin films and the sheet member include thermoplastic resin. An electric device is inserted in the opening or the recess. Then, the piled body including the electric device is pressed and heated to integrate the piled body. When the piled body is pressed and heated, electrodes of the electric device are electrically connected to the conductive layers while the first and second resin films and the sheet member plastically deformed to seal the electric device.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: January 23, 2007
    Assignee: Denso Corporation
    Inventors: Koji Kondo, Tomohiro Yokochi, Toshihiro Miyake, Satoshi Takeuchi
  • Patent number: 7154047
    Abstract: A substrate (300) for a package of high frequency semiconductor devices comprising a planar insulating substrate having a plurality of parallel, planar metal layers (301a, 301b, etc.) embedded in the insulator. The substrate further has at least one pair of parallel, metal-filled vias (302 and 303) traversing the substrate; the vias have a diameter and a distance from each other of at least this diameter. The metal in each via has a sheet-like extension (321a, 321b, etc.) in each of selected planes of said metal layers, resulting in an increased via-to-via capacitance so that the reflection of a high frequency signal is less than 10%.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: December 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory E. Howard
  • Patent number: 7152318
    Abstract: A built-up printed circuit board includes stacked micro via-holes, each of which is provided for interconnection between layers in the printed circuit board, and in each of which a filling material, such as liquefied resin or conductive paste, is filled using a poly screen of a general screen printing machine.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: December 26, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Bong-Suck Kim, Gye-Soo Kim, Jong-Hyung Kim, Il-Woon Shin
  • Patent number: 7149092
    Abstract: In a printed circuit board of the invention, a first signal wiring layer, a first ground layer, a second ground layer and a second signal wiring layer are laminated via an insulating material. A first signal wiring is formed on the first signal wiring layer and a second signal wiring is formed on the second signal wiring layer. The two signal wirings are connected via a first through hole. The conductive first ground layer and the conductive second ground layer are connected via a second through hole. The second through hole is insulated from the first through hole and formed so as to surround the first through hole.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: December 12, 2006
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Daisuke Iguchi
  • Patent number: 7143929
    Abstract: In the ceramic circuit board, within the through hole of the ceramic substrate is arranged the metal column which is 0 to 150 ?m shorter relative to the thickness of the ceramic substrate; the metal circuit plates are attached to both surfaces of the ceramic substrate to stop up the through hole; and the metal column and the metal circuit plate are bonded together via the brazing material. For its manufacture, the metal column with brazing material is used that is made 40 to 140 ?m longer relative to the thickness of the ceramic substrate by being formed of the metal column which is 0 to 150 ?m shorter relative to the thickness of the ceramic substrate and has its both ends coated with the brazing material.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: December 5, 2006
    Assignee: Kyocera Corporation
    Inventor: Ken Furukuwa
  • Patent number: 7140104
    Abstract: A circuit component built-in module can be produced by filling a conducting material in through holes of a sheet-like member, stacking the sheet-like member and a metal foil on a circuit component package, and applying heat and pressure to embed the circuit component in the sheet-like member, and patterning the metal foil. The circuit component package includes a mounting member with substrate and wiring pattern and a circuit component. The circuit component includes a component body and external electrode, with the component body being thinner at a portion on which the external electrode is provided. The external electrode is provided on a surface of the circuit component that is opposed to the mounting member, and the component body is in contact with the mounting member.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: November 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Seiichi Nakatani, Hiroyuki Handa, Tsunenori Yoshida, Yoshihisa Yamashita, Hiroyuki Ishitomi
  • Patent number: 7131188
    Abstract: The touch panel comprises two conductive substrates arranged in parallel and secured to each other with a gap existing between the conductive substrates The process for implementing a conductive tracing layout in a touch panel includes steps of forming a first conductive layer on at least one of the conductive substrates; forming a first photo-resist layer on the first conductive layer; removing a specified portion of the first photo-resist layer to form a first specified mask on a specified portion of the first conductive layer; and removing the first conductive layer except the specified portion of the first conductive layer to form a first conductive tracing layout.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: November 7, 2006
    Assignee: TPO Displays Corp.
    Inventors: Hong-Yu Lin, Yi-Hung Tsai
  • Patent number: 7081672
    Abstract: A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Anand Govind, Aritharan Thurairajaratnam, Farshad Ghahghahi
  • Patent number: 7071424
    Abstract: The present invention provides a multilayer printed wiring board having a filled viahole structure advantageously usable for forming a fine circuit pattern thereon, and having an excellent resistance against cracking under a thermal shock or due to heat cycle. The multilayer printed wiring board is comprised of conductor circuitry layers and interlaminar insulative resin layers deposited alternately one on another, the interlaminar insulative resin layers each having formed through them holes each filled with a plating layer to form a viahole. The surface of the plating layer exposed out of the hole for the viahole is formed substantially flat and lies at a substantially same level as the surface of the conductor circuit disposed in the interlaminar insulative resin layer. The thickness of the conductor circuitry layer is less than a half of the viahole diameter and less than 25 ?m.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: July 4, 2006
    Assignee: Ibiden Co., Ltd.
    Inventors: Seiji Shirai, Kenichi Shimada, Motoo Asai
  • Patent number: 7047630
    Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: May 23, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
  • Patent number: 7022399
    Abstract: The present invention provides a semiconductor device integrated multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring, thereby enabling the production of high density, ultra small three dimensional mounting modules and the like, can also be ideally applied to low volume high mix manufacturing configurations, and has little impact on the environment, and also provides a method of manufacturing such a semiconductor device integrated multilayer wiring board. In the semiconductor device integrated multilayer wiring board, a wiring substrate is formed by embedding conductive wiring within an insulating substrate, formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: April 4, 2006
    Assignees: Sony Corporation, Mitsubishi Plastics, Inc.
    Inventors: Minoru Ogawa, Masahiro Izumi, Shigeyasu Itoh, Shingetsu Yamada, Shuuji Suzuki, Hiroo Kurosaki
  • Patent number: 7018705
    Abstract: It is an object of the present invention to provide a multilayer circuit board, and a method for manufacturing the same, in which a plurality of circuit boards are layered, wherein as regards at least one circuit board positioned on an outer side, a conductive substance is filled into holes passing through the circuit board in the thickness direction and cured, and the wiring layers of the plurality of circuit boards are electrically connected by the conductive substance that has been cured, wherein in the multilayer circuit board, the wiring layer positioned outside the conductive substance that has been cured projects outward from its surroundings. Thus, the conductive paste is sufficiently compressed during hot pressing to yield a stable electrical connection, and thermosetting resin can be filled in between the inner layer wiring pattern without leaving gaps.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: March 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Nakatani, Hideki Higashitani, Tadashi Nakamura, Fumio Echigo
  • Patent number: 6998540
    Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: February 14, 2006
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Robert Edward Belke, Jr., Vivek A. Jairazbhoy, Thomas B. Krautheim, William F. Quitty, Jr.
  • Patent number: 6989590
    Abstract: A power semiconductor device according to the present invention comprises at least one insulating substrate; at least one power semiconductor element mounted on a metal pattern formed on the main surface of the insulating substrate; and a control circuit board which is arranged so that its first surface can oppose the above main surface of the insulating substrate with the power semiconductor element interposed therebetween, and which has at least one electronic component for control, mounted on a metal pattern formed on its second surface in parallel to the above first surface, and at least one through hole formed vertically to the first and second surfaces so as to electrically connect circuit patterns laminated between the first surface and the second surface, and this power semiconductor device is characterized in that the above through hole is filled with a filler.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: January 24, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hironobu Hanada, Yasuo Koutake
  • Patent number: 6977349
    Abstract: Wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other difficult operations are rendered unnecessary. By utilizing a technique whereby a bump-formation etching mask 7 is formed on a bump-forming surface 3a of a metal foil 3 which has a thickness that is the sum of the thickness t1 of the wiring circuit 1 and the height t2 of the bumps 2 which are to be formed on the wiring circuit 1 (t1+t2), and then the bumps 2 are formed by half-etching the metal foil 3 to a depth corresponding to the desired bump height t2 from the bump-formation etching mask 7 side, wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other complex processes are rendered unnecessary.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: December 20, 2005
    Assignees: Sony Corporation, Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Keiichi Naito, Toshihiro Shinohara
  • Patent number: 6977348
    Abstract: A laminated substrate structure composed of a plurality of dielectric layers and a plurality of circuit layers stacked with each other. Each of the dielectric layers has a plurality of via studs, and the circuit layers are electrically coupled with each other through the via studs. The laminated substrate structure of the present invention is characterized by adopting the embedded structure landless design that provides high reliability and better adherence. The present invention also provides a laminated substrate manufacture method. The dielectric layers having the patterned circuit and the dielectric layers having the via holes are formed first, and after the dielectric layers having the patterned circuit and the dielectric layers having the via holes are formed, they are aligned and laminated synchronously to complete the manufacture of the laminated substrate.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: December 20, 2005
    Assignee: VIA Technologies, Inc.
    Inventors: Kwun-Yao Ho, Chen-Yueh Kung
  • Patent number: 6974915
    Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: William Louis Brodsky, Benson Chan, Michael Anthony Gaynes, Voya Rista Markovich
  • Patent number: 6974916
    Abstract: In a laminated ceramic electronic component, the sectional size of via-hole conductors extending through thicker ceramic layers is larger than that of via-hole conductors extending through thinner ceramic layers. This makes it possible to facilitate filling of a conductive paste for the via-hole conductors having a larger height and to inhibit a conductive paste for the via-hole conductors having a smaller height from being lost after filling.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: December 13, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Norio Sakai