Abstract: Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.

Abstract: A method for making plural plated through holes in a single circuit board via is provided. The method includes plating copper in the walls of said circuit board via to form a first plated through hole and applying a thin layer of first adhesive promotor to the surface of said plated via. The method further includes vacuum depositing an organic layer having a high dielectric strength unto said layer of first adhesive promoter and applying a second layer of adhesive promoter over said organic layer. The method even further includes plating copper over said second layer of adhesive promoter to form a second plated through hole in said circuit board via.

Abstract: A ceramic multilayer substrate exhibiting reduced pealing and breakage of an internal conductor disposed between a ceramic layer serving as a base member and a ceramic layer for restricting shrinkage includes a first ceramic layer 11, a second ceramic layer 12 laminated so as to come into contact with a principal surface of the first ceramic layer 11, and an internal conductor 13 disposed between the first ceramic layer 11 and the second ceramic layer 12, a phosphorus component layer 16a is disposed in the first ceramic layer 11 with a concentration gradient in which the concentration decreases in a direction away from the internal conductor 13.

Abstract: A laminate for a printed wiring board having a laminate structure comprising an electrical insulator layer (A) and an electrical conductor layer (B) bonded directly to each other, wherein the electrical insulator layer (A) is formed of a fluorocopolymer comprising repeating units (a) based on tetrafluoroethylene and/or chlorotrifluoroethylene, repeating units (b) based on a fluoromonomer excluding tetrafluoroethylene and chlorotrifluoroethylene, and repeating units (c) based on a monomer having an acid anhydride residue and a polymerizable unsaturated bond in amounts of (a) being from 50 to 99.89 mol %, (b) being from 0.1 to 49.99 mol % and (c) being from 0.01 to 5 mol %, based on ((a)+(b)+(c)), and the electrical conductor layer (B) has a surface roughness of at most 10 ?m on the side being in contact with the electrical insulator layer (A). The laminate for a printed wiring board is excellent in signal response in a high frequency region.

Abstract: A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a second surface; arranging an insulating board having thermo-plasticity and thermo-setting properties so as to face the first surface of the first metal foil, and arranging the first surface side of the second metal foil so as to face a surface different from a surface to which the first metal foil faces of the insulating board; forming a double-sided wiring board by stacking, pressurizing and heating the arranged first metal foil, insulating board, and second metal foil, and thereby integrating these; and patterning the first metal foil and/or the second metal foil.

Abstract: A contact of semiconductor device and manufacturing method thereof prevent generation or inlet of noise through a contact plug which connects wires in different layers. The contact includes a lower wire, an insulating layer covering the lower wire, a contact plug connected to the lower wire through the insulating layer, a conductive tube encircling the contact plug and having the insulating layer in between, and an upper wire connected to the contact plug.

Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

Abstract: The printed wiring board 1 includes the metallic substrate 2, the insulating layer 3 provided on the surface of the metallic substrate 2, and the conductive layer 4 formed on the surface of the insulating layer 3. The conductive layer 4 is electrically connected to the metallic substrate 2. A bottomed via hole or a through hole 6 is formed in the insulating layer 3 and the conducive layer 4. The via hole has a bottom in the metallic substrate 2, and has a wall surface in the insulating layer 3 and in the conductive layer 4. The through hole 6 extends through the insulating layer 3, the conductive layer 4, and the metallic substrate 2. Conductive paste 7 fills the bottomed via hole or the through hole 6 to electrically connect the metallic substrate 2 and the conductive layer 4 with each other. The printed wiring board 1 is subjected to a process in which current is applied to the interface between the metallic substrate 2 and the conductive paste 7.

Abstract: In one embodiment the present invention includes an electrical arrangement comprising conductive elements such as electrical traces. The conductive elements carry differential signals. The conductive elements extend horizontally and have alternating sections around one or more center lines. Ground lines may be included the further enhance signal integrity. In one embodiment, magnetic field cancellation may be achieved by providing an offset between pairs of alternating differential elements.

Abstract: The present invention discloses a flexible printed circuit (FPC) layout and a method thereof.

Abstract: A printed circuit board and a method of manufacturing a printed circuit board are disclosed. Using a method of manufacturing a printed circuit board, which includes: forming a multilayer board by alternately stacking circuit pattern layers and insulation layers such that a predetermined thickness of a partial area has only insulation layers stacked therein; and removing insulation layers from the partial area of the multilayer board, a printed circuit board can be manufactured that is suitable for a slim module.

Abstract: Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 ?m.

Abstract: A manufacturing method of a multilayer substrate that suppresses relative displacement of layers and forms interconnecting portions electrically connecting layers having an accurate positioning. A manufacturing method of a multilayer substrate for laminating, via an insulating film, a wiring layer formed by patterning a conductive film comprises providing a positioning hole in a conductive film laminated at the beginning and patterning a second and/or any subsequent wiring layers after identifying a position of an identification section. Interconnecting sections for interconnecting wiring layers are formed using the identification section.

Abstract: A wiring substrate of the invention comprises electrical insulation substrate (1), through-hole (3) formed in the electrical insulation substrate, electrically conductive paste (4) filled inside the through-hole, and wiring traces (11) formed on one or both surfaces of the electrical insulation substrate and electrically connected with the electrically conductive paste, wherein interfaces of the wiring traces in contact with the electrically conductive paste have at least one of an asperate surface and a smooth surface, and a plurality of granular bumps (14) formed further thereon.

Abstract: A circuit board is manufactured by filling a via-hole formed in an insulating substrate with conductive material, disposing conductive layers on both sides of the insulating substrate, and forming alloy of component material of the conductive material with component material of the conductive layers. In the circuit board, therefore, the conductive material filled in the via-hole formed in the insulating substrate is securely connected electrically as well as mechanically to the conductive layers on both sides of the insulating substrate with high reliability.

Abstract: An electrically conductive substrate with a high heat conductivity has an aluminum plate having multiple holes. An isolation layer is formed on the aluminum plate and inner walls of the holes. Multiple electrically conductive materials are inserted in the holes. A circuit layer is formed on the aluminum plate, electrically connects to the electrically conductive materials and has a rough surface. A graphite layer is formed on the rough surface of the circuit layer. The electric components are respectively provided on the holes, and the heat generated by the electric components is dissipated effectively by the aluminum plate.

Abstract: A wafer assembly (30) includes a substrate (71), in turn including a wafer (70) or a stack of wafers. The wafer assembly (30) further includes an electrical connection (32) arranged through at least a part of the substrate (71). The electrical connection (32) is made by low-resistance silicon. The electrical connection (32) is positioned in a hole (84) penetrating at least a part of the substrate (71). A surface (78) of the substrate (71) confining the hole (84) is electrically insulating. The electrical connection (32) has at least one protrusion (75), which protrudes transversally to a main extension (83) of the hole (84) and the protrusion (75) protrudes outside a minimum hole diameter (85), as projected in the main extension (83) of the hole (84). Preferably, the protrusion (75) is supported by a support surface (81) of the substrate (71). A manufacturing method is also disclosed.

Abstract: A multilayer substrate includes an internal conductor connection structure having first and second via conductors adjacent to each other in the multilayer substrate and a first line conductor disposed in the multilayer substrate. The first via conductor includes a first continuous via conductor arranged to extend in a direction away from the second via conductor, and the first via conductor is connected to the first line conductor through the first continuous via conductor.

Abstract: Embodiments include electronic device substrates and methods for forming the same. A method for forming a package comprising a multilayer substrate includes forming a stack of a plurality of dielectric layers comprising a ceramic material, the stack including upper and lower dielectric layers. The method also includes providing a plurality of metallization lines on the dielectric layers in the stack. The method also includes forming a plurality of vias in the dielectric layers, the vias formed to include electrically conductive material therein. A first metal layer is formed on the upper dielectric layer, and a second metal layer is formed on the lower dielectric layer. The first metal layer and the second metal layer are each formed to be at least 250 ?m thick. Other embodiments are described and claimed.

Abstract: To improve reliability of interlayer connection of a multilayer wiring board. Plural metal conductor pattern layers are formed on a base material made of thermoplastic resin. Then, high melting metal containing copper, low melting metal containing tin, and binder resin are packed into a via hole. Subsequently, predetermined heat and pressure are applied. Then, while half-melted metal mixture droplets of the low and high melting metals and melted binder resin are phase separated from each other, the surfaces of the conductor patterns that face the openings of the via and the low melting metal are alloyed with each other to form an alloy layer as well as the high and low meting metals are alloyed with each other to form a columnar-shaped interlayer connection part. As a result, an intermediate layer is formed between the outer surface of the columnar-shaped interlayer connection part and inner surface of the via hole.

Abstract: A wiring substrate includes a core substrate having a first main surface and a mutually opposing second main surface, the second main surface having a conductive property. A first through hole penetrates a core substrate. A first conductive layer extends from the first main surface to the second main surface via the first through hole. An insulating layer is formed on the first conductive layer. A second through hole has the insulating layer as an interior wall. And a second conductive layer is formed inside the second through hole.

Abstract: A package substrate having double-sided circuits and a method of manufacturing the same are proposed. The package substrate includes a core board having a plated through hole, a plurality of first electrical contact pads, and a first solder mask layer formed on the core board. A first wiring layer and a second wiring layer are disposed on two opposite surfaces of the core board, respectively, and electrically connected to the plated through hole. A portion of the first wiring layer is exposed from a first opening formed in the first solder mask layer. The first electrical contact pads are disposed on the exposed portion of the first wiring layer. The top surface of the first electrical contact pads is higher than that of the first wiring layer to thereby allow a semiconductor chip to be mounted on the electrical contact pads for improving electrical connection.

Abstract: Large-sized through holes are formed in a core layer of a printed wiring board. Large-sized vias are formed in the shape of a cylinder along the inward wall surfaces of the large-sized through holes located within a specific area. A filling material fills the inner space of the large-sized via. A small-sized through hole penetrates through the corresponding filling material along the longitudinal axis of the small-sized through hole. A small-sized via is formed in the shape of a cylinder along the inward wall surface of the small-sized through hole. The filling material and the core layer are uniformly distributed within the specific area in the in-plane direction of the core substrate. This results in suppression of uneven distribution of thermal stress in the core layer in the in-plane direction of the core layer.

Abstract: A multilayer wiring board is capable of preventing the occurrence of cracking in the vicinity of a connection portion of a conductor pattern disposed inside a basic material layer and a via-hole conductor even when the conductor pattern is connected to the via-hole conductor. A multilayer wiring board includes basic material layers and the constraining layers that are alternately stacked. In the material layer, a via-hole conductor is connected to an intermediate conductor pattern. An extended portion is defined by extending an end of the via-hole conductor beyond the intermediate conductor pattern inside the basic material layer.

Abstract: First, a plurality of wiring boards are fabricated at separate steps. The first wiring board includes a Cu post formed on a wiring layer on one surface of a substrate, and a first stopper layer formed at a desired position around the Cu post. The second wiring board includes a through hole for insertion of the Cu post therethrough, a connection terminal formed on a wiring layer on one surface of a substrate, and a second stopper layer that engages the first stopper layer and functions to suppress in-plane misalignment. The third wiring board includes a connection terminal formed on a wiring layer on one surface of a substrate. Then, the wiring boards are stacked up, as aligned with one another so that the wiring layers are interconnected via the Cu post and the connection terminals, to thereby electrically connect the wiring boards. Thereafter, resin is filled into gaps between the wiring boards.

Abstract: The present invention provides a multilayer printed wiring board having a filled viahole structure advantageously usable for forming a fine circuit pattern thereon, and having an excellent resistance against cracking under a thermal shock or due to heat cycle. The multilayer printed wiring board is comprised of conductor circuitry layers and interlaminar insulative resin layers deposited alternately one on another, the interlaminar insulative resin layers each having formed through them holes each filled with a plating layer to form a viahole. The surface of the plating layer exposed out of the hole for the viahole is formed substantially flat and lies at a substantially same level as the surface of the conductor circuit disposed in the interlaminar insulative resin layer. The thickness of the conductor circuitry layer is less than a half of the viahole diameter and less than 25 ?m.

Abstract: An interconnect structure includes: an interlayer insulating film formed on a lower metal layer; a contact hole formed in the interlayer insulating film to expose the lower metal layer; a plurality of carbon nanotubes formed on a bottom of the contact hole; an wiring metal filled in the contact hole to fill gap between the plurality of carbon nanotubes; and an upper wiring formed above the contact hole. A Ti layer is formed between the plurality of carbon nanotubes and the upper wiring.

Abstract: This invention relates to a printed circuit board having a landless via hole, including a circuit pattern formed on a via made of a first metal and having a line width smaller than the diameter of the via hole, in which the circuit pattern includes a seed layer made of a second metal and a plating layer made of a third metal, which is different from the second metal, and to a method of manufacturing the same. In the printed circuit board, the via has no upper land, thus making it possible to finely form the circuit pattern which is connected to the via, thereby realizing a high-density circuit pattern.

Abstract: Electronic modules and interposers are formed by encapsulating microelectronic dies and/or posts within cavities in a substrate.

Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.

Abstract: A method of making a circuitized substrate in which pairs of vertically oriented though holes are formed such that at least one of the through holes is partially embedded within a lower one, thus assuring a sound connection following subsequent lamination or other steps the substrate including such holes is subjected to during manufacture. An electrical assembly including a substrate with such features is also provided.

Abstract: A method is described by which an electrical path is created between layers on a printed circuit board (PCB) without the use of plated through holes (PTH). Through the use of a liquid solder or conductive epoxy injection fixture, a conductive path is created in pre-drilled holes forming an electrical connection between internal PCB metal layers and surface mounted components without the creation of parasitic stubs on the signal nets.

Abstract: A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.

Abstract: A first insulating layer is formed on a suspension body, and a write wiring trace is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer so as to cover the wiring trace. A write wiring trace is formed, above the write wiring trace, on the second insulating layer. A ground trace is formed on one side of the write wiring trace at a distance on the second insulating layer. A third insulating layer is formed on the second insulating layer so as to cover the wiring trace and the ground trace. An opening is formed in a region, below the write wiring trace, of the suspension body.

Abstract: A method for manufacturing a multilayer FPCB includes the steps of: providing a first copper clad laminate, a second copper clad laminate and a binder layer; defining an opening on the binder layer; defining a first slit on the first copper clad laminate; laminating the first copper clad laminate, the binder layer and the second copper clad laminate; defining a via hole for establishing electric connection between the first copper clad laminate and the second copper clad laminate; cutting the first copper clad laminate, the binder layer and the second copper clad laminate thereby forming a multilayer flexible printed circuit board having different numbers of layers in different areas.

Abstract: A device includes a plane metallization layer, and a plane plated through hole attached to the plane metallization layer and terminating at the at a major exterior surface with a plurality of component mounting pads. The plated through hole is attached to the plane metallization layer. The plane plated through hole is electrically isolated from the plurality of component mounting pads at the exterior surface. A method for testing the device includes contacting the signal carrying through hole, and contacting the plane through hole, and checking for current flow between the signal carrying through hole and the plane through hole. If current flows between the signal carrying through hole and the plane through hole the device fails. If no current flows between the signal carrying through hole and the plane through hole the device passes.

Abstract: A front-and-back electrically conductive substrate includes a plurality of posts composed of a material that can be anisotropically etched and having an electrically conductive portion that has at least a first surface and a second surface that communicate with each other, and an insulative substrate that supports the plurality of posts.

Abstract: A conductive portion is formed in a hole formed in a material sheet. A metal foil is placed on a surface of the material sheet to provide a laminated sheet. The laminated sheet is heated and pressed to provide a circuit-forming board. The metal foil includes a pressure absorption portion and a hard portion adjacent to the pressure absorption portion. The pressure absorption portion has a thickness changing according to a pressure applied thereto. The circuit-forming board provided by this method provides a high-density circuit board of high quality having reliable electrical connection.

Abstract: In one embodiment, a printed circuit board includes a plurality of insulating layers in which an aperture is formed through some of the layers. A resistive plug at least partially fills the aperture and contacts respective conductive members at each end of the resistive plug to form a resistive via that traverses partially through the printed circuit board. In another embodiment, a printed circuit board includes a plurality of insulating layers in which an aperture is formed through at least some of the layers. A dielectric plug at least partially fills the aperture and contacts respective conductive members at each end of the dielectric plug to form a capacitive via that traverses at least partially through the printed circuit board.

Abstract: Aluminum filled via disks are manufactured utilizing a plurality of drilled substrates placed into a metal can in a stacked, interdisposed assembly with a corresponding number of graphite molds. Aluminum infiltration ingots are added and the can is heated to a temperature to melt the ingots. The molten aluminum is pressurized so that it flows into the vias. The substrates are then cooled, removed from the can, separated from between the graphite molds, and the flat surface faces are ground and polished to expose the filled vias.

Abstract: A process for fabricating a circuit board includes: providing a substrate including a first electrically conductive core having a first insulating coating on a first side and a second insulating coating on a second side, forming an opening in the first and second insulating coatings and the first electrically conductive core, exposing an edge of the conductive core within the opening, and electrodepositing a third insulating material on the exposed edge of the first electrically conductive core. A circuit board fabricated using the process is also provided.

Abstract: Closed vias are formed in a multilayer printed circuit board by laminating a dielectric layer to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer.

Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.

Abstract: A multilayer printed wiring board including an insulation layer and a first interlayer resin insulation layer provided on the insulation layer. A layered capacitor section is provided on the first interlayer resin insulation layer and has a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. Also included is a second interlayer resin insulation layer provided on the first interlayer resin insulation layer and the layered capacitor section, and a metal thin-film layer provided over the layered capacitor section and on the second interlayer resin insulation layer. An outermost interlayer resin insulation layer is provided on the second interlayer resin insulation layer and the metal thin-film layer, and a mounting section is provided on the outermost interlayer resin insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each interlayer resin insulation layer.

Abstract: A printed wiring board having a through hole conductor formed on the surface of a through hole formed in a copper-clad laminate board, and on the surface of the copper-clad laminate board 1 in the vicinity of an opening of the through hole. The through hole conductor is filled with a positive photosensitive resin. A capped conductor is formed on the positive photosensitive resin and is coupled to the through hole conductor. Further, a circuit pattern is formed on the surface of the copper-clad laminate board. An insulating layer is formed on the surface of the copper-clad laminate board, capped conductor, and the circuit pattern, and formed with a via hole extending from the surface of the insulating layer to the capped conductor. A via conductor is formed inside the via hole and on the surface of the insulating layer in the vicinity of an opening of the via hole.

Abstract: A multilayer printed wiring board includes: an insulating base including an indentation section formed thereon; a conductor pattern formed on the insulating base, the conductor pattern including a thick film section formed by embedding a conductor in the indentation section; and a via hole section formed in an upper layer of the insulating base, the via hole section including a bottom portion that is in contact with the thick film section.

Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.

Abstract: An electrically conductive shock mount system for electrical subassemblies is provided. The shock mount system includes a first assembly having a housing containing a hook member for a hook and loop fastener. The second assembly has a housing containing a loop member for a hook and loop fastener. A plurality of holes in the housings of the first and second assemblies allows the hook member to engage the loop member. In one embodiment, the housings are made from a conductive fabric and include a plurality of conductive columns that extend through the housings.

Abstract: A multilayer printed wiring board is composed of a substrate provided with through-holes, and a wiring board formed on the substrate through the interposition of an interlaminar insulating resin layer, the through-holes having a roughened internal surface and being filled with a filler, an exposed part of the filler in the through-holes being covered with a through-hole-covering conductor layer, and a viahole formed just thereabove being connected to the through-hole-covering conductor layer. Without peeling between the through-holes and the filler, this wiring board has a satisfactory connection reliability between the through-holes and the internal layer circuit and provides a high density wiring.

Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.