Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

Abstract: A multilayer printed wiring board is characterized in that the interlayer connection material in the via holes has a lower coefficient of thermal expansion in the thickness direction than the electrically insulating substrate made of insulating material; the interlayer connection is formed at a temperature higher than the operating temperature; and the interlayer connection material is larger in thickness than the interlayer connection material of the same wiring layer at normal temperature. This causes a difference in the coefficient of thermal expansion between the different materials in the thickness direction of the printed wiring board in the environment in which it is used resulting in high connection reliability.

Abstract: A printed wiring board including a substrate having first and second surfaces and a penetrating hole extending through the substrate between the surfaces, a first conductive circuit on the first surface, a second conductive circuit on the second surface, and a through-hole conductor in the hole and connecting the first and second conductive circuits. The conductor includes an electroless plated film on the inner-wall surface of the hole, a first electrolytic plated film formed on the electroless plated film and forming a first opening portion opening on the first surface and a second opening portion opening on the second surface, a second electrolytic plated film filling the first portion, and a third electrolytic plated film filling the second portion. The first and second portions taper toward the central portion of the hole with respect to the axis direction of the hole and have cross sections forming a substantially U-shape, respectively.

Abstract: A wiring substrate includes a first insulation layer, a connection terminal, a second insulation layer, a via, and a wiring pattern. The connection terminal is disposed in the first insulation layer so as to be exposed from a first main surface of the first insulation layer, and is electrically connected with a semiconductor chip. The second insulation layer is disposed on a second main surface of the first insulation layer situated on the opposite side from the first main surface. The via is disposed in the second insulation layer, and is electrically connected with the connection terminal. The via is separated from the connection terminal. The wiring pattern is disposed on the second main surface of the first insulation layer and electrically connects the connection terminal and the via.

Abstract: A method and apparatus for filling a via with transparent material is presented, including the steps of providing a panel having a via, occluding the via with transparent material in a workable state so that a portion of the occluding material is internal to the via and a portion of the material is external to said via. The external and internal portions are separated so the transparent filler material, when set, forms a smooth and featureless surface. This causes the filled via to have a substantially even and uniform appearance over a wide range of viewing angles when lit.

Abstract: In accordance with an embodiment, the printed circuit board, having an analog circuit and a digital circuit includes: a first metal layer and a second metal layer, one of the first metal layer and the second metal layer being a power layer and the other being a ground layer; a third metal layer, layer-built between the first metal layer and the second metal layer; and a mushroom type structure including a via connected to a metal plate, the metal plate being arranged in a space between circuit patterns of the third metal layer.

Abstract: A multilayered printed circuit board including a substrate, a multilayered structure built thereon and having conductor circuits and interlaminar resin insulating layers in an alternate fashion, and one or more stack-via structures including via-holes stacked one another and electrically connected to the conductor circuits through the insulating layers. Each of the via-holes includes a land portion formed on a respective one of the insulating layers and a filled via structure portion filling an opening of the respective one of the insulating layers with a metal layer such that the via-holes are stacked one another immediately above the filled via structure portion of each via-hole, the via-holes include the outermost layer via-hole in the outermost layer of the insulating layers, and one or more via-holes have the land portion having the land diameter which is larger than the land diameter of the land portion of the outermost layer via-hole.

Abstract: A wiring board has a first rigid wiring board having a substrate with a penetrating hole, a first insulation layer formed on the substrate to cover at least one opening of the penetrating hole, and a first wiring layer formed on the first insulation layer, a second rigid wiring board having a second wiring layer on a main surface and being accommodated in the penetrating hole, a first connection conductor which connects the first wiring layer and the second wiring layer, and a first interlayer insulation layer formed on the first wiring layer.

Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract: A wiring unit includes a first insulating layer which is provided with an electrode and a wire electrically connected to the electrode on one surface of the first insulating layer; a second insulating layer which is formed on the one surface of the first insulating layer and which covers the wire; an adhesive layer which is formed on a surface, of the second insulating layer, not facing the first insulating layer; a through hole which is formed through the adhesive layer and the second insulating layer and in which the electrode is exposed; a protective sheet which is detachably adhered on a surface, of the adhesive layer, not facing the second insulating layer, and; and a liquid electroconductive material which is filled in a space defined by the through hole, the electrode exposed in the through hole, and the protective sheet.

Abstract: A printed wiring board includes an interlayer resin insulation layer having the first surface, the second surface on the opposite side of the first surface, and a penetrating hole for a via conductor, a conductive circuit formed on the first surface of the interlayer resin insulation layer, a via conductor formed in the penetrating hole and connected to the conductive circuit on the first surface of the interlayer resin insulation layer, and a surface-treatment coating formed on the surface of the via conductor exposed from the second surface of the interlayer resin insulation layer through the penetrating hole. The via conductor is made of a first conductive layer formed on the side wall of the penetrating hole and a plated-metal filling the penetrating hole. The surface of the via conductor is recessed from the second surface of the interlayer resin insulation layer.

Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.

Abstract: The invention is a hermetic via in a ceramic substrate that is comprised of noble metal powder in a glass-free paste that contains an admixture of a particulate phase of niobium pentoxide. The electrically conductive platinum provides excellent electrical conductivity while the niobium pentoxide phase prevents shrinkage of the paste during thermal processing and binds to both the ceramic and the noble metal particulates in the via, thus maintaining a hermetic seal around the via.

Abstract: The present invention provides a ceramic substrate including: a ceramic stacked layer structure in which multiple ceramic layers are stacked to be interconnected through a via provided within each of the ceramic layers, the ceramic stacked layer structure having a hole provided therein to expose a top portion of the via provided within a ceramic layer of being a surface layer; a conductive material filled within the hole; and an external electrode formed on the surface of the ceramic stacked layer structure so that the external electrode is electrically connected to the conductive material, and a manufacturing method thereof.

Abstract: A coreless packaging substrate includes: a substrate body including an auxiliary dielectric layer having opposing first and second surfaces, an inner wiring formed on the second surface, and a built-up structure formed on both the second surface of the auxiliary dielectric layer and the inner wiring; and a plurality of conductive bumps including metal pillars having opposing first and second ends and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer and electrically connecting with the inner wiring, and the first ends of the metal pillars with the solder layer protrude from the first surface of the auxiliary dielectric layer, thereby achieving ultra-fine pitch and even-height conductive bumps. A method for fabricating the coreless packaging substrate as described above is further provided.

Abstract: A multi-layer printed circuit board including a first insulating layer, a first conductor layer having conductor circuits on one surface of the first insulating layer, a second conductor layer having conductor circuits on the opposite surface of the first insulating layer, a second insulating layer on the second conductor and first insulating layers, and a third conductor layer having conductor circuits on the second insulating layer on the opposite side of the second conductor layer. The first and second insulating layers have first and second via holes which are formed in openings of the first and second insulating layers and made of conductive materials filled to the top of the openings such that conductor circuits in the first and third conductor layers are connected to one or more conductor circuits in the second conductor layer, and the first and second via holes are tapering toward the second conductor layer.

Abstract: The formation of electronic assemblies is described. One embodiment includes providing a body and forming a first metal pad layer on a first surface thereof. A second metal pad layer is formed in contact with the first metal pad layer, the second metal pad layer having a denser pitch than the first metal pad layer. A dielectric layer is formed between the metal pads in the first and second metal pad layers. Vias extending through the body from a second surface thereof are formed, the vias exposing the first metal pad layer. An insulating layer is formed on via sidewalls and on the second surface, and an electrically conductive layer formed on the insulating layer and on the exposed surface of the first metal layer. Elements are coupled to the second metal pad layer and the electrically conductive layer coupled to a substrate. Other embodiments are described and claimed.

Abstract: Disclosed herein is a method of manufacturing a heat radiation substrate, including injection-molding mixed powder of carbon nanotubes and metal in a die to fabricate a metal core having through holes; molding the entire metal core including the through holes with an insulating resin to fabricate a metal core substrate; processing the insulating resin provided in the through holes to form connection holes; and forming a circuit pattern on the metal core substrate in which the connection holes are formed.

Abstract: A circuit board includes a core layer substrate having a plated through hole filled with a dielectric material. The plated through hole has a sidewall coated with an inner electroless copper layer, and an electroplated metal layer plated on the inner electroless copper layer before the plated through hole is filled with the dielectric material. The outer portion of the filled plated through hole is thicker than the center portion and tapered toward the center portion to form a depressed surface on the filled plated through hole. The core layer substrate is covered with a patterned electroless copper layer and a patterned electroplated copper layer that connect with the inner electroless copper layer and electroplated metal layer of the plated through hole. The patterned electroplated copper layer forms a flat copper pad above the plated through hole.

Abstract: A package substrate, a manufacturing method thereof, a base package module, and a multi-layered package module having package substrates laminated on upper and lower portions of a base package module are provided. The base package module includes a base metal substrate, a first metal oxide layer that is formed on the base metal substrate to have a cavity therein, a device that is mounted in the cavity on the base metal substrate and insulated by the first metal oxide layer formed on a sidewall in the cavity, and a conductor that is connected to the device and a wiring pad formed on the first metal oxide layer on the base metal substrate. The package substrate includes a wiring pad, a conductor line, a second metal oxide layer having an opening that exposes a device, and a via that is connected to the wiring pad through a connection pad in the second metal oxide layer.

Abstract: The present invention provides a circuit board structure, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.

Abstract: An integrated circuit semiconductor device includes a substrate, a deep via within the substrate which is provided with a dielectric cladding in contact with the substrate, metal fill located within the deep via and defining an upper surface, interconnect wiring, and a dielectric layer located above the deep via and a void between the upper surface of the metal fill and the dielectric layer. The interconnect wiring layer contacts the metal fill laterally.

Abstract: A method for manufacturing a double-sided circuit board includes preparing a substrate having the first and second surfaces, forming a first hole having a first opening with a diameter R1 on the first surface of the substrate, forming a second hole having a second opening with a diameter R2 on the second surface of the substrate, forming a third hole having a diameter smaller than R1 and/or R2 and connecting the first and second holes such that a penetrating hole formed of the first hole, the second hole and the third hole is formed in the substrate, forming a first conductive circuit on the first surface of the substrate, forming a second conductive circuit on the second surface of the substrate, and filling the penetrating hole with conductive material such that a through-hole conductor electrically connecting the first conductive circuit and the second conductive circuit is formed.

Abstract: A wiring board includes a core substrate having a structure including an insulating base material and a large number of filamentous conductors densely provided in the insulating base material and piercing the insulating base material in a thickness direction thereof. Pads made of portions of wiring layers are oppositely disposed on both surfaces of the core substrate and electrically connected to opposite ends of a plurality of filamentous conductors in such a manner that the pads share the filamentous conductors. A wiring connection between one surface side and the other surface side of the core substrate is made through the pads. The insulating base material is made of an inorganic dielectric. Pads made of portions of the wiring layers are disposed on both surfaces of the core substrate and electrically connected only to corresponding one end sides of different groups each formed of a plurality of filamentous conductors.

Abstract: A multilayer printed circuit board has an IC chip (20) included in a core substrate (30) in advance and a transition layer (38) provided on a pad (24) of the IC chip (20). Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer (38) made of copper on the die pad (24), it is possible to prevent resin residues on the pad (24) and to improve connection characteristics between the pad (24) and a via hole (60) and reliability.

Abstract: A circuit board structure with an embedded semiconductor element and a fabrication method thereof are disclosed according to the present invention. The circuit board structure comprises: a carrier board having a first surface, a second surface, and at least one through hole penetrating the carrier board from the first surface to the second surface; a first semiconductor element received in the through hole and having an active surface and an inactive surface, the active surface having a plurality of electrode pads; at least one second semiconductor element mounted on the carrier board; a first encapsulation layer formed on the first surface of the carrier board to block one end of the through hole; and a second encapsulation layer formed on the second surface of the carrier board.

Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.

Abstract: The present invention provides a method of manufacturing printed a circuit board capable of formation of via holes having a low aspect ratio and formation of fine lines, and a printed circuit board manufactured by the method. The method of manufacturing a printed circuit board 10 according to the present invention includes a step of selectively forming a plating layer 16 for lands 22a and 22b on a metal foil 14 on the printed circuit board 10, a step of adjusting the thickness of the plating layer 16, and a step of forming the metal foil 14 into lines 14a. The aspect ratio of via holes 28 formed on lands 22a and 22b can be adjusted by adjusting the thickness of the lands 22a and 22b.

Abstract: A blind hole (3) is formed on a substrate (1) from a first side of the substrate toward a second side of the substrate (1). A conductor (11) is filled in the blind hole (3). The substrate (1) is removed from the opposite side to expose the conductor (13) filled in the blind hole (3).

Abstract: The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided LCP, where both the high and low temperature LCP are provided with a z-axis connection. The single sided conductive layer is a bus layer to form z-axis conductive stud within the high and low temperature LCP. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond.

Abstract: Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.

Abstract: A multilayer printed wiring board includes: an insulating base including an indentation section formed thereon; a conductor pattern formed on the insulating base, the conductor pattern including a thick film section formed by embedding a conductor in the indentation section; and a via hole section formed in an upper layer of the insulating base, the via hole section including a bottom portion that is in contact with the thick film section.

Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.

Abstract: A multilayer printed wiring board comprises insulating layers and conductor layers being stacked alternately on each other. The conductor layers are electrically connected to each other through viaholes formed in the insulating layers. Each of the viaholes is formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. The multilayer printed wiring board is to have electronic components such as a capacitor, IC and the like mounted on the surface layer thereof.

Abstract: A multilayer ceramic substrate includes a plurality of stacked glass ceramic layers and internal conductors. The glass ceramic layers contain at least one diffusion element selected from the group consisting of Ti, Zr and Mn. The internal conductors contain Ag as a conductive material. The multilayer ceramic substrate is produced by the steps of adding at least one diffusion element selected from the group consisting of Ti, Zr and Mn to conductive paste and diffusing the diffusion element in the glass ceramic layers around the conductive paste. As a result, defects otherwise possibly generated around the internal conductors can be eliminated with exactitude.

Abstract: A capture pad structure includes a lower dielectric layer, a capture pad embedded within the lower dielectric layer, the capture pad comprising a plurality of linear segments. To form the capture pad, a focused laser beam is moved linearly to form linear channels in the dielectric layer. These channels are filled with an electrically conductive material to form the capture pad.

Abstract: A printed wiring board includes a substrate having a first surface, a second surface on the opposite side of the first surface and a through-hole extending between the first and second surfaces, a first conductive circuit formed on the first surface of the substrate, a second conductive circuit formed on the second surface of the substrate, and a through-hole conductor filling the through-hole and connecting the first and second conductive circuits. The through-hole has a first opening portion tapering from the first surface toward the second surface and a second opening portion tapering from the second surface toward the first surface. The substrate is made of a resin and a reinforcing material portion in the resin. The reinforcing material portion has a protruding portion protruding into the through-hole at the intersection of the first and second opening portions. The protruding portion encroaches into the through-hole conductor.

Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 ?m or less.

Abstract: A multilayer printed wiring board comprises insulating layers and conductor layers being stacked alternately on each other. The conductor layers are electrically connected to each other through viaholes formed in the insulating layers. Each of the viaholes is formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. The multilayer printed wiring board is to have electronic components such as a capacitor, IC and the like mounted on the surface layer thereof.

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board can include: processing a first hole, which has a tapered shape, in one side of a substrate by using a laser drill; processing a second hole, which has a tapered shape and which connects with the first hole, in the other side of the substrate by using a laser drill in a position corresponding to that of the first hole; and forming a conductive portion, which electrically connects both sides of the substrate through the first hole and the second hole, by performing plating. This method may be used for providing reliable interlayer connections.

Abstract: Holes having the same diameter as via holes are formed in predetermined positions in advance when forming wiring patterns on releasable carriers. The carriers with the wiring patterns are bonded on an insulating material, and a laser beam is irradiated from the side of the carrier using the holes in the wiring pattern as a laser mask to form via holes in the insulating material. The via holes and the holes in the carrier are then filled with a conductive paste. With the holes in the carrier that are matched in position with the via holes, lands in the conductor layers are precisely positioned relative to the via holes. A multilayer circuit board thus produced has lower electrical connection resistance and excellent mountability with improved performances. Also a manufacturing method thereof is achieved.

Abstract: A semiconductor mounting board 80 is prepared by electrically joining an IC chip 70 via an interposer 60 of high rigidity to external pads 41 and internal pads 43, which are formed on the uppermost surface of a build-up layer 30. When the IC chip 70 generates heat, since pads 41 are positioned away from the center, a large shearing stress is applied to the portions at which pads 41 are joined to the interposer 60 in comparison to the portions at which pads 43 are joined to the interposer 60. Here, pads 41 are formed at substantially flat wiring portions and thus when joined to the interposer 60 by means of solder bumps 51, voids and angled portions, at which stress tends to concentrate, are not formed in the interiors of solder bumps 51. The joining reliability is thus high.

Abstract: An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation.

Abstract: A multilayer ceramic substrate includes a plurality of ceramic layers laminated each other. The plurality of ceramic layers form a bulge and a cavity having such a shape that an opening area of the cavity gradually becomes smaller toward a bottom of the cavity.

Abstract: An electronic component mounting structure includes a board and an electronic component mounted on a surface of the board. The board includes lands. The electronic component includes a body and terminals extending from the body. Each terminal is electrically connected to a corresponding one of the lands of the board. The terminal has a first terminal portion extending along the surface of the board and a second terminal portion extending toward the surface of the board. Each land includes a land portion electrically soldered to the first terminal portion and a blind hole for receiving the second terminal portion. The first terminal portion is soldered to the land portion in a reflow process under the condition that the second terminal portion is inserted in the blind hole.

Abstract: The invention concerns a method which consists in coating uniformly the non-developable surface (6) with an electrically conductive material (9), which is in turn coated, by spraying, with a pattern (10) of polymerizable protective material, said pattern being polymerized as it is being formed, and then selectively eliminating, through the openings (10.8) of said pattern (10), the portions of said electrically conductive material (9) which do not over said electrically conductive patterns.

Abstract: A multi-layer printed circuit board including a core structure including resin layers and conductor circuits sandwiched by the resin layers, the core structure having a first surface and a second surface on an opposite side of the first surface, a first conductor layer including conductor circuits formed on the first surface of the core structure, and a second conductor layer including conductor circuits formed on the second surface of the core structure. The core structure includes a first via hole and a second via hole, the first via hole and the second via hole sandwich one or more conductor circuits in the core substrate and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and the second conductor layers, and the first via hole and the second via hole are deviated from each other in a vertical direction.

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 ?m and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 ?m. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract: A built-up printed circuit board includes stacked micro via-holes, each of which is provided for interconnection between layers in the printed circuit board, and in each of which a filling material, such as liquefied resin or conductive paste, is filled using a poly screen of a general screen printing machine.

Abstract: A non-shrinkage ceramic substrate includes: a ceramic laminated body formed by laminating a plurality of green sheets; an electrode part including a via electrode penetratingly formed at the ceramic laminated body and an outer electrode formed on a surface of the ceramic laminated body and electrically connected with the via electrode; and an interface part formed between the ceramic laminated body and the electrode part to prevent an electrical connection between the electrodes from weakening.