Voidless (e.g., Solid) Patents (Class 174/264)
  • Patent number: 8314348
    Abstract: A multilayer printed wiring board includes a first interlaminar resin insulating layer, a first conductor circuit formed on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer formed on the first interlaminar resin insulating layer and the first conductor circuit, a second conductor circuit formed on the second interlaminar resin insulating layer. A via conductor can be formed in the opening portion. The opening portion of the second interlaminar resin insulating layer can expose a face of the first conductor circuit. The via conductor connects the first conductor circuit and the second conductor circuit. The via conductor includes an electroless plating film formed on inner wall face of the opening portion and includes an electrolytic plating film formed on the electroless plating film and on the exposed face of the first conductor circuit exposed by the opening portion.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: November 20, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Toru Nakai, Sho Akai
  • Patent number: 8310840
    Abstract: Disclosed are an electromagnetic bandgap structure and a printed circuit board including the same. In accordance with an embodiment of the present invention, the printed circuit board can include a dielectric layer, a plurality of conductive plates, and a stitching via, which is configured to electrically connect the conductive plates to each other. The stitching via can pass through the dielectric layer, and a part of the stitching via can be placed in a planar surface that is different from a planar surface in which the conductive plates are placed. With the present invention, the electromagnetic bandgap structure can prevent a signal of a predetermined frequency band from being transferred.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: November 13, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Je-Gwang Yoo, Chang-Sup Ryu
  • Patent number: 8304657
    Abstract: A printed wiring board includes a core substrate having a penetrating hole, a first circuit on a first surface of the substrate, a second circuit on a second surface of the substrate, and a through-hole conductor in the hole connecting the first and second circuits. The hole has first and second opening portions. The first opening portion becomes thinner toward the second surface. The second opening portion becomes thinner toward the first surface. The first opening portion has first and second portions. The second opening portion has first and second portions. The first and second portions of the first opening portion form inner walls bending inward at the boundary between the first and second portions. The first and second portions of the second opening portion form inner walls bending inward at the boundary between the first and second portions.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: November 6, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Hiroyuki Sato, Tomohiko Murata, Fusaji Nagaya
  • Patent number: 8304665
    Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 6, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Yen-Ping Wang, Don-Son Jiang, Jeng-Yuan Lai, Yu-Po Wang
  • Patent number: 8300421
    Abstract: An electronic component and a method of manufacturing an electronic component including a first surface mount device and a second surface mount device are provided. The first surface mount device and the second surface mount device are joined to a substrate via joint materials such that either or both of the first and second surface mount devices are shifted from the locations corresponding to land electrodes located on the substrate so as to be aligned with each other and are subjected to a reflow process. The outer land electrodes are formed at locations shifted inwardly from the locations corresponding to a virtual arrangement state in which the first surface mount device and the second surface mount device are arranged in series such that an end surface of the first surface mount device is in contact with an end surface of the second surface mount device.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 30, 2012
    Assignee: Murata manufacturing Co., Ltd.
    Inventor: Yasuo Yokoyama
  • Publication number: 20120261179
    Abstract: An interposer substrate of the present invention includes a planar substrate, and through hole wiring that is formed by filling a through hole that connects together a first main surface and a second main surface of this substrate with a conductor. When the through hole is viewed in a vertical cross-sectional view of the substrate, the through hole has a trapezoidal shape whose side walls are formed by an inside surface of the through hole, and two side faces of the trapezoid are not parallel to each other. The two side faces of the trapezoid are both inclined towards the same side relative to two perpendicular lines that are perpendicular to the first main surface or the second main surface at two apex points forming a top face or a bottom face of the trapezoid.
    Type: Application
    Filed: June 21, 2012
    Publication date: October 18, 2012
    Applicant: FUJIKURA LTD.
    Inventors: Satoshi YAMAMOTO, Takanao SUZUKI, Masami MATSUYAMA
  • Patent number: 8288662
    Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: October 16, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chang-Ming Lee, Wen-Fang Liu, Cheng-Po Yu
  • Patent number: 8288657
    Abstract: An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jinwoo Choi, Sungjun Chun, Anand Haridass, Roger Weekly
  • Patent number: 8288665
    Abstract: A multi-layer printed circuit board including a first insulating layer, a first conductor layer having conductor circuits on one surface of the first insulating layer, a second conductor layer having conductor circuits on the opposite surface of the first insulating layer, a second insulating layer on the second conductor and first insulating layers, and a third conductor layer having conductor circuits on the second insulating layer on the opposite side of the second conductor layer. The first and second insulating layers have first and second via holes which are formed in openings of the first and second insulating layers and made of conductive materials filled to the top of the openings such that conductor circuits in the first and third conductor layers are connected to one or more conductor circuits in the second conductor layer, and the first and second via holes are tapering toward the second conductor layer.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: October 16, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Dongdong Wang, Takahiro Mori
  • Patent number: 8288664
    Abstract: A metal layer 18 is sandwiched between insulating layers 14 and 20 so that required strength is maintained. Hence it follows that the thickness of a core substrate 30 can be reduced and, therefore, the thickness of a multi-layer printed circuit board can be reduced. Formation of non-penetrating openings 22 which reach the metal layer 18 in the insulating layers 14 and 20 is simply required. Therefore, small non-penetrating openings 22 can easily be formed by applying laser beams. Thus, through holes 36 each having a small diameter can be formed.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: October 16, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Dongdong Wang, Takahiro Mori
  • Publication number: 20120256320
    Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and a first electrode pad 130 is formed on a chip mounting side. A taper surface 132 of the first electrode pad 130 has a gradient in an orientation reduced in an upward direction toward a solder connecting side or a chip mounting side. Therefore, a holding force for a force applied to the solder connecting side or the chip mounting side is increased, and furthermore, the taper surface 132 adheres to a tapered internal wall of an insulating layer of a first layer so that a bonding strength to the insulating layer is increased.
    Type: Application
    Filed: June 18, 2012
    Publication date: October 11, 2012
    Applicant: SHINKO ELECTRIC ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kentaro Kaneko
  • Patent number: 8283573
    Abstract: A multi-layer printed circuit board including a core structure including resin layers and conductor circuits sandwiched by the resin layers, the core structure having a first surface and a second surface on an opposite side of the first surface, a first conductor layer including conductor circuits formed on the first surface of the core structure, and a second conductor layer including conductor circuits formed on the second surface of the core structure. The core structure includes a first via hole and a second via hole, the first via hole and the second via hole sandwich one or more conductor circuits in the core substrate and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and the second conductor layers, and the first via hole and the second via hole are deviated from each other in a vertical direction.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: October 9, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Dongdong Wang, Takahiro Mori
  • Publication number: 20120247824
    Abstract: A suspension board with circuit includes a conductive pattern on a top surface thereof. A folded-back portion that is capable of being folded back toward a back surface side is provided therein. At the circumference edge of the folded-back portion, a part of the circumference edge is continuous to the suspension board with circuit around the folded-back portion via a bent portion and the remaining portion of the circumference edge is disposed apart from the suspension board with circuit around the folded-back portion by a penetrating space that penetrates the suspension board with circuit in a thickness direction. The conductive pattern at least includes a top-surface-side terminal that is disposed on the top surface of the suspension board with circuit and a back-surface-side terminal that is disposed in the folded-back portion.
    Type: Application
    Filed: March 16, 2012
    Publication date: October 4, 2012
    Applicant: NITTO DENKO CORPORATION
    Inventor: Tetsuya OHSAWA
  • Patent number: 8274181
    Abstract: A structure for transmission in a power supply, particularly to a power structure for transmission for bearing large DC current, wherein the power supply includes a power input port for connecting to DC input power and a DC/DC conversion circuit for converting the DC input power into DC output power. The architecture including at least one power transmission board for disposing the power input port, wherein the power transmission board is electrically connected to the power process board with the DC/DC conversion circuit mounted thereon by at least one power conduction element. Therefore, through the power conduction elements replacing the conventional connecting wires with large diameter to connect the power input port and the power process board without disobeying the safety regulation, not only the space occupied by the bent connection wires can be reduced, but the collisions and damage to other components caused therefrom also can be avoided.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: September 25, 2012
    Assignees: FSP Technology Inc., 3Y Power Technology (Taiwan), Inc.
    Inventor: Shao-Feng Lu
  • Patent number: 8258410
    Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.
    Type: Grant
    Filed: January 26, 2008
    Date of Patent: September 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
  • Patent number: 8253031
    Abstract: A printed circuit board can support different connectors by selectively setting connection components on the printed circuit board without changing wiring of transmission lines or making new vias in the printed circuit board.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: August 28, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yung-Chieh Chen, Cheng-Hsien Lee, Shou-Kuo Hsu, Shen-Chun Li, Hsien-Chuan Liang, Shin-Ting Yen
  • Patent number: 8253027
    Abstract: According to one embodiment of the invention, a circuit board comprises a conductive layer including a land portion and a line portion connected to the land portion, and; a conductor connected to a surface of the land portion. A planar shape of the connected portion between the conductor and the land portion has a elongated shape along a width direction of the line portion. A part of the connected portion is located within an imaginary region formed by imaginarily extending the line portion toward the land portion.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: August 28, 2012
    Assignee: Kyocera Corporation
    Inventors: Kimihiro Yamanaka, Manabu Ichinose, Satoshi Nakamura
  • Publication number: 20120199389
    Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.
    Type: Application
    Filed: April 10, 2012
    Publication date: August 9, 2012
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Takeshi Furusawa
  • Patent number: 8238109
    Abstract: A flex-rigid wiring board including a flexible printed wiring board, a rigid printed wiring board, a first connection terminal formed over the rigid printed wiring board and positioned to be mounted onto a motherboard, and a second connection terminal formed over the rigid printed wiring board and positioned to mount an electronic component. The flexible printed wiring board has a first conductive layer, the rigid printed wiring board has a rigid base material, an insulation layer over the rigid base material and a second conductive layer formed over the insulation layer. The insulation layer covers at least a portion of the flexible printed wiring board and at least a portion of the rigid base material while exposing at least a portion of the flexible printed wiring board, and the first conductive layer and the second conductive layer are connected through a plated metallic layer penetrating through the insulation layer.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: August 7, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventor: Katsumi Sagisaka
  • Publication number: 20120194617
    Abstract: The present invention provides a method of manufacturing a substrate which forms a wiring pattern on a substrate having a plurality of through-holes. In the method, the wiring pattern is formed, after burying a filling material into the through-holes and planarizing a surface of the substrate. The filling material may be a conductive material, and a portion of the conductive material may be removed after the wiring pattern is formed. Removal of the portion of the conductive material may be carried out after a protective film, which protects the wiring pattern, is formed. The filling material may be a conductive material and a sacrificial material, and the sacrificial material may be removed after the wiring pattern is formed.
    Type: Application
    Filed: April 11, 2012
    Publication date: August 2, 2012
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Regan Nayve, Michiaki Murata
  • Patent number: 8232477
    Abstract: In a curable resin composition containing an inorganic filler, the average particle diameter of the inorganic filler is 1 ?m or less and the content of the inorganic filler is 50 wt % or less. The curable resin composition can be preferably used for a halogen-free resin substrate and the like having a small load on an environment as a hole-plugging curable resin composition as well as used to provide a hole-plugging build-up printed wiring board having a via-on-via structure (in particular, a stacked via structure) having an excellent crack-resistant property, an excellent insulation/connection reliability, and the like.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: July 31, 2012
    Assignee: San-Ei Kagaku Co., Ltd.
    Inventors: Kazunori Kitamura, Yukihiro Koga, Kiyoshi Sato
  • Patent number: 8222532
    Abstract: A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 17, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Shigetsugu Muramatsu, Yasuhiko Kusama
  • Patent number: 8222529
    Abstract: The present invention provides a ceramic substrate including: a ceramic stacked layer structure in which multiple ceramic layers are stacked to be interconnected through a via provided within each of the ceramic layers, the ceramic stacked layer structure having a hole provided therein to expose a top portion of the via provided within a ceramic layer of being a surface layer; a conductive material filled within the hole; and an external electrode formed on the surface of the ceramic stacked layer structure so that the external electrode is electrically connected to the conductive material, and a manufacturing method thereof.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: July 17, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Je Hong Sung, Jin Waun Kim, Myung Whun Chang
  • Patent number: 8217279
    Abstract: A ceramic electronic component achieves a sufficient drop resistance strength even when terminal electrodes are formed with a higher density. The ceramic electronic component includes a ceramic laminate including ceramic laminates which are laminated to each other, first terminal electrodes disposed in a peripheral portion of a bottom surface of the ceramic laminate, catch pad electrodes arranged in the ceramic laminate so as to face the respective first terminal electrodes, and sets each including at least two first via hole conductors, which electrically connect the first terminal electrodes and the respective catch pad electrodes.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: July 10, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Daigo Matsubara, Osamu Chikagawa
  • Publication number: 20120168220
    Abstract: Disclosed herein are a multi-layer printed circuit board and a method of manufacturing the same. In the multi-layer printed circuit board and the method of manufacturing the same, circuit layers formed in a plurality of insulating layers are electrically interconnected through vias formed in a lump, thereby making it possible to secure bonding reliability of an interlayer circuit layer and more stably secure performance of the printed circuit board. In addition, since a stacked type via structure may be implemented by performing a via hole drilling process, a desmear process, and a copper plating process only one time after an insulating layer and an circuit layer are stacked, a manufacturing process, a manufacturing time, and manufacturing costs of the stacked type via structure may be reduced.
    Type: Application
    Filed: October 25, 2011
    Publication date: July 5, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Han Ul Lee, Byung Bae SEO, Chang Sup RYU, Yong Sam LEE
  • Publication number: 20120168221
    Abstract: A relay board for relaying plurality of electric wires to a transmission connector, the relay board provided with first and second front ground pads 12a, 12b which are arranged on a front surface, first and second back ground pads 13a, 13b which are arranged on a back surface, signal pads 14a to 15b which are arranged between the ground pads, a first via hole 17a which connected the first front ground pad 12a and the first back ground pad 13a, and a second via holes 17b which connects the second front ground pad 12b and second back ground pad 13b, the first via hole 17a and the second via hole 17b being arranged at the both sides of the signal pads. It is possible to provide an inexpensive relay board with excellent transmission characteristics and grounding characteristics.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 5, 2012
    Applicant: FUJITSU COMPONENT LIMITED
    Inventors: Takeshi Okuyama, Tohru Yamakami
  • Patent number: 8206536
    Abstract: A method of stacking a flexible substrate is provided. The method includes the steps of: preparing a carrier substrate; stacking an adhesive layer on the carrier substrate; and stacking a flexible substrate having at least one image display device on the adhesive layer using a laminating or pressing method. Thus, the flexible substrate is easily fabricated without modification of conventional mass-production equipment for fabricating a display, and thereby a lightweight, thin, and compact flexible display can be realized.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: June 26, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gi Heon Kim, Yong Hae Kim, Dong Jin Park, Chul Am Kim, Kyung Soo Suh
  • Publication number: 20120145447
    Abstract: Disclosed herein is a via structure with a conductive via. There is provided a via structure, including: a substrate laminate having a multilayer structure and a via hole penetrating through the multilayer structure; a first circuit pattern formed on one surface of the substrate laminate; a second circuit pattern formed on the other surface of the substrate laminate; and a conductive via formed in the via hole and having one end connected to the first circuit pattern and the other end connected to the second circuit pattern, wherein the multilayer structure includes resin layers having different etching rates using an alkaline solution.
    Type: Application
    Filed: April 8, 2011
    Publication date: June 14, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Bonghie Jung, Minjung Cho, Kwangseop Youm, Younghwan Shin, Kyoungro Yoon
  • Patent number: 8198546
    Abstract: A method of manufacturing a printed wiring board includes preparing a wiring substrate having a conductive circuit, coating a solder-resist layer over the conductive circuit, leveling a surface of the solder-resist layer so as to obtain a maximum surface roughness in a predetermined range, removing the resin film from the surface of the solder-resist layer, and forming multiple openings in the surface of the solder-resist layer to expose multiple portions of the conductive circuit so as to form multiple conductive pads for mounting an electronic components.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: June 12, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8199519
    Abstract: A chip adapter used to install a chip on a first chip arranging area of a circuit board includes a board. The size of the board has the same size as the first chip arranging area of the circuit board. Edges of the chip adapter define a number of gaps corresponding to first pads of the circuit board. A second chip arranging area of the same size as the chip is arranged in a center of the chip adapter. A number of second pads are arranged around the second chip arranging area of the chip adapter corresponding to pins of the chip. Each second pad is electrically connected to a sidewall of the corresponding gap of the chip adapter.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: June 12, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Ming-Chih Hsieh, Heng-Chen Kuo
  • Publication number: 20120138352
    Abstract: Insulating substrates may be selectively removed to form electrical connections between conductive patterns on different faces of the insulating substrate or between conductive patterns on the insulating substrate and external circuits.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 7, 2012
    Inventors: Carl CARLEY, David Brent Guard
  • Publication number: 20120132462
    Abstract: A circuit board comprises a substrate; a through hole penetrating the substrate along with a direction of a thickness thereof; and a through hole conductor covering an inner wall of the through hole. The substrate comprises a first fiber layer, a second fiber layer, and a resin layer arranged between the first fiber layer and the second fiber layer. Each of the first fiber layer and the second fiber layer has a plurality of fibers and a resin arranged among the plurality of the fibers. The resin layer contains a resin and doesn't contain a fiber. The inner wall of the through hole, in a cross-section view along with the direction of the thickness of the substrate, comprises a curved depression in the resin layer.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 31, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Masaaki Harazono, Yoshihiro Hosoi
  • Patent number: 8188866
    Abstract: A radio frequency identification (RFID) tag is coupled to a circuit board to track the specific operating and environmental conditions of each manufacturing stage as the circuit board passes through the manufacturing stages. An RFID reader and data collector are used at each stage to read the RFID tag and store its identifying information along with processing information, operating conditions, and results for each stage. This permits to quickly and accurately collect manufacturing information for each circuit board at various manufacturing stages as well as the operating conditions for each stage at a particular time. Such manufacturing metrics can then be retrieved on a stage-by-stage basis for a particular circuit board by an identifier printed on the circuit board.
    Type: Grant
    Filed: February 20, 2011
    Date of Patent: May 29, 2012
    Assignee: Sanmina-SCI Corporation
    Inventor: Rony Shachar
  • Patent number: 8183468
    Abstract: An electromagnetic bandgap structure and a printed circuit board including it as well as a method of manufacturing thereof that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. The electromagnetic bandgap structure in accordance with an embodiment of the present invention can include: a first metal layer; a first dielectric layer, stacked on the first metal layer; a metal plate, stacked on the first dielectric layer; a second dielectric layer, stacked on the metal plate and the first dielectric layer; a second metal layer, stacked on the second dielectric layer; and a via, directed from the metal plate to the first metal layer and the second metal layer. The via can be connected to the first metal layer and is not connected the second metal layer.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: May 22, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Dae-Hyun Park
  • Publication number: 20120111625
    Abstract: Disclosed herein is a method for filling a via hole of a printed circuit board, the method including: a dividing step of dividing a via hole that is to be formed in a base substrate into a predetermined number; a first via forming step of forming a first divided via by primarily processing portions of the divided via hole; a first filling step of filling the formed first divided via with a metal; a second via forming step of forming a second divided via by secondarily processing other portions of the divided via hole; and a second filling step of filling the formed second divided via with a metal to fill the via hole, thereby making it possible to fill the via hole without a dimple.
    Type: Application
    Filed: October 14, 2011
    Publication date: May 10, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kwangok Jeong, Hyoseung Nam
  • Publication number: 20120103679
    Abstract: A through wiring substrate includes a substrate having a first face and a second face; and a through-wire formed by filling, or forming a film of, an electrically-conductive substance into a through-hole, which penetrates between the first face and the second face. The through-hole has a bend part comprising an inner peripheral part that is curved in a recessed shape and an outer peripheral part that is curved in a protruding shape, in a longitudinal cross-section of the through-hole, and at least the inner peripheral part is formed in a circular arc shape in the longitudinal cross-section.
    Type: Application
    Filed: January 5, 2012
    Publication date: May 3, 2012
    Applicant: FUJIKURA LTD.
    Inventors: Satoshi YAMAMOTO, Hirokazu HASHIMOTO
  • Patent number: 8169790
    Abstract: An electromagnetic bandgap structure and a printed circuit board having the electromagnetic bandgap that intercepts the transfer of a signal ranging a frequency band are disclosed. The electromagnetic bandgap structure includes a metal layer; a dielectric layer, stacked on the metal layer; at least two metal plates, stacked on the same planar surface of the dielectric layer; and a stitching via, connecting the adjacent metal plates. The stitching via passes through the dielectric layer, and a part of the stitching via is placed on the same planar surface of the metal layer. With the present invention, the electromagnetic bandgap can decrease the noise of a particular frequency by having a compact size and a low bandgap frequency.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: May 1, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Je-Gwang Yoo, Chang-Sup Ryu
  • Patent number: 8169792
    Abstract: A multilayer printed wiring board includes: a build-up layer that is formed on a core substrate and has a conductor pattern disposed on an upper surface; a low elastic modulus layer that is formed on the build-up layer; lands that are disposed on an upper surface of the low elastic modulus layer and connected via solder bumps to a IC chip; and conductor posts that pass through the low elastic modulus layer and electrically connect lands with conductor patterns. The conductor posts have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 ?m, and the aspect ratio Rasp of external conductor posts, which are positioned at external portions of the low elastic modulus layer, is greater than or equal to the aspect ratio Rasp of internal conductor posts, which are positioned at internal portions of the low elastic modulus layer.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: May 1, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Toshiki Furutani
  • Patent number: 8164005
    Abstract: A multilayer high-frequency circuit board includes a signal line, ground layers, and an interlayer circuit. A signal line where a high-frequency signal flows is formed in the signal line layer. The ground layers are laminated on both sides of the signal line layer, each of which is grounded. The interlayer circuit is provided in the signal line layer and includes a ground connecting portion connected to the ground layers and a signal line connecting portion connected to the signal line. One of the signal line connecting portion and the ground connecting portion surrounds an outer periphery of the other of the signal line connecting portion and the ground connecting portion concentrically with the one being separated from the outer periphery of the other along the signal line layer. An inner periphery of the one and the outer periphery of the other have a similar shape excluding a complete circle.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: April 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuusuke Yamashita, Ryota Suzuki, Masahiro Tanabe, Taihei Nakada, Tsuyoshi Kumamoto
  • Patent number: 8164006
    Abstract: According to an embodiment of the present invention, an electromagnetic bandgap structure can include: at least three conductive plates; a first stitching via, configured to electrically connect any one of the conductive plates to another conductive plate; and a second stitching via, configured to electrically connect the one conductive plate to yet another conductive plate. In the electromagnetic bandgap structure of the present invention, the first stitching via can electrically connect the one conductive plate to another conductive plate by allowing a part of the first stitching via to be connected through a planar surface above the one conductive plate, and the second stitching via can electrically connect the one conductive plate to yet another conductive plate by allowing a part of the second stitching via to be connected through a planar surface below the one conductive plate.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: April 24, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Mi-Ja Han, Hyo-Jic Jung
  • Patent number: 8163397
    Abstract: A method and apparatus suitable for forming hermetic electrical feedthroughs in a ceramic sheet having a thickness of .ltoreq.40 mils. More particularly, the method yields an apparatus including a hermetic electrical feedthrough which is both biocompatible and electrochemically stable and suitable for implantation in a patient's body. The method involves: (a) providing an unfired, ceramic sheet having a thickness of .ltoreq.40 mils and preferably comprising .ltoreq.99% aluminum oxide; (b) forming multiple blind holes in said sheet; (c) inserting solid wires, preferably of platinum, in said holes; (d) firing the assembly of sheet and wires to a temperature sufficient to sinter the sheet material but insufficient to melt the wires; and (e) removing sufficient material from the sheet lower surface so that the lower ends of said wires are flush with the finished sheet lower surface.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: April 24, 2012
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Jerry Ok, Robert J. Greenberg
  • Patent number: 8158891
    Abstract: A circuit board disclosed in the present invention includes a core board on which a first circuit layer is placed, wherein the first circuit layer has a plurality of conductive pads; and at least one built-up structure covering the surface of the circuit board, which comprises a dielectric layer, a second circuit layer, and a plurality of conductive vias without being surrounded by annular metal rings. The conductive vias are conducted with the conductive pads of the first circuit layer and the second circuit layer. Besides, the surface of the second circuit layer is in the same height as the surface of the dielectric layer. Also, the present invention provides a method for manufacturing the above-mentioned circuit board structure. Therefore, a circuit board having fine circuits can be formed, and the shape of the circuit can be ensured efficiently. Moreover, electric performances of the circuit board can be improved.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: April 17, 2012
    Assignee: Unimicron Technology Corp.
    Inventor: Chao-Wen Shih
  • Publication number: 20120085574
    Abstract: Provided are a heat radiating substrate and a method of manufacturing the same. The heat radiating substrate includes a substrate having a via-hole, an anode oxide layer formed on the entire surface of the substrate having the via-hole through an anodizing process, a first circuit pattern formed on the substrate on which the anode oxide layer is formed, and a second circuit pattern formed at a lower part of the via-hole to be connected to the via-hole. Therefore, it is possible to simplify a circuit forming process and readily manufacture the heat radiating substrate by applying a metal anodic bonding process, without using a conventional adhesion layer and metal seed when the heat radiating substrate is manufactured.
    Type: Application
    Filed: March 21, 2011
    Publication date: April 12, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ji Hyun Park, Tae Hoon Kim, Sang Hyun Shin, Ki Ho Seo, Cheol Ho Heo, Young Ki Lee
  • Patent number: 8138424
    Abstract: A wiring substrate includes (i) a wiring forming region in which wiring layers and an insulating layer are alternately stacked, (ii) an outer periphery region around the wiring forming region, and (iii) a reinforcing structural body having (a) a first reinforcing member continuously extending along said outer periphery region, and (b) a second reinforcing member extending in a thickness direction and being engaged with the first reinforcing member.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: March 20, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Hiroshi Shimizu
  • Patent number: 8134078
    Abstract: A plurality of first output terminals is provided along one side of a circuit element, and a plurality of input terminals and a plurality of second output terminals are provided adjacently along the other opposite side thereof. Leads include a first output lead extending from the first output terminal to an output connection electrode, and a second output lead extending from the second output terminal to the output connection electrode. The second output lead is extended from the other side of the circuit element to one side of the circuit element through a surface of a flexible wiring cable opposite the circuit element and further extended in parallel with the first output lead and connected to the output connection electrode.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: March 13, 2012
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Tomoyuki Kubo
  • Publication number: 20120055708
    Abstract: An electronic component package includes a first sealing member and a second sealing member. The first sealing member has one principal surface on which an electronic component element is to be mounted. The second sealing member is opposite the first sealing member. The second sealing member hermetically encloses an electrode of the electronic component element. A through hole passes through between one principal surface and another principal surface of a substrate constituting the first sealing member. A conducting material fills the through hole. A resin material seals an open end portion of the through hole at a side of the other principal surface of the substrate.
    Type: Application
    Filed: August 30, 2011
    Publication date: March 8, 2012
    Applicant: DAISHINKU CORPORATION
    Inventor: Naoki KOHDA
  • Patent number: 8129626
    Abstract: A multilayer wiring substrate having no core substrate is provided. The multilayer wiring substrate includes: a laminated body includes: a plurality of insulating layers; and a plurality of wiring layers. The laminated body has: a mounting surface on which a semiconductor element is mounted; and a bonding surface to which external connection terminals are bonded. At least one of the insulating layers contains a glass cloth.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: March 6, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Natsuko Ueda, Yuji Yukiiri
  • Publication number: 20120048602
    Abstract: There is provided a method of manufacturing a ceramic substrate for a probe card and a ceramic substrate for a probe card. The method includes preparing a ceramic substrate having a via electrode provided therein; filling a void formed between the ceramic substrate and the via electrode with a filling material including thermosetting resin; and curing the filling material. Since the void formed between the ceramic substrate and the via electrode is removed, fixation strength between the via electrode and a probe tip can be increased and a defect such as a hollow at the periphery of the via electrode can be prevented.
    Type: Application
    Filed: March 18, 2011
    Publication date: March 1, 2012
    Inventors: Taek Jung LEE, Byeung Gyu CHANG, Yun Hwi PARK
  • Patent number: 8124885
    Abstract: An anisotropically conductive connector and an anisotropically conductive connector device. The anisotropically conductive connector includes a supporting member, a plurality of through-holes each extending in a thickness-wise direction of the supporting member, and anisotropically conductive sheets respectively held in the through-holes of the supporting member. Each anisotropically conductive sheet includes a frame plate, a plurality of through-holes each extending in a thickness-wise direction of the frame plate, and a plurality of anisotropically conductive elements arranged in the respective through-holes of the frame plate. Each of the anisotropically conductive elements includes a conductive part, conductive particles contained in an elastic polymeric substance in a state oriented so as to align in a thickness-wise direction of the element, and an insulating part to cover the outer periphery of the conductive part and including an elastic polymeric substance.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 28, 2012
    Assignee: JSR Corporation
    Inventors: Daisuke Yamada, Kiyoshi Kimura
  • Patent number: RE43509
    Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: July 17, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Yasuji Hiramatsu, Yoshinori Wakihara, Kazuhito Yamada