Electrical Contact Material Patents (Class 204/192.17)
-
Patent number: 6755945Abstract: An iPVD apparatus (20) is programmed to deposit material (10) into high aspect ratio submicron features (11) on semiconductor substrates (21) by cycling between deposition and etch modes within a vacuum chamber (30). The modes operate at different power and pressure parameters. Pressure of more than 50 mTorr, for example, is used for sputtering material from a target while pressure of less than a few mTorr, for example, is used to etch. Bias power on the substrate is an order of magnitude higher for etching, producing several hundred volt bias for etching, but only a few tens of volts for deposition. The alternating etching modes remove deposited material that overhangs edges of features on the substrate, removes some of the deposited material from the bottoms (15) of the features, and resputters the removed deposited material onto sidewalls (16) of the features. The substrate (21) is cooled during deposition and etching, and particularly during etching to substantially below 0° C.Type: GrantFiled: May 3, 2002Date of Patent: June 29, 2004Assignee: Tokyo Electron LimitedInventors: Tugrul Yasar, Glyn Reynolds, Frank Cerio, Bruce Gittleman, Michael Grapperhaus, Rodney Robison
-
Publication number: 20040119131Abstract: The invention described herein relates to physical vapor deposition targets comprising both Ti and Zr. The targets can comprise a uniform texture across the target surface and throughout the thickness; and can further have an increased mechanical strength compared to high purity titanium and tantalum. The sputtering targets can be utilized to sputter deposit a thin film; and such film can be utilized as a copper barrier layer.Type: ApplicationFiled: November 12, 2002Publication date: June 24, 2004Inventor: Stephen P. Turner
-
Patent number: 6752912Abstract: In a sputtering apparatus, target particles to be deposited onto a substrate are selectively ionized relative to other particles in the deposition chamber. For example, titanium or titanium-containing target particles are selectively ionized, while inert particles, such as argon atoms, remain substantially unaffected. Advantageously, one or more optical ionizers, such as lasers, are used to create one or more ionization zones within the deposition chamber in which such selective ionization takes place.Type: GrantFiled: August 27, 1999Date of Patent: June 22, 2004Assignee: Micron Technology, Inc.Inventor: Gurtej S. Sandhu
-
Patent number: 6746823Abstract: A process of fabricating a non-gap 3-D microstructure array mold core comprises a first step in which a buffer layer is coated on a substrate. A photomask layer is then coated of the buffer layer. A pattern is subsequently formed on the photomask by photo-lithography. The patterned photomask layer is subjected to a reflow by which a microstructure array is formed on the photomask layer. The microstructure array is coated with a metal conductive layer. The microgaps of the microstructure array are eliminated by an electrocasting layer which is coated on the microstructure array. The non-gap microstructure array mold core so fabricated is made into a metal molding tool by microinjection molding or microthermo-pressure molding.Type: GrantFiled: June 1, 2002Date of Patent: June 8, 2004Assignee: Industrial Technology Research InstituteInventors: Kun-Lung Lin, Min-Chieh Chou, Cheng-Tang Pan
-
Patent number: 6726812Abstract: An ion beam sputtering apparatus comprising: a first means for generating an ion beam and directing said ion beam in a prescribed direction, a second means for supporting a target at a position where said target is capable of exposing said ion beam irradiated in said prescribed direction and of being sputtered by said ion beam, a third means for supporting an electrically conductive substrate having a semiconductor layer on which a component sputtered from said target is to be deposited, and a fourth means for making said electrically conductive substrate have a non-earth potential. A method for forming a transparent and electrically conductive film on an electrically conductive substrate having a semiconductor layer, which is based on said ion beam sputtering apparatus. A process for producing a semiconductor device by forming a transparent and electrically conductive film on a semiconductor layer for said semiconductor device, which is based on said ion beam sputtering apparatus.Type: GrantFiled: March 4, 1998Date of Patent: April 27, 2004Assignee: Canon Kabushiki KaishaInventor: Noboru Toyama
-
Patent number: 6716736Abstract: In a method for manufacturing an under-bump metallurgy (UBM) layer, a plate having a plurality of openings is prepared. Then, the plate is placed on the wafer. Finally, the material of the under-bump metallurgy layer is sputtered on the wafer using the plate as a sputter mask so as to quickly form the under-bump metallurgy layer.Type: GrantFiled: January 14, 2002Date of Patent: April 6, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Shih-Kuang Chen, Chih-Hsiang Hsu
-
Patent number: 6716363Abstract: A process for fabricating piezoelectric elements each having a wrap-around electrode to be used in a differential actuator design where electrical connection is made to the bottom electrode of the element from the top surface of the element. The wrap-around electrode is formed during the creation of the elements instead of on an element by element basis.Type: GrantFiled: January 14, 2002Date of Patent: April 6, 2004Assignee: Seagate Technology LLCInventors: John Stuart Wright, Zine-Eddine Boutaghou
-
Patent number: 6717178Abstract: A thin film transistor includes an active silicon layer deposited by physical vapor deposition (PVD), wherein a silicon precursor is doped with impurities prior to use as a target in the PVD chamber, wherein the precursor has a resistivity in the range of about 0.5 &OHgr;-cm<&rgr;s<60 &OHgr;-cm; and wherein the target includes plural, rectangular tiles wherein all individual tiles are larger than 8.5 inches square.Type: GrantFiled: August 13, 2002Date of Patent: April 6, 2004Assignee: Sharp Laboratories of America, Inc.Inventors: Yukihiko Nakata, Apostolos Voutsas, John Hartzell
-
Publication number: 20040060812Abstract: A method of controlling intrinsic stress in metal films deposited on a substrate using physical vapor deposition (PVD) techniques is disclosed. The film stress is controlled, by applying a bias power to the substrate during the deposition process. The magnitude of the bias power applied to the substrate modulates the film stress such that as-deposited material layers have an intrinsic stress that may be either tensile or compressive. Also, a reflected bias power may be applied to the substrate during the deposition process, in addition to the bias power. The magnitude of the reflected bias power in combination with the bias power also modulates the film stress such that as-deposited material layers have an intrinsic stress that may be either tensile or compressive.Type: ApplicationFiled: September 27, 2002Publication date: April 1, 2004Applicant: Applied Materials, Inc.Inventors: Jr-Jyan Chen, Harald Herchen, Kenny King-Tai Ngan
-
Publication number: 20040061116Abstract: A cube used to perform optical functions in a system, such as beam splitting or polarizing, or both, is manufactured by optically contacting a coated prism with an uncoated prism. The coated prism includes a dielectric stack having alternating layers of high and low index of refraction materials. To ensure secure optical contacting between the coated prism and uncoated prism, low interface reflection, and good throughput, a contacting layer is deposited on the dielectric stack. The contacting layer can be fused silica or SiO2, which has natural compatibility with the CaF2 materials that make up the uncoated prism and the coating layers.Type: ApplicationFiled: October 1, 2002Publication date: April 1, 2004Applicant: ASML US, Inc.Inventors: Samad M. Edlou, David H. Peterson
-
Publication number: 20040055872Abstract: A stamper forming method, including the following steps: coating a first photoresist on a substrate, coating a stop layer on the first photoresist, coating a second photoresist on the stop layer, exposing the second photoresist by using a beam of light, exposing the first photoresist by using another beam of light, developing the first photoresist and the second photoresist, and sputtering a metal layer over the second photoresist. The invention also discloses another stamper forming method.Type: ApplicationFiled: November 8, 2002Publication date: March 25, 2004Inventors: Kuo-Hsin Teng, Hao-Chia Liao
-
Publication number: 20040050687Abstract: The present invention provides a bias sputtering film forming process and film forming apparatus that can form a coating film having a good film thickness distribution in a minute coated surface of a complicated shape, such as contact holes, through-holes and wiring grooves, especially for the sidewall portions thereof.Type: ApplicationFiled: September 10, 2003Publication date: March 18, 2004Applicant: ULVAC, INC.Inventors: Myounggoo Lee, Yoshihiro Okamura, Kazuyuki Tomizawa, Satoru Toyoda, Narishi Gonohe
-
Publication number: 20040048468Abstract: A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.Type: ApplicationFiled: September 10, 2002Publication date: March 11, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Wuping Liu, Beichao Zhang, Liang Choo Hsia
-
Magnetically confined metal plasma sputter source with magnetic control of ion and neutral densities
Publication number: 20040045811Abstract: A metal vapor deposition reactor includes a primary reactor chamber having a primary chamber enclosure comprising a ceiling and side wall. A wafer support pedestal within the primary chamber has a planar processing surface for supporting a planar semiconductor wafer. The reactor further includes a secondary reactor chamber having a secondary chamber enclosure and a metal source target within the secondary chamber formed of a metal species to be deposited on said semiconductor wafer. Process gas inlets furnish process gases into a region of the secondary chamber near a working surface of said metal source target. A D.C. power source connected across said metal source target and a conductive portion of said secondary chamber enclosure has sufficient power to support ionization of the process gas near the working surface of the metal source target whereby to form a plasma that sputters metal ions and neutrals from the working surface of the metal source target.Type: ApplicationFiled: September 10, 2002Publication date: March 11, 2004Applicant: Applied Materials, Inc.Inventors: Wei D. Wang, Praburam Gopalraja, Jianming Fu -
Publication number: 20040043334Abstract: In the present invention, the problem of stability deterioration of the obtained conductive pattern substrate at the time of forming a conductive pattern by an additive method when a layer having reactivity remains on the substrate is to be solved. According to pattern exposure with a photo catalyst substrate 4 having a photo catalyst layer 3 laminated on a second substrate 5 superimposed onto a wettability changeable substrate 1 with a wettability changeable layer 3 laminated on a first substrate 2, a wettability pattern is formed. And furthermore, by adhering a conductive coating solution, or the like, a conductive pattern substrate without containing a photo catalyst can be manufactured.Type: ApplicationFiled: April 17, 2003Publication date: March 4, 2004Inventors: Hironori Kobayashi, Yudai Yamashita
-
Patent number: 6699372Abstract: The present invention provides a method of depositing a film on a surface of a coil that includes depositing a metal from a target onto a surface of a coil to form a first film on the surface and forming a second film over the first film at a low pressure and at a first power at the target that is substantially higher than a first power at the component's surface. The conditioned deposition tool is well suited for manufacturing integrated circuits.Type: GrantFiled: April 16, 2001Date of Patent: March 2, 2004Assignee: Agere Systems Guardian CorporationInventors: Siddhartha Bhowmik, Sailesh M. Merchant, Frank Minardi
-
Publication number: 20040035693Abstract: A method for removing voids in a ceramic substrate includes steps of preparing a ceramic substrate and defining holes of different dimensions in the ceramic substrate, sputtering a titanium/copper film onto opposite sides of the ceramic substrate, chemical copper plating, forming a dry film onto the ceramic substrate, forming an image, plating copper leads, plating nickel and gold, removing the dry film, and etching titanium/copper.Type: ApplicationFiled: August 26, 2002Publication date: February 26, 2004Inventor: Shao-Pin Ru
-
Publication number: 20040035692Abstract: An array of auxiliary magnets is disclosed that is positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.Type: ApplicationFiled: August 22, 2003Publication date: February 26, 2004Inventors: Peijun Ding, Rong Tao, Zheng Xu
-
Publication number: 20040031677Abstract: A system for performing PVD of metallic nitride(s) is disclosed. The improved performance is provided by a method of increasing the partial pressures of nitrogen or other active gases near the wafer surface through initial introduction of the argon or other neutral gases alone into an ionized metal plasma PVD chamber through an upper gas inlet at or near the target, initiating the plasma in the presence of argon or other neutral gases alone, after which nitrogen or other active gases are introduced into the chamber through a lower gas inlet at or near the wafer surface to increase deposition rates and lower electrical resistivity of the deposited metallic layer. An apparatus for carrying out the invention includes a source of argon near the target surface and a source of nitrogen integral to the substrate support thereby delivering nitrogen near the substrate surface.Type: ApplicationFiled: August 22, 2003Publication date: February 19, 2004Applicant: Applied Materials, Inc.Inventors: Wei Wang, James Van Gogh
-
Publication number: 20040023057Abstract: A method of forming a patterned thin film comprises the step of forming a frame having an undercut near the bottom thereof on an electrode film, and the plating step of forming the patterned thin film by plating through the use of the frame. The patterned thin film includes a plurality of linear portions disposed side by side. Each of the linear portions has a portion close to the electrode film. This portion has a width greater than the width of the remaining portion of each of the linear portions.Type: ApplicationFiled: July 11, 2003Publication date: February 5, 2004Applicant: TDK CORPORATIONInventor: Akifumi Kamijima
-
Publication number: 20040017419Abstract: A method of manufacturing a microelectronics device is provided, wherein the microelectronics device is formed on a substrate having a frontside and a backside. The method comprises forming a circuit element on the frontside of the substrate from a plurality of layers deposited on the frontside of the substrate, wherein the plurality of layers includes an intermediate electrical contact layer, and forming an interconnect structure after forming the electrical contact layer. The interconnect structure includes a contact pad formed on the backside of the substrate, and a through-substrate interconnect in electrical communication with the contact pad, wherein the through-substrate interconnect extends from the backside of the substrate to the electrical contact layer.Type: ApplicationFiled: July 29, 2002Publication date: January 29, 2004Inventors: Diane Lai, Samson Berhane, Barry C. Snyder, Ronald A. Hellekson, Hubert Vander Plas
-
Patent number: 6679977Abstract: A method for producing flat panels for TFT or plasma display applications includes forming a sputter source within a sputter coating chamber, the source having at least two electrically mutually isolated stationery bar-shaped target arrangements. A controlled magnet arrangement provided under each target with a time-varying magnetron field.Type: GrantFiled: September 6, 2002Date of Patent: January 20, 2004Assignee: Unakis Trading AGInventors: Walter Haag, Pius Grunenfelder, Urs Schwendener, Markus Schlegel, Siegfried Krassnitzer
-
Patent number: 6676812Abstract: An alignment mark shielding ring for use in a physical vapor deposition chamber and a method for using the ring to avoid arcing problems on the wafer. The alignment mark shielding ring can be constructed of a ring that has a generally L-shaped cross-section, at least one hood portion to function as the shield for the alignment mark, at least one alignment pin for engaging at least one alignment sleeve mounted in a lower chamber shield for holding the alignment mark shielding ring in place. The alignment sleeve is constructed in two halves, each having an aperture therethrough. The aperture in the top half is larger than the aperture in the bottom half such that even when the apertures are coated with a metal layer deposited in the PVD process, the alignment pin does not electrically short to the lower chamber shield and thus, any possibility of arcing is avoided.Type: GrantFiled: May 9, 2002Date of Patent: January 13, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chen-Fang Chung
-
Patent number: 6673130Abstract: Fuel cell stacks contain an electrolyte layer surrounded on top and bottom by an electrode layer. Porous electrodes are prepared which enable fuel and oxidant to easily flow to the respective electrode-electrolyte interface without the need for high temperatures or pressures to assist the flow. Rigid, inert microspheres in combination with thin-film metal deposition techniques are used to fabricate porous anodes, cathodes, and electrolytes. Microshperes contained in a liquid are randomly dispersed onto a host structure and dried such that the microsperes remain in position. A thin-film deposition technique is subsequently employed to deposit a metal layer onto the microsperes. After such metal layer deposition, the microspheres are removed leaving voids, i.e. pores, in the metal layer, thus forming a porous electrode. Successive repetitions of the fabrication process result in the formation of a continuous fuel cell stack. Such stacks may produce power outputs ranging from about 0.1 Watt to about 50 Watts.Type: GrantFiled: June 15, 2001Date of Patent: January 6, 2004Assignee: The Regents of the University of CaliforniaInventors: Alan F. Jankowski, Jeffrey D. Morse
-
Patent number: 6662429Abstract: In a device for measuring the filling level, thermoelements (20) are used which are disposed on a sheet-shaped support (25). The thermoelements (20) consist of two different materials and are disposed in two rows (71, 72) placed side by side. Two adjacent thermoelements (20) of said rows (71, 72) have a common junction point (23) that is heated. Both rows (71, 72) of thermoelements also have two additional junction points that are cold. A first group of thermoelements (20) is disposed with their supports (25) in the interior of the container and operate as measuring detectors. A second group of thermoelements (20) serves as reference sensors since they regulate the heat flow impinging upon the junctions points (23) relative to a defined reference voltage.Type: GrantFiled: June 22, 2001Date of Patent: December 16, 2003Assignee: Kromberg & SchubertInventor: Gottfried Domorazek
-
Publication number: 20030227068Abstract: The invention describes herein relates to new titanium-comprising materials which can be utilized for forming titanium alloy sputtering targets. The titanium alloy sputtering targets can be reactively sputtered in a nitrogen-comprising sputtering atmosphere to form an alloy TiN film, or alternatively in a nitrogen-comprising and oxygen-comprising sputtering atmosphere to form an alloy TiON thin film. The thin films formed in accordance with the present invention can have a non-columnar grain structure, low electrical resistivity, high chemical stability, and barrier layer properties comparable to those of TaN for thin film Cu barrier applications. Further, the titanium alloy sputtering target materials produced in accordance with the present invention are more cost-effective for semiconductor applications than are high-purity tantalum materials and have superior mechanical strength suitable for high-power sputtering applications.Type: ApplicationFiled: November 26, 2002Publication date: December 11, 2003Inventors: Jianxing Li, Stephen Turner, Lijun Yao
-
Patent number: 6660136Abstract: The invention includes methods of forming a non-volatile resistance variable device and methods of forming a metal layer comprising silver and tungsten. A method of forming a non-volatile resistance variable device includes forming a chalcogenide material over a semiconductor substrate. First and second electrodes are formed operably proximate the chalcogenide material. At least one of the first and second electrodes includes a metal layer having silver and tungsten. The metal layer is formed by providing the substrate within a sputter deposition chamber. One or more target(s) is/are provided within the chamber which include(s) at least tungsten and silver. The one or more target(s) is/are sputtered using a sputtering gas comprising at least one of Xe, Kr and Rn under conditions effective to deposit the metal layer onto the substrate. The metal layer can be fabricated independent of fabrication of a non-volatile resistance variable device.Type: GrantFiled: March 27, 2002Date of Patent: December 9, 2003Assignee: Micron Technology, Inc.Inventors: Jiutao Li, Shane P. Leiphart
-
Publication number: 20030219622Abstract: Electrical connectors incorporate a composite coating of molybdenum disulfide and a metal, preferably tin, for one or both of the contact surfaces of the electrical connector. The coating provides for a low coefficient of friction, low contact resistance, and good electrical conductivity, as well as good mechanical properties. The coating also reduces the insertion force of the electrical connectors, thereby increasing the number of possible terminal pairs and/or reducing terminal bending and breakage for a manually mated connector. The coating can be deposited on copper, tin-plated copper, tin alloy-plated copper or other metallic substrates, using any of several physical vapor deposition methods.Type: ApplicationFiled: April 22, 2003Publication date: November 27, 2003Inventor: Daniel A. Niebauer
-
Publication number: 20030217915Abstract: A cavity forming formed in an encapsulation structure under a vacuum in a vacuum chamber is sealed with a capping layer. A stiff protective layer under tensile stress is deposited on the capping layer prior to venting the vacuum chamber to atmospheric pressure. The capping layer is preferably aluminum or an aluminum alloy, and the protective layer is preferably &dgr;-TiN having a suitable high Young's modulus.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventors: Luc Ouellet, Robert Antaki, Yves Tremblay
-
Publication number: 20030216035Abstract: A physical vapor deposition chamber is employed to sputter-deposit a layer of material, such as a tantalum or tantalum nitride barrier layer, in a via formed on a semiconductor substrate. After the sputter-deposition step, a second processing step is performed in which material from the barrier layer is back-sputtered from the bottom wall of the via. The second step is performed at a high pedestal bias and with substantial power applied to the sputtering target. The power applied to the sputtering target in the second step may be at a higher level than the power applied to the sputtering target in the first step. Numerous other aspects are provided.Type: ApplicationFiled: May 14, 2003Publication date: November 20, 2003Applicant: Applied Materials, Inc.Inventors: Suraj Rengarajan, Michael Miller, Darryl Angelo, Nirmalya Maity, Peijun Ding
-
Patent number: 6649031Abstract: A corrosion resistant coated fuel cell plate and method of making the same are embodied in a metal plate provided with a multilayered conductive coating and then with an overcoating which fills in fine scale porosities in the coating. In one preferred embodiment, the overcoating is amorphous graphite applied through a deposition process. In another preferred embodiment, the overcoating is a thin layer of oxide created by a chemical anodization process.Type: GrantFiled: October 8, 1999Date of Patent: November 18, 2003Assignee: Hybrid Power Generation Systems, LLCInventors: Zafar Iqbal, Dave Narasimhan, James V. Guiheen, Timothy Rehg
-
Publication number: 20030209422Abstract: A method and apparatus for depositing a film on a substrate comprising a deposition interval wherein DC power is applied to a target to form a first plasma and material is sputtered from the target onto a substrate and, during a subsequent forming interval, high frequency power is applied to the target to remove material from at least a portion of the substrate. The sputtering working gas admitted to the chamber may be maintained at a first pressure during the deposition interval and the pressure of the sputtering working gas may be increased to a second pressure during the forming interval.Type: ApplicationFiled: May 9, 2002Publication date: November 13, 2003Applicant: Applied Materials, Inc.Inventors: Wei Wang, Praburam Gopalraja, Jianming Fu
-
Publication number: 20030188964Abstract: The sputtering target comprises a backing plate 10, a copper target 12 provided on the backing plate 10, and a protection layer 14 formed on the surface of the copper target 12 and having corrosion-resistant metal. Accordingly, the oxidation of the copper target 12 can be suppressed. Thus, the formation of a contaminant layer on the shielding plate of the sputtering system can be suppressed, and resultantly the adhesion of particles to a substrate due to the release of a deposited layer on the surface of the shielding plate can be suppressed.Type: ApplicationFiled: February 24, 2003Publication date: October 9, 2003Applicant: Fujitsu LimitedInventor: Takashi Hasegawa
-
Publication number: 20030188886Abstract: A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.Type: ApplicationFiled: April 9, 2002Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Edmond Otto Fey, Raymond Thomas Galasco, Thomas Richard Miller, Anita Sargent
-
Publication number: 20030183510Abstract: A conductive composition of titanium boronitride (TiBxNy) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the titanium boronitride is used to construct contact pads such as inline pads, backend pads, sensors or probes. Advantages of embodiments of the titanium boronitride include reduced scratching, increased hardness, finer granularity, thermal stability, good adhesion, and low bulk resistivity. Exemplary methods of creating the titanium boronitride include a sputtering process and a plasma anneal process.Type: ApplicationFiled: May 2, 2003Publication date: October 2, 2003Inventor: Yungjun Jeff Hu
-
Publication number: 20030183509Abstract: Uniformity of a sputtered conductive barrier layer (50) or seed layer (52) across a semiconductor substrate (18, 42) is improved by incorporating a plurality of electromagnets (26) in or around the sputtering chamber (14) which can be independently powered. In other words, each individual electromagnet can be turned on or off, and/or the amount of power being supplied to each electromagnet (and thus the magnetic field generated by each electromagnet) can be varied independently. Further, the sputtering system (10) includes connection to a computer (30) that is either integral to or connected to a metrology tool (28). The metrology tool measures uniformity of a layer deposited by the sputtering system, analyzes the measurements and feeds back information to the sputtering system as to how to vary the power being supplied to the plurality of electromagnets to improve layer uniformity.Type: ApplicationFiled: March 28, 2002Publication date: October 2, 2003Inventor: Walter Gregor Braeckelmann
-
Publication number: 20030183507Abstract: The invention includes methods of forming a non-volatile resistance variable device and methods of forming a metal layer comprising silver and tungsten. A method of forming a non-volatile resistance variable device includes forming a chalcogenide material over a semiconductor substrate. First and second electrodes are formed operably proximate the chalcogenide material. At least one of the first and second electrodes includes a metal layer having silver and tungsten. The metal layer is formed by providing the substrate within a sputter deposition chamber. One or more target(s) is/are provided within the chamber which include(s) at least tungsten and silver. The one or more target(s) is/are sputtered using a sputtering gas comprising at least one of Xe, Kr and Rn under conditions effective to deposit the metal layer onto the substrate. The metal layer can be fabricated independent of fabrication of a non-volatile resistance variable device.Type: ApplicationFiled: March 27, 2002Publication date: October 2, 2003Applicant: Micron Technology, Inc.Inventors: Jiutao Li, Shane P. Leiphart
-
Patent number: 6624073Abstract: A new method of forming a tantalum carbide nitride diffusion barrier layer having optimized nitrogen concentration for improved thermal stability is described. A contact region is provided in a substrate. A via is opened through an insulating layer to the contact region. A tantalum carbide nitride barrier layer is deposited within the via wherein the tantalum carbide nitride layer has an optimized nitrogen content of between about 17% and 24% by atomic percentage. A layer of copper is deposited overlying the tantalum carbide nitride barrier layer to complete copper metallization in the fabrication of an integrated circuit device.Type: GrantFiled: December 3, 2001Date of Patent: September 23, 2003Assignees: ProMos Technologies, Inc., Mosel Vitelic Inc., Intineon Technologies, Inc.Inventors: Shi-Chung Sun, Hao-Yi Tsai
-
Publication number: 20030173106Abstract: A simplified manufacturing process for fabricating transparent conductive panels with a low contact surface impedance employs a yellow light and etching technique to form a wiring structure on a single layer transparent conductive film that requires high transparency, and form a wiring structure on a double layer metal film and transparent conductive film for a connecting area to externally connect to a driver circuit. The invention can achieve a higher reliability and lower cost in the processes of fabricating high resolution products.Type: ApplicationFiled: March 13, 2003Publication date: September 18, 2003Inventor: Chin-Pei Hwang
-
Patent number: 6620301Abstract: Uniformity of a sputtered conductive barrier layer (50) or seed layer (52) across a semiconductor substrate (18, 42) is improved by incorporating a plurality of electromagnets (26) in or around the sputtering chamber (14) which can be independently powered. In other words, each individual electromagnet can be turned on or off, and/or the amount of power being supplied to each electromagnet (and thus the magnetic field generated by each electromagnet) can be varied independently. Further, the sputtering system (10) includes connection to a computer (30) that is either integral to or connected to a metrology tool (28). The metrology tool measures uniformity of a layer deposited by the sputtering system, analyzes the measurements and feeds back information to the sputtering system as to how to vary the power being supplied to the plurality of electromagnets to improve layer uniformity.Type: GrantFiled: March 28, 2002Date of Patent: September 16, 2003Assignee: Motorola, Inc.Inventor: Walter Gregor Braeckelmann
-
Patent number: 6610597Abstract: A semiconductor manufacturing process is disclosed that may form a contact structure with a tungsten plug. A contact structure hole may be adequately filled with tungsten, while avoiding plug loss, increased resistance and/or trenching, that can result from conventional approaches. According to one particular embodiment, a titanium film (003) may be deposited with an anisotropic sputtering method, such as an ion metal plasma method, or the like. A titanium film (003) may have a thickness outside a contact hole (020) that is 100 nm or more. However, due to anisotropic sputtering, a titanium film (003) within a contact hole (020) may be thinner than outside the contact hole (020). A contact hole (020) may then be filled with a tungsten film (005). A tungsten film (005) and titanium film (003) may then be etched back leaving a tungsten plug having shape with an upwardly projecting portion.Type: GrantFiled: January 29, 2002Date of Patent: August 26, 2003Assignees: NEC Corporation, NEC Electronics CorporationInventor: Migaku Kobayashi
-
Publication number: 20030157799Abstract: A method of filling trenches or vias on a semiconductor workpiece surface with copper using sputtering techniques. A copper wetting layer and a copper fill layer may both be applied by sputtering techniques. The thin wetting layer of copper is applied at a substrate surface temperature ranging between about 20° C. to about 250° C., and subsequently the temperature of the substrate is increased, with the application of the sputtered copper fill layer beginning at above at least about 200° C. and continuing while the substrate temperature is increased to a temperature as high as about 600° C. Preferably the substrate temperature during application of the sputtered fill layer ranges between about 300° C. and about 500° C.Type: ApplicationFiled: February 20, 2003Publication date: August 21, 2003Inventors: Peijun Ding, Tony Chiang, Barry L. Chin
-
Patent number: 6607613Abstract: A metal alloy solder ball comprising a first metal and a second metal, the first metal having a sputtering yield greater than the second metal. The solder ball comprises a bulk portion having a bulk ratio of the first metal to the second metal, an outer surface, and a surface gradient having a depth and a gradient ratio of the first metal to the second metal that is less than the bulk ratio. The gradient ratio increases along the surface gradient depth from a minimum at the outer surface. The solder ball may be formed by the process of exposing the ball to energized ions of a sputtering gas for an effective amount of time to form the surface gradient.Type: GrantFiled: February 1, 2001Date of Patent: August 19, 2003Assignee: International Business Machines CorporationInventors: Frank D. Egitto, Edmond O. Fey, Luis J. Matienzo, David L. Questad, Rajinder S. Rai, Daniel C. Van Hart
-
Publication number: 20030150721Abstract: A source of sputtered deposition material has, in one embodiment, a torus-shaped plasma generation area in which a plasma operates to sputter the interior surface of a toroidal cathode. In one embodiment, the sputtered deposition material passes to the exterior of the source through apertures provided in the cathode itself. A torus-shaped magnetic field generated in the torus-shaped plasma facilitates plasma generation, sputtering of the cathode and ionization of the sputtered material by the plasma.Type: ApplicationFiled: February 11, 2002Publication date: August 14, 2003Applicant: Applied Materials, Inc.Inventor: Mark A. Perrin
-
Publication number: 20030153177Abstract: In one embodiment of the present inventions, an exhaust outlet in a vacuum processing chamber includes a nonsealing flow restrictor which can facilitate rapid opening and closing of the flow restrictor in some applications. Because the flow restrictor is a nonsealing flow restrictor, the conductance of the flow restrictor in the closed position may not be zero. However, the flow restrictor can restrict the flow of an exhaust gas from the chamber to permit the retention of sufficient processing gas in the chamber to deposit a film on the substrate or otherwise react with the substrate. After a film has been deposited, typically in a thin atomic layer, the exhaust flow restrictor may be opened such that the flow restrictor conductance is significantly increased to a second, higher flow rate to facilitate exhausting residue gas from the chamber. The nonsealing flow restrictor may be closed again to deposit a second layer, typically of a different material onto the substrate.Type: ApplicationFiled: February 11, 2002Publication date: August 14, 2003Applicant: Applied Materials, Inc.Inventors: Avi Tepman, Lawrence Chung-Iai Lei
-
Publication number: 20030150711Abstract: A coated article that can be used in applications such as insulating glass (IG) units, so that resulting IG units can achieve high visible transmission of at least 70% (e.g., when using clear glass substrates from 1.0 to 3.5 mm thick), combined with at least one of: (a) SHGC no greater than about 0.45, more preferably no greater than about 0.40; (b) SC no greater than about 0.49, more preferably no greater than about 0.46; (c) chemical and/or mechanical durability; (d) neutral transmissive color such that transmissive a* is from −5.0 to 0 (more preferably from −3.5 to −1.5), and transmissive b* is from −2.0 to 4.0 (more preferably from 1.0 to 3.0); and (e) neutral reflective color from the exterior of the IG unit (i.e., Rg/Rout) such that reflective a* is from −3.0 to 2.0 (more preferably from −2.0 to 0.5), and reflective b* is from −5.0 to 1.0 (more preferably from −4.0 to −1.0).Type: ApplicationFiled: October 17, 2001Publication date: August 14, 2003Inventor: Ronald E. Laird
-
Publication number: 20030138554Abstract: A method for manufacturing an electrode for a lithium secondary battery includes a step of forming an oxide film other than a natural oxide film on a current collector by oxidizing the surface of the current collector, and a step of forming an active material layer on the oxide film by a method to provide a material for the active material layer by emitting in the vapor phase, such as PVD (physical vapor deposition) including sputtering, vapor evaporation, and the like, and CVD (chemical vapor deposition) including plasma CVD.Type: ApplicationFiled: January 17, 2003Publication date: July 24, 2003Inventors: Hiromasa Yagi, Hisaki Tarui
-
Patent number: 6596133Abstract: An apparatus and method for the deposition of thin film material layers provides improved use of processing chamber space for enhanced processing capability in the fabrication of microelectronic devices. In one embodiment, a physical-vapor deposition target offset from the processing chamber central axis, such as a target having an annular shape and central opening, deposits a material on a substrate while leaving the central region of the processing chamber available for other deposition techniques, including a centrally located sputtering target, CVD showerhead, or ion source. Alternatively, a collimator divides a processing chamber into sub-chambers and allows energetic species from a PVD target or ion source to pass to a substrate located in a separate sub-chamber for interaction with a CVD precursor without mixing the precursor and the plasma associated with the PVD or ion processes.Type: GrantFiled: June 14, 2001Date of Patent: July 22, 2003Assignee: CVC Products, Inc.Inventors: Mehrdad M. Moslehi, Ajit P. Paranjpe
-
Patent number: 6596132Abstract: A method for producing thin film deposits of ternary shape-memory alloys using an ion sputtering deposition process comprising using a hot pressed metal powder composition target.Type: GrantFiled: September 22, 1999Date of Patent: July 22, 2003Assignee: Delphi Technologies, Inc.Inventors: Gregory Keller Rasmussen, Fenglian Chang, Jinping Zhang, Terry Jack Gold
-
Patent number: 6592724Abstract: Disclosed is a method for producing ternary shape-memory alloy films employing sputtering process techniques using krypton as a process gas.Type: GrantFiled: September 22, 1999Date of Patent: July 15, 2003Assignee: Delphi Technologies, Inc.Inventors: Gregory Keller Rasmussen, Fenglian Chang, Jinping Zhang, Terry Jack Gold