Electrical Contact Material Patents (Class 204/192.17)
  • Patent number: 6589398
    Abstract: The present invention pertains to methods for preventing metal or metal-derived material from flaking during sputter processing of substrates. Methods of the invention are particularly useful for non-planar sputter targets. The magnetic field configuration in a sputter apparatus is modulated during a pasting process. Flaking from regions of the target, shield, or other internal components of the sputter apparatus is inhibited by pasting methods which include encapsulation and optionally removal of material, for example by erosion via high density plasma.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: July 8, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Jean Qing Lu, Jeffrey Andrew Tobin, Linda Lee Stenzel, Lananh Pham
  • Publication number: 20030124846
    Abstract: A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling. The copper seed layer may be deposited by a combination of SIP and high-density plasma sputtering. For very narrow holes, the CVD copper layer may fill the hole.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 3, 2003
    Inventors: Tony P. Chiang, Yu D. Cong, Peijun Ding, Jianming Fu, Howard H. Tang, Anish Tolia
  • Publication number: 20030118798
    Abstract: A copper interconnection where holes in the vicinity of an interface are reduced to lower contribution of interface diffusion to Cu the EM, increase a lifetime, and simultaneously increase adhesiveness and resistance to stress migration is constituted in a manner that impurities 15 form a solid solution in the vicinity of an interface between a Cu layer 16 and a barrier metal layer 12, the impurities are precipitated, and an amorphous Cu layer 14 is fabricated, or a compound with Cu is fabricated. The copper interconnection is also constituted in a manner that impurities 15 form a solid solution in the vicinity of an interface between the Cu layer 16 and a cap layer 19, the impurities 15 are precipitated, and an amorphous Cu layer 14 is fabricated, or a compound with Cu is fabricated.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 26, 2003
    Applicant: NEC Electronics Corporation
    Inventor: Akiko Fujii
  • Publication number: 20030116427
    Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same chamber. Also, bottom coverage may be thinned or eliminated by ICP resputtering. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering.
    Type: Application
    Filed: July 25, 2002
    Publication date: June 26, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Peijun Ding, Zheng Xu, Roderick C. Mosely, Suraj Rengarajan, Nirmalya Maity, Daniel A. Carl, Barry Chin, Paul F. Smith, Darryl Angelo, Anish Tolia, Jianming Fu, Fusen Chen, Praburam Gopalraja, Xianmin Tang, John C. Forster
  • Patent number: 6582569
    Abstract: A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling. The copper seed layer may be deposited by a combination of SIP and high-density plasma sputtering. For very narrow holes, the CVD copper layer may fill the hole.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: June 24, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Tony P. Chiang, Yu D. Cong, Peijun Ding, Jianming Fu, Howard H. Tang, Anish Tolia
  • Patent number: 6562207
    Abstract: Sputter target, method of manufacture of same and sputter coating process using the target as a sputtering source are disclosed. The sputter target comprises an Me/Si multi-phase, consolidated blend wherein the Si component is present in a very small amount of about trace—0.99 mole Si:1 mole Me. Preferably, Me comprises one or more of Ta, Ti, Mo, or W. The targets are made from the requisite powders via HIP consolidation to provide densities of greater than 98 % of the theoretical density. The targets are especially useful in reactive cathodic sputtering systems employing N2 as the reactive gas to form amorphous Me/Si/N layers.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: May 13, 2003
    Assignee: Tosoh SMD, Inc.
    Inventor: Eugene Y. Ivanov
  • Patent number: 6562715
    Abstract: A barrier layer structure and a method of forming the structure. The barrier layer structure comprises a bilayer, with a first layer formed by chemical vapor deposition and a second layer formed by physical vapor deposition. The first barrier layer comprises a metal or a metal nitride and the second barrier layer comprises a metal or a metal nitride. The barrier bilayer is applicable to copper metallization.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: May 13, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Ling Chen, Christophe Marcadal
  • Patent number: 6551653
    Abstract: This invention relates to a process for metalizing polyolefin film in which at least one outermost layer of the unmetalized polyolefin film has at least about 90% cycloolefin polymer that has not been subjected to a process for increasing surface tension before metalization. The metalized films are useful as dielectrics in capacitors.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: April 22, 2003
    Assignee: Ticona GmbH
    Inventors: Wilfried Hatke, Karl-Heinz Kochem, Theo Grosse Kreul
  • Publication number: 20030062254
    Abstract: A method and an apparatus for depositing a metal layer on a substrate use a sputtering technique wherein first sputter particles sputtered from a first target including a metal are deposited on the substrate. A first metal layer portion having a first thickness corresponding to 40 to 60% of the whole deposition thickness is formed on the substrate. Second sputter particles sputtered from a second target including a metal identical to the first target are deposited on the first metal layer portion. Thus, a second metal layer portion including a material identical to the first metal layer portion and having a second thickness corresponding to 40 to 60% of the whole deposition thickness is formed on the first metal layer portion. When depositing the second metal layer portion, a radio frequency bias is applied to a bottom surface of the substrate so that the first and second sputter particles deposited on the substrate are resputtered towards the surface of the substrate.
    Type: Application
    Filed: September 18, 2002
    Publication date: April 3, 2003
    Inventors: Seung-Soo Choi, Seung-Cheol Choi
  • Publication number: 20030062255
    Abstract: A method for producing flat panels for TFT or plasma display applications includes forming a sputter source within a sputter coating chamber, the source having at least two electrically mutually isolated stationery bar-shaped target arrangements. A controlled magnet arrangement provided under each target with a time-varying magnetron field.
    Type: Application
    Filed: September 6, 2002
    Publication date: April 3, 2003
    Inventors: Walter Haag, Pius Grunenfelder, Urs Schwendener, Markus Schlegel, Siegfried Krassnitzer
  • Publication number: 20030044682
    Abstract: A n anode thin film for a lithium secondary battery having a current collector and an anode active material layer formed thereon, wherein the anode active material layer contains an intermetallic compound of tin (Sn) and nickel (Ni). In particular, the intermetallic compound is Ni3Sn4.
    Type: Application
    Filed: January 10, 2002
    Publication date: March 6, 2003
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Young-Sin Park, Joo-Yeal Oh, Sung-man Lee, Hong-Koo Baik
  • Publication number: 20030042133
    Abstract: A substrate is placed in a sputter chamber so as to be spaced from a target contained in the chamber. A gaseous impurity is provided into the sputter chamber so as to control a pressure within the chamber in a pressure transition range. A first pressure in the chamber when during an increase in pressure is different from a second pressure in the chamber during a decrease in pressure, while an equal amount of the nitrogen gas is provided into the sputter chamber. Accelerated particles collide with the target to sputter the metal material from the target. Accordingly, a metal barrier layer containing an impurity comprised of the gaseous impurity and the metal material is deposited on the substrate.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 6, 2003
    Inventors: Jae-Wook Lee, Yoon-Bon Koo
  • Publication number: 20030038025
    Abstract: Increased sidewall coverage by a sputtered material is achieved by generating an ionizing plasma in a relatively low pressure sputtering gas. By reducing the pressure of the sputtering gas, it is believed that the ionization rate of the deposition material passing through the plasma is correspondingly reduced which in turn is believed to increase the sidewall coverage by the underlayer. Although the ionization rate is decreased, sufficient bottom coverage of the by the material is maintained. In an alternative embodiment, increased sidewall coverage by the material may be achieved even in a high density plasma chamber by generating the high density plasma only during an initial portion of the material deposition. Once good bottom coverage has been achieved, the RF power to the coil generating the high density plasma may be turned off entirely and the remainder of the deposition conducted without the high density plasma.
    Type: Application
    Filed: October 2, 2002
    Publication date: February 27, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Ken Ngan, Simon Hui, Seshadri Ramaswami
  • Publication number: 20030024808
    Abstract: A method of sputtering a layer from a target having a plurality of recesses or openings includes using Krypton as a sputtering gas and is characterized in that the gas flow is less than 20 sccm and or the Krypton pressure is less than 1 militor.
    Type: Application
    Filed: August 21, 2002
    Publication date: February 6, 2003
    Inventors: Hilke Donohue, Mark Graeme Martin Harris
  • Patent number: 6508919
    Abstract: A method of forming diffusion barrier stacks on a dielectric for a dual damascene metal chip-level interconnect, and a diffusion barrier stack produced thereby. Alternating layers of a metal and an electrically resistive diffusion barrier are deposited on a dielectric substrate, with different layers having different thicknesses appropriate to their functions in the device. In an example of the present invention, alternating layers of tantalum and tantalum nitride are deposited on a dielectric substrate.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: January 21, 2003
    Assignee: Tokyo Electron Limited
    Inventors: Thomas J. Licata, Joseph T. Hillman
  • Publication number: 20030010624
    Abstract: A system and method are provided to sequentially deposit a silicon dioxide base coat barrier layer adjacent a thin silicon films, to minimize the formation of water and —OH radicals. Both the base coat and thin silicon films are sputter deposited to eliminate hydrogen chemistries. Further, the sputter processes are conducted sequentially, with breaking the vacuum seal, to minimize the absorption of water in the base coat layer that conventionally occurs between deposition steps. This process eliminates the total number of process steps required, as there is no longer a need for furnace annealing the base coat before the deposition of the thin silicon film, and no longer a need for a dehydrogenation annealing step after the deposition of the thin silicon film.
    Type: Application
    Filed: July 16, 2001
    Publication date: January 16, 2003
    Inventors: Apostolos Voutsas, Yukihiko Nakata
  • Patent number: 6500315
    Abstract: A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: December 31, 2002
    Assignee: Motorola, Inc.
    Inventors: Valli Arunachalam, Peter L. G. Ventzek, Dean J. Denning, John C. Arnold
  • Patent number: 6495001
    Abstract: A method for manufacturing a metal composite strip for the production of electrical contact components. A film made of tin or a tin alloy is first applied onto an initial material made of an electrically conductive base material. A film of silver is then deposited thereonto. Copper or a copper alloy is preferably used as the base material. The tin film can be applied in the molten state, and the silver film by electroplating. Furthermore, both the tin film and the silver film can be deposited by electroplating. A further alternative provides for manufacturing the tin film in the molten state and the silver film by cathodic sputtering. The diffusion operations which occur in the coating result in a homogeneous film of a tin-silver alloy. This formation can be assisted by way of a heat treatment of the composite strip.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: December 17, 2002
    Assignee: Stolberger Metallwerke GmbH and Co. KG
    Inventors: Udo Adler, Klaus Schleicher
  • Publication number: 20020185370
    Abstract: A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.
    Type: Application
    Filed: July 16, 2002
    Publication date: December 12, 2002
    Inventors: Praburam Gopalraja, Jianming Fu, Fusen Chen, Girish Dixit, Zheng Xu, Wei Wang, Ashok K. Sinha
  • Publication number: 20020182862
    Abstract: A new method of forming a tantalum carbide nitride diffusion barrier layer having optimized nitrogen concentration for improved thermal stability is described. A contact region is provided in a substrate. A via is opened through an insulating layer to the contact region. A tantalum carbide nitride barrier layer is deposited within the via wherein the tantalum carbide nitride layer has an optimized nitrogen content of between about 17% and 24% by atomic percentage. A layer of copper is deposited overlying the tantalum carbide nitride barrier layer to complete copper metallization in the fabrication of an integrated circuit device.
    Type: Application
    Filed: December 3, 2001
    Publication date: December 5, 2002
    Applicant: ProMOS Technologies, Inc.
    Inventors: Shi-Chung Sun, Hao-Yi Tsai
  • Publication number: 20020177006
    Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.
    Type: Application
    Filed: May 23, 2001
    Publication date: November 28, 2002
    Applicant: International Business Machines Corporation
    Inventors: Ronald Clothier, Jeffrey Alan Knight, Robert David Sebesta
  • Patent number: 6485617
    Abstract: A target and magnetron for a plasma sputter reactor and the associated sputtering method provided by the extended magnetic fields and plasma regions. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault, some of which may rotate along the vault, create a magnetic field in the vault to support a plasma extending over a large volume of the vault from its top to its bottom. The large plasma volume increases the probability that the sputtered metal atoms will become ionized and be accelerated towards an electrically biased wafer support electrode.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: November 26, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Jianming Fu, Praburam Gopalraja
  • Patent number: 6485618
    Abstract: A target and magnetron for a plasma sputter reactor. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process includes a first step of highly ionized sputter deposition of copper, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and electroplating copper into the hole to complete the metallization.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: November 26, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Praburam Gopalraja, Jianming Fu, Fusen Chen, Girish Dixit, Zheng Xu, Sankaram Athreya, Wei D. Wang, Ashok K. Sinha
  • Patent number: 6475356
    Abstract: Increased sidewall coverage by a sputtered material is achieved by generating an ionizing plasma in a relatively low pressure sputtering gas. By reducing the pressure of the sputtering gas, it is believed that the ionization rate of the deposition material passing through the plasma is correspondingly reduced which in turn is believed to increase the sidewall coverage by the underlayer. Although the ionization rate is decreased, sufficient bottom coverage of the by the material is maintained. In an alternative embodiment, increased sidewall coverage by the material may be achieved even in a high density plasma chamber by generating the high density plasma only during an initial portion of the material deposition. Once good bottom coverage has been achieved, the RF power to the coil generating the high density plasma may be turned off entirely and the remainder of the deposition conducted without the high density plasma.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: November 5, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Ken Ngan, Simon Hui, Seshadri Ramaswami
  • Publication number: 20020144891
    Abstract: Thickness uniformity of films sputtered from a target onto a series of substrates is maintained as the target surface shape changes due to the consumption of the target. The eroded condition of the target is sensed by directly measuring the position of a point on the target surface, by measuring power consumption of the target, by measuring deposition from the surface of the target or by some other means. A controller responds to the measurement by moving a substrate holder to determine an amount to change the distance between the substrate and the target, usually by moving the substrate closer to the target, by an amount necessary to maintain uniformity of the coatings on the wafers being processed. A servo or stepper motor responds to a signal from the controller to move the substrate holder in accordance with the determined amount of distance change required. The adjustment is made following the coating of wafers at various times over the life of the target.
    Type: Application
    Filed: May 24, 2002
    Publication date: October 10, 2002
    Applicant: Tokyo Electron Limited of TBS Broadcast Center
    Inventors: Steven Hurwitt, Israel Wagner
  • Patent number: 6461483
    Abstract: A method and apparatus that operates at a high pressure of at least one torr for improving sidewall coverage within trenches and vias in a substrate. The apparatus comprises a chamber enclosing a target and a pedestal, a process gas that provides a process gas in the chamber, a pump for maintaining the high pressure of at least about one torr in the chamber and a power source coupled to the target. Additionally, the distance between the target and the substrate is set to ensure that collisions between the sputtered particles and the plasma occur in the trenches and vias on the substrate. The method comprises the steps of providing a process gas into the chamber such that the gas pressure is at least about one torr, generating a plasma from the process gas, and sputtering material from the target.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: October 8, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Praburam Gopalraja, Bradley O. Stimson, John C. Forster, Wei Wang
  • Patent number: 6454914
    Abstract: An object of the present invention is to provide a ferroelectric capacitor which shows excellent ferroelectricity. A silicon oxidation layer 4, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 15 are formed on a silicon substrate 2. The lower electrode 12 is made of palladium oxide. Also, the upper electrode 15 is made by palladium oxide, since palladium oxide prevents leakage of oxygen contained in the ferroelectric layer 8. Thus, the ferroelectric capacitor of the present invention offers excellent ferroelectricity can be realized.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: September 24, 2002
    Assignee: Rohm Co., Ltd.
    Inventor: Takashi Nakamura
  • Patent number: 6451179
    Abstract: Increased sidewall coverage in a wetting layer for a substrate via or trench is achieved in an inductively coupled plasma chamber by sputtering relatively pure aluminum.
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: September 17, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Zheng Xu, Gongda Yao
  • Patent number: 6451181
    Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: September 17, 2002
    Assignee: Motorola, Inc.
    Inventors: Dean J. Denning, Sam S. Garcia, Bradley P. Smith, Daniel J. Loop, Gregory Norman Hamilton, Md. Rabiul Islam, Brian G. Anthony
  • Publication number: 20020125123
    Abstract: The resistivity of titanium nitride films is reduced, by about 40% (to less than about 60 &mgr;Ohm-cm), for example; and, the film surface roughness is reduced, by about 45% (to less than 6 Å) by using a combination of particular process conditions during deposition of the film. In particular, titanium atoms produced by impact of inert gas ions upon a titanium target travel through a high density, inductively coupled rf plasma, an ion metal plasma (IMP), in which the titanium atoms are at least partially ionized. The ionized titanium ions are contacted with ionized nitrogen atoms also present in the processing chamber. The resultant gas phase composition is contacted with the surface of a semiconductor substrate on which a titanium nitride barrier layer is to be deposited.
    Type: Application
    Filed: May 7, 2002
    Publication date: September 12, 2002
    Inventors: Kenny King-tai Ngan, Seshadri Ramaswami
  • Patent number: 6440831
    Abstract: A method for depositing an adhesion layer in a contact region on a semiconductor substrate provides for sufficient coverage on the bottom and sidewalls of the contact region. In an example embodiment, a contact region having a bottom and sidewalls has a first coat of the adhesion layer deposited thereon at a thickness greater than the thickness on the sidewall. To compensate for the narrower adhesion layer thickness on the sidewalls, a second coat of the adhesion layer is deposited so that the second coat on the sidewalls is at a thickness greater than the second coat thickness on the bottom. The adhesion layer is titanium nitride although other materials may be used as well.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: August 27, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jeffrey Klatt, Somchintana Norasetthekul
  • Publication number: 20020102347
    Abstract: A method for making a sensor is disclosed comprising using a sensing electrode having a first and second side. Using a reference electrode having a first and second side and a second electrical lead in electrical communication with the reference electrode. Disposing an electrolyte between the first side of sensing electrode and the first side of reference electrode. Disposing a first side of a protective layer adjacent to the side of sensing electrode. Mixing a metal oxide, a fugitive material, and a solvent to form a mixture. Applying the mixture to a second side of the protective layer and calcining the sensor to form the protective coating on the protective layer second side.
    Type: Application
    Filed: December 18, 2000
    Publication date: August 1, 2002
    Inventors: Eric P. Clyde, Richard F. Beckmeyer, William J. Labarge, Marsha E. Nottingham
  • Publication number: 20020096427
    Abstract: A PVD system comprises a hollow cathode magnetron with a capability of producing a high magnetic field for PVD and a low magnetic field for pasting. The high magnetic field is used for PVD and causes an optimal uniform film to form on a substrate but redeposits some metals onto a top portion of a target within the magnetron. The low magnetic field erodes redeposited materials from a top portion of a target within the magnetron.
    Type: Application
    Filed: January 23, 2001
    Publication date: July 25, 2002
    Inventors: Jean Qing Lu, Tom Yu, Jeffrey Tobin
  • Publication number: 20020092763
    Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.
    Type: Application
    Filed: February 22, 2002
    Publication date: July 18, 2002
    Inventors: Dean J. Denning, Sam S. Garcia, Bradley P. Smith, Daniel J. Loop, Gregory Norman Hamilton, Md. Rabiul Islam, Brian G. Anthony
  • Patent number: 6420263
    Abstract: A method of forming a semiconductor device having aluminum lines therein, wherein the occurrence of lateral extrusions and voids are reduced. The method comprises the formation of a metal stack on a surface of the substrate, wherein the aluminum layer of the metal stack is deposited under controlled conditions; etching the metal lines in the metal stack; and exposing the substrate to a subsequent anneal.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: July 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Roger W. Cheek, George A. Dunbar, III, Robert M. Geffken, William J. Murphy, Prabhat Tiwari, David H. Yao
  • Publication number: 20020089027
    Abstract: The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact.
    Type: Application
    Filed: March 6, 2002
    Publication date: July 11, 2002
    Inventors: Zheng Xu, John Forster, Tse-Yong Yao
  • Publication number: 20020088716
    Abstract: The present invention provides a method and apparatus for forming a copper layer on a substrate, preferably using a sputtering process. The sputtering process involves bombarding a conductive member of enhanced hardness with ions to dislodge the copper from the conductive member. The hardness of the target may be enhanced by alloying the copper conductive member with another material and/or mechanically working the material of the conductive member during its manufacturing process in order to improve conductive member and film qualities. The copper may be alloyed with magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof.
    Type: Application
    Filed: March 6, 2002
    Publication date: July 11, 2002
    Inventors: Vikram Pavate, Murali Abburi, Murali Narasimhan, Seshadri Ramaswami
  • Publication number: 20020070375
    Abstract: The present disclosure pertains to our discovery that the residual stress residing in a tantalum (Ta) film or a tantalum nitride (TaNx, where 0<x≦1.5) film can be controlled (tuned) by controlling particular process variables during deposition of the film. Process variables of particular interest during film deposition, for sputter applied Ta and TaNx films, include the following. The power to the sputtering target; the process chamber pressure (i.e. the concentration of various gases and ions present in the chamber); the substrate DC offset bias voltage (typically an increase in the AC applied substrate bias power); and, the temperature of the substrate upon which the film is being deposited. When the Ta or TaNx film is deposited using IMP sputtering, the power to the ionization coil can be used for stress tuning of the film. Of these variables, the process chamber pressure and the substrate offset bias most significantly affect the tensile and compressive stress components, respectively.
    Type: Application
    Filed: January 29, 2002
    Publication date: June 13, 2002
    Inventors: Tony Chiang, Peijun Ding, Barry L. Chin
  • Patent number: 6402907
    Abstract: This invention relates to method of forming a barrier layer in a high aspect ratio recess in a dielectric layer on a semi-conductor wafer.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: June 11, 2002
    Assignee: Trikon Holdings Limited
    Inventor: Paul Rich
  • Patent number: 6398923
    Abstract: An improved sputtering process increases the perpendicularity of the sputtered flux to the target surface by bombarding the target with both low and high mass ions, with low mass ions predominating, packing the target with both low and high mass implanted ions, and causing target atoms ejected as a result of high mass incident ions to have a higher probability of perpendicular or near perpendicular ejection. An alternative improved sputtering process bombards the target with both low and high mass ions, with high mass ions predominating, resulting in a higher sputter rate than achievable with either the high or low mass species alone. Including in either process as the high or the low mass species a species having a lower ionization energy than a standard species allows a reduced pressure plasma, resulting in less scattering of the sputtered flux. A low ionization energy species may also be employed to assist in striking a plasma before sputtering by a single species during deposition.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: June 4, 2002
    Assignee: Micron Technology, Inc.
    Inventors: P. J. Ireland, Howard Rhodes, Sujit Sharan, Sukesh Sandhu, Tim O'Brien, Tim Johnson
  • Publication number: 20020064952
    Abstract: The present invention is a semiconductor metallization process for providing complete via fill on a substrate and a planar metal surface, wherein the vias are free of voids and the metal surface is free of grooves. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A PVD metal layer, such as PVD Al or PVD Cu, is then deposited onto the refractory layer at a pressure below about 1 milliTorr to provide a conformal PVD metal layer. Then the vias or contacts are filled with metal, such as by reflowing additional metal deposited by physical vapor deposition on the conformal PVD metal layer. The process is preferably carried out in an integrated processing system that includes a long throw PVD chamber, wherein a target and a substrate are separated by a long throw distance of at least 100 mm, and a hot metal PVD chamber that also serves as a reflow chamber.
    Type: Application
    Filed: December 21, 2001
    Publication date: May 30, 2002
    Inventors: Sang-Ho Yu, Yonghwa Chris Cha, Murali Abburi, Shri Singhvi, Fufa Chen
  • Patent number: 6395148
    Abstract: The invention relates to a method for producing improved tantalum conductive and resistive materials for use in ink jet heater chips. Specifically, a method for producing thin film tantalum layers of a desired phase on a semiconductor substrate comprises depositing protective layers upon the semiconductor substrate; pre-sputter etching the semiconductor substrate; preheating the semiconductor substrate; maintaining the substrate at a predetermined temperature while depositing the thin film tantalum layer by sputtering for a predetermined period of time at a predetermined input power. Use of the method enables production of a desired tantalum phase for use on a semiconductor substrate thereby providing enhanced corrosion and/or cavitation resistance depending on the use of the semiconductor device.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: May 28, 2002
    Assignee: Lexmark International, Inc.
    Inventor: Charles Spencer Whitman
  • Patent number: 6387536
    Abstract: The present invention provides an Al alloy thin film for a semiconductor device electrode having an electrical resistivity of as low as 6 &mgr;&OHgr;cm or less, high hillock resistance, high void resistance, and high corrosion resistance against an alkaline solution, which are required for an electrode thin film of large-screen liquid crystal display (LCD) or high-resolution LCD. The present invention also provides a sputtering target to deposit the Al alloy film by sputtering process for a semiconductor device electrode. The Al alloy thin film for a semiconductor device electrode satisfies the conditions of Y≧0.3 at %, IVa group metal element≧0.2 at %, and 0.3Cy+3CIVa≦2 (wherein Cy: Y content (at %), CIVa: content of IVa group metal element (at %)), and the sputtering target is made of an Al alloy satisfying the above conditions.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: May 14, 2002
    Assignee: Kabushiki Kaisha Kobe Seiko Sho.
    Inventors: Katsutoshi Takagi, Takashi Onishi
  • Patent number: 6372114
    Abstract: A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the metal of the metal seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventor: Nobukazu Ito
  • Patent number: 6365510
    Abstract: A contact layer is used, for example, as a liner for the fabrication of electrical contacts in contact holes. The contact layer is fabricated in two steps, in a first step a first contact layer is deposited, in which only a small proportion of the particles to be sputtered is ionized. In a second sputtering step, a second contact layer is sputtered, in the course of whose fabrication a larger proportion of the particles to be sputtered is ionized. The procedure ensures that the first contact layer is disposed as a protective layer on the substrate by gentle sputtering before the second contact layer is sputtered.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: April 2, 2002
    Assignee: Infineon Technologies AG
    Inventors: Sven Schmidbauer, Norbert Urbansky
  • Patent number: 6361704
    Abstract: A new method is provided to create aluminum pads that overlay an electrical contact point. A thick layer of passivation is deposited over the surface that contains one or more electrical contact points, the layer of passivation is patterned thereby creating openings in the layer of passivation that overlay and align with one or more of the contact points. A layer of aluminum is sputter deposited over the passivation layer including the openings that has been created in the passivation layer, this layer of aluminum is sputtered to a thickness such that the surface of the aluminum that is created in the openings in the layer of passivation is lower than the surface of the layer of passivation. The deposited layer of aluminum is polished using methods of CMP whereby the polishing end point is the surface of the layer of passivation.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: March 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tsu Shih, Chen-Hua Yu
  • Publication number: 20020017453
    Abstract: A first Ti film is formed by sputtering with the space between a semiconductor substrate and a target provided at a greater distance such as 350 mm, subsequently, a second Ti film is formed again by sputtering with a shorter distance such as 80 mm, thereon a first TiN film is formed by sputtering with a greater distance such as 350 mm, and, subsequently, a second TiN film is formed again by sputtering with a shorter distance such as 80 mm. Then, these first and second Ti films and first and second TiN films are combined to provide a barrier layer.
    Type: Application
    Filed: March 21, 2001
    Publication date: February 14, 2002
    Inventor: Souichirou Iguchi
  • Publication number: 20020014406
    Abstract: The first Al-based target material for sputtering contains 0.01-10 atomic % of at least one intermetallic compound-forming element, and an intermetallic compound having a maximum diameter of substantially 50 &mgr;m or less. The second Al-based target material for sputtering has a microstructure comprising an alloy phase containing 20 atomic % or less of the intermetallic compound-forming element and Al and an Al matrix phase comprising substantially pure Al, the maximum diameter of the intermetallic compound in the alloy phase being substantially 50 &mgr;m or less. The content of the intermetallic compound forming element based on the whole structure is 0.01-10 atomic %. These target materials are produced by pressure-sintering a rapid solidification powder at 400-600° C. After the pressure sintering, the target material is preferably hot-rolled at 400-600° C.
    Type: Application
    Filed: May 21, 1998
    Publication date: February 7, 2002
    Inventor: HIROSHI TAKASHIMA
  • Patent number: 6342133
    Abstract: Ti and TiN layers are formed on an integrated circuit substrate using a titanium target in non-nitrided mode in a hollow cathode magnetron apparatus. Neither a collimator nor a shield is used. Ti and TiN layers are deposited in vias and trenches having aspect ratios up to 5:1.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: January 29, 2002
  • Publication number: 20020008017
    Abstract: A magnetron especially advantageous for low-pressure plasma sputtering or sustained self-sputtering having reduced area but full target coverage. The magnetron includes an outer pole face surrounding an inner pole face with a gap therebetween. The outer pole of the magnetron of the invention is smaller than that of a circular magnetron similarly extending from the center to the periphery of the target and has a substantially larger total magnetic intensity. Thereby, sputtering at low pressure and high ionization fraction is enabled.
    Type: Application
    Filed: July 30, 2001
    Publication date: January 24, 2002
    Inventor: Jianming Fu