Abstract: Disclosed herein is a method for manufacturing a printed circuit board, wherein a protective film for stripping and a metal layer closely adhered to the protective film for stripping are formed on an inner layer pad to protect the inner layer pad at the time of laser processing related to cavity processing and applying an etchant, thereby making it possible to improve reliability of a product.

Abstract: Disclosed is a resin wiring sheet wherein generation of wrinkles due to heat treatment can be suppressed. The wiring sheet (1) has wiring (3) formed thereon by laminating a metal foil on the surface of a resin base material (2) and patterning the metal foil into a desired wiring shape. The resin base material (2) is a biaxially stretched sheet, which is stretched in the TD direction and the MD direction of the biaxially extending apparatus. In the wiring (3) formed on the wiring sheet (1), with respect to the components in the two directions that orthogonally intersect each other, the total length of the wiring (3) components in one direction is longer than the total length of the wiring (3) components in the other direction, thus the wiring has anisotropy, and said direction of the components accords with the MD direction of the stretched resin base material (2).

Abstract: A method for manufacturing a printed wiring board includes forming a resin layer on an interlayer layer such that the resin layer has first openings exposing circuits in central portion and second openings exposing circuits in peripheral portion of the interlayer layer, forming solder bumps on the circuits in the first openings, forming a plating resist over the bumps and resin layer such that the resist has openings having diameters greater than the second openings and exposing the second openings, forming a seed layer on the resist, in the openings and on the circuits through the second openings, applying electrolytic plating on the resist such that electrolytic plating fills the openings and forms a plated film on the resist and metal posts in the openings, etching the plating such that the plated film is removed and recesses are formed on end surfaces of the posts, and removing the resist.

Abstract: A magnetic write head having a write pole with a tapered trailing edge portion and having a spin torque oscillator that is formed entirely on the tapered trailing edge portion and that is self aligned with first and second sides of the write pole. The write pole and spin torque oscillator are formed by a method wherein the sides of the spin torque oscillator and write pole are defined in the same photolithographic and ion milling process, thereby allowing for the self alignment of the spin torque oscillator with the sides of the write pole.

Abstract: This invention provides a method for mass production of silicon nanowires and/or nanobelts. The invented method is a chemical etching process employing an etchant that preferentially etches and removes other phases from a multiphase silicon alloy, over a silicon phase, and allows harvesting of the residual silicon nanowires and/or nanobelts. The silicon alloy comprises, or is treated so as to comprise, one-dimensional and/or two-dimensional silicon nanostructures in the microstructure of the multi-phase silicon alloy prior to etching. When used as anode for secondary lithium batteries, the silicon nanowires or nanobelts produced by the invented method exhibit high storage capacity.

Abstract: Described herein are coating compositions for protecting one-glass solution (OGS) glasses and other display glasses during processing. The coatings are non-reactive to typical indium-tin oxide touch components, metal electrodes, and black matrix inks, and can thus be used to over-coat these materials. In one aspect, the coating compositions described herein can be applied by a screen printing application process in a single layer or in multiple layers and are compatible with CNC edge grinding and acid etching. Further, the protective coatings are rigid, but not brittle, and are durable but still able to be processed rapidly. Additionally, the protective coatings are transparent, allowing alignment marks on the substrates to be visible. Finally, the protective coatings can easily be removed after substrate processing has been completed.

Abstract: Novel anisotropic magneto-resistive (AMR) sensor architectures and techniques for fabricating same are described. In at least one embodiment, an AMR sensor is provided that includes barber pole structures having upper and low metal layers that are formed of different materials. The metal material closer to the AMR element is formed of a material that can be etched using an etching process that does not attack the AMR material. In some other embodiments, AMR sensors having segmented AMR sensing elements are described.

Abstract: A method is provided for fabricating a substrate having multiple metal layers separated by one or more dielectric layers, respectively. The method includes forming a cavity in at least one dielectric layer through an exposed portion of a top dielectric layer of the substrate, applying metal to side and bottom surfaces of the cavity, forming a pattern through a portion of the metal applied to the bottom surface of the cavity, and micro-etching the metal applied to the bottom surface of the cavity. The micro-etching extends the pattern through a remaining portion of the metal applied to the bottom surface of the cavity.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.

Abstract: A method for manufacturing a printed wiring board includes forming a resin insulation layer on an interlayer resin insulation layer and conductive circuits such that the resin insulation layer has first openings exposing pad portions in central portion of the interlayer layer and second openings exposing pad portions in peripheral portion of the interlayer layer, forming a seed layer on the resin insulation layer, in the first and second openings and on the pad portions, forming on the seed layer a plating resist such that the resist has resist openings exposing the second openings and having diameters greater than the second openings, filling the resist openings with electrolytic plating material via the seed layer such that metal posts are formed in the resist openings, removing the resist from the resin insulation layer, and removing the seed layer exposed on the resin insulation layer by the removing of the resist.

Abstract: There is provided a coil sheet including: a base sheet, and a coil unit disposed on the base sheet and including a central conductive part and a surface conductive part formed on surfaces of the central conductive part, wherein when a thickness of the surface conductive part formed on lateral surfaces of the central conductive part is ‘a’ and a thickness of the surface conductive part formed on an upper surface of the central conductive part is ‘b’, a<b may be satisfied.

Abstract: A semiconductor device according to the present invention includes a ceramic substrate, a plurality of circuit patterns arranged on a surface of the ceramic substrate, a semiconductor element arranged on an upper surface of at least one circuit pattern, and a sealing resin for sealing the ceramic substrate, the plurality of circuit patterns, and the semiconductor element, in which an undercut part is formed in opposed side surfaces of the circuit patterns adjacent to one another, the undercut part is configured such that an end of an upper surface of the circuit pattern protrudes outside the circuit pattern more than an end of a lower surface of the circuit pattern on the ceramic substrate, and the undercut part is also filled with the sealing resin.

Abstract: A method of etching a material layer on a substrate is described. In one embodiment, the method includes modifying an etch resistance of a material layer to a pre-determined etch process by doping the material layer using energetic charged particles, and etching the modified material layer using the pre-determined etch process.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: To provide a photocured product having small mold releasing force. A photocured product obtained by curing with light and containing a surface active agent, wherein a peak area of the ether bond derived peak is 3.0 times or more as large as a peak area of the ester bond derived peak, wherein the peak areas are obtained by peak separation processing by curve fitting of an X-ray photoelectron spectroscopy spectrum obtained as an analytical result on a chemical state of carbon at topmost surface of the photocured product, the analytical result being among analytical results on the topmost surface of the photocured product obtained by surface analysis of the photocured product with angle resolved X-ray photoelectron spectroscopy.

Abstract: Provided are a conductive structure including a) a base, b) a conductive pattern provided on at least one side of the base, and c) a darkening layer provided on the upper surface and lower surface of the conductive pattern, provided on at least a part of the side of the conductive pattern, and provided in an area corresponding to the conductive pattern area, and a touch panel including the same and a manufacturing method thereof.

Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.

Abstract: A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented.

Abstract: A method comprising: providing a transparent electrically conductive film comprising: a transparent substrate (14); a composite layer (18) comprising: an electrically conductive layer disposed on at least a portion of a major surface of the transparent substrate (14) and comprising a plurality of interconnecting metallic nanowires (12); and a polymeric overcoat layer disposed on a portion of the electrically conductive layer, to provide a coated area of the electrically conductive layer; and patternwise exposing the coated area of the electrically conductive layer to a corona discharge to provide a patternwise exposed electrically conductive film comprising (1) an un exposed region (122) of the coated region having a first electrical resistivity, and (2) an exposed region (121) having a second electrical resistivity; wherein the exposed region is less electrically conductive than the unexposed region, and wherein there is a ratio of the second electrical resistivity over the first electrical resistivity of at

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board includes: a base substrate; an inner layer build-up layer formed on the base substrate and including a first inner layer circuit layer, a second inner layer circuit layer, an inner layer insulating layer, and an inner layer via having a tapered section; and an outer layer build-up layer formed on the inner layer build-up layer and including an outer layer circuit layer, an outer layer insulating layer, and an outer layer via having a rectangular section.

Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.

Abstract: The invention relates to a submillimeter-sized hot-wire sensor (1) comprising a substrate (10), two support rods (11, 12), a metal wire (13) extending between the two ends of the support rods (11, 12), and electrical contacts (14, 15) disposed on the support rods, said contacts each being linked to one of the ends of the wire (13). The metal wire comprises at least two layers of metal materials, one of said layers being made of a material exhibiting a residual stress under tension and the other layer being made of a material exhibiting a residual stress under compression. The thicknesses of these metal layers are adapted so as to compensate the residual stresses between the various layers.

Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.

Abstract: Provided are a porous silicon-based particle including a silicon (Si) or SiOx (0<x<2) particle, wherein the particle includes a plurality of nonlinear pores, and the nonlinear pores are formed as open pores in a surface of the particle, and a method of preparing the porous silicon-based particles. Porous silicon-based particles according to an embodiment of the present invention may be more easily dispersed in an anode active material slurry, may minimize side reactions with an electrolyte, and may reduce volume expansion during charge and discharge. Also, according to an embodiment of the present invention, the shape, form, and size of pores formed in the porous silicon-based particle may be controlled by adjusting the type of a metal catalyst, the concentration of the catalyst, and etching time.

Abstract: A polyimide film for production of a wiring board having a metal wiring, which is formed by forming a metal layer on one side (Side B) of the polyimide film, and etching the metal layer; the polyimide film is curled toward the side (Side A) opposite Side B; and the curling of the polyimide film is controlled so as to reduce the drooping of the wiring board having a metal wiring formed thereon. The handling characteristics and productivity in IC chip mounting may be improved by the use of the polyimide film.

Abstract: A method of manufacturing a print element substrate, comprising preparing a substrate, including a first region and a second region, in which a printing portion is formed on the first region, and a wiring pattern connected to the printing portion is formed on the first region and the second region, forming an insulating film covering the printing portion and the wiring pattern, and forming a conductive cavitation-resistant film on the insulating film, wherein in the forming the insulating film, the insulating film is formed such that a side surface of a portion of the insulating film, which is formed on the second region, includes an inclined face.

Abstract: A method comprising etching a film comprising electrically conductive structures according to a pattern using an aqueous etching solution to provide an etched region having a first conductivity and an unetched region having a second conductivity, the second conductivity being greater than the first conductivity, wherein the aqueous etching solution either comprises 25 to 65% by weight of phosphoric acid and 1 to 18% by weight of nitric acid, or the aqueous etching solution comprises 65 to 75% by weight of nitric acid.

Abstract: According to one embodiment, there is provided a pattern formation method including forming a target layer to be processed on a substrate, adding a second dispersion containing a polymer material including a polymer chain having a base metal at a terminal end and a second solvent to a first dispersion containing noble-metal microparticles and a first solvent, thereby preparing a noble-metal microparticle layer coating solution in which microparticles covered with the polymer material are dispersed, arranging the noble-metal microparticles covered with the polymer material on the target layer by using the noble-metal microparticle layer coating solution, and transferring a projections pattern of the noble-metal microparticles covered with the polymer material to the target layer.

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate, a first stamp, and a different multi-level second stamp. A curable bottom layer is provided over the substrate. One or more bottom-layer micro-channels) are imprinted in the curable bottom layer with the first stamp and a bottom-layer micro-wire formed in each bottom-layer micro-channel. A curable multi-layer is formed adjacent to and in contact with the cured bottom layer. First and second multi-layer micro-channels and a top-layer micro-channel are imprinted in the curable multi-layer with the multi-level second stamp. Either two bottom-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a top-layer micro-wire or two top-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a bottom-layer micro-wire.

Abstract: Provided is a translucent conductive patterned member in which, as the metal pattern portion itself has a translucency, the metal pattern portion is hardly visible, and scattering caused by a moiré or diffraction is reduced, and in which it is also provided with sufficient conductivity. The translucent conductive patterned member is provided with a base layer formed by using a compound containing a nitrogen atom and a conductive pattern portion having a translucency in which the conductive pattern portion is formed on at least one part of the base layer by using silver or an alloy containing silver as a main component.

Abstract: An etching process includes: forming a metal film on a substrate having a pattern formation region; forming a mask having a predetermined pattern on the metal film in the pattern formation region, and forming a resist film in part or all of a periphery of the pattern formation region; and dry-etching the metal film in the pattern formation region.

Abstract: A method for forming a rough silicon wafer including the successive steps of: performing a plasma etching of a surface of the wafer in conditions suitable to obtain a rough structure, and performing two successive ion milling steps, one at an incidence in the range of 0 to 10°, the other at an incidence in the range of 40 to 60° relative to the normal to the wafer.

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing a first stamp and a multi-level second stamp. A curable bottom layer and multi-layer are provided on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer. A multi-layer micro-channel and a top-layer micro-channel are imprinted in the multi-layer. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire extends from the central area into the edge area. The multi-layer micro-wire contacts the bottom-layer micro-wire in the edge area. The top-layer micro-wire is over the central area and is separate from the multi-layer micro-wire and the bottom-layer micro-channel. The bottom-layer micro-wire is electrically connected to the multi-layer micro-wire and is electrically isolated from the top-layer micro-wire.

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connecting-layer micro-channel is imprinted in the connecting layer in the edge area over the bottom-layer micro-channel, an edge micro-channel is imprinted in the top layer in the edge area over the connecting-layer micro-channel, and top-layer micro-channels are imprinted in the top layer over the central area. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.

Abstract: A method of forming an electrode is disclosed. A carbon nanotube is deposited on a substrate. A section of the carbon nanotube is removed to form at least one exposed end defining a first gap. A metal is deposited at the at least one exposed end to form the electrode that defines a second gap.

Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

Abstract: An approach for making thin flexible circuits. A layer of dielectric may have one or two surfaces coated with metal. The dielectric and the metal may each have a sub-mil thickness. The dielectric may be held in a fixture for fabrication like that of integrated circuits. The metal may be patterned and have components attached. More layers of dielectric and patterned metal may be added to the flexible circuit. Also bond pads and connecting vias may be fabricated in the flexible circuit. The flexible circuit may be cut into a plurality of smaller flexible circuits.

Abstract: A method of forming a silicon anode material for rechargeable cells includes providing a metal matrix that includes no more than 30 wt % of silicon, including silicon structures dispersed therein. The metal matrix is at least partially etched to at least partially isolate the silicon structures.

Abstract: A method of etching silicon of a material comprising silicon, the method comprising the steps of partially covering a silicon surface of the material comprising silicon with an elemental metal and then carrying out a metal-assisted chemical etching of the silicon by exposing the partially covered silicon surface to an etching composition, wherein at least some of the elemental metal for the metal-assisted chemical etching is formed by either: (a) exposing the silicon surface to a composition comprising metal ions, wherein the elemental metal forms by reduction of the metal ions and wherein the composition comprising metal ions is substantially free of HF, or (b) depositing the elemental metal directly onto the silicon surface.

Abstract: Provided is a copper foil for a printed wiring board including a roughened layer on at least one surface thereof. In the roughened layer, the average diameter D1 at the particle bottom being apart from the bottom of each particle by 10% of the particle length is 0.2 to 1.0 ?m, and the ratio L1/D1 of the particle length L1 to the average diameter D1 at the particle bottom is 15 or less. In the copper foil for printed wiring board, when a copper foil for printed wiring having a roughened layer is laminated to a resin and then the copper layer is removed by etching, the sum of areas of holes accounting for the resin roughened surface having unevenness is 20% or more. The present invention involves the development of a copper foil for a semiconductor package substrate that can avoid circuit erosion without causing deterioration in other properties of the copper foil.

Abstract: A pressure sensor includes a top cap with a recess formed in an end of the top cap and a cavity formed in the end of the top cap to communicate with the recess. The cavity extends further axially into the top cap than the recess thereby having depth greater than a depth of the recess. Outer edges of the recess extend laterally outward beyond outer edges of the cavity thereby defining a bonding boundary. A silicon substrate has a sensing circuit on a top side thereof. The top cap is bonded to the top side of the silicon substrate in a range from the outer edges of the top cap to the bonding boundary. The recess and the cavity of the top cap face the top side of the silicon substrate and form a reference vacuum cavity. When pressure is exerted on a backside of the substrate, a portion of the substrate is constructed and arranged to deflect.

Abstract: A method of forming a microwave applicator comprising forming a body comprising dielectric material so that there is a void in the dielectric material, and depositing conductive material in the void to form a feed for coupling energy into the dielectric material.

Abstract: A process for the preparation of a printed wiring board that can prevent generation of crack and warpage is provided. A process for the preparation of a printed wiring board, comprising a step of forming a curable resin layer and a non-curable resin layer sequentially on a surface of a substrate; a step of forming depressions in the non-curable resin layer and the curable resin layer from the non-curable resin layer side; a step of applying a catalyst for plating to a surface of the non-curable resin layer and surfaces of the depressions; a step of removing the non-curable resin layer and the catalyst for plating provided on the surface of the non-curable resin layer; and a step of electroless plating the surfaces of the depressions.

Abstract: A method of forming at least one curved plate having first and second layers, the first layer being formed of a first material and the second layer being formed of a second material, the method including forming one or more blocks of a fusible material on a surface of a substrate; baking the one or more blocks to deform their shape; and depositing the first and second materials over the one or more deformed blocks to form the first and second layers.

Abstract: A substrate for an electrowetting display device including a pixel electrode, a partition wall pattern and a water-repellent pattern. The pixel electrode is formed on a base substrate. The partition wall pattern is disposed along an edge of the pixel electrode to expose the pixel electrode. The water-repellent pattern is disposed at a space formed by the pixel electrode and the partition wall pattern to be extended along a lower portion of side surfaces of the partition wall pattern from an area on which the pixel electrode is formed. The water-repellent pattern exposes an upper portion of the side surfaces and an upper surface of the partition wall pattern. Thus, a manufacturing reliability of a substrate for an electrowetting display device is improved to prevent a display quality from being reduced.

Abstract: Provided is a resin composition which enables the formation of a roughened surface having a low roughness degree on the surface of an insulation layer in a printed wiring board material when used on the insulation layer regardless of the roughening conditions employed and also enables the formation of a conductive layer having excellent adhesion properties, heat resistance, heat resistance under absorption of moisture, thermal expansion properties and chemical resistance on the roughened surface. A resin composition comprising (A) an inorganic filler that is soluble in an acid, (B) a cyanic acid ester compound and (C) an epoxy resin.

Abstract: The invention relates to an article, such as a plate for a use in a fuel cell, which has a base onto which a coating is applied which is electrically conductive and which includes a substantially carbon material layer and at least one intermediate layer which can be a nitride, carbide, metal and metal alloy. The multilayer coating which is formed allows the protection of the article in an efficient and effective manner.

Abstract: Disclosed is a fuel cell with enhanced mass transfer characteristics in which a highly hydrophobic porous medium, which is prepared by forming a micro-nano dual structure in which nanometer-scale protrusions with a high aspect ratio are formed on the surface of a porous medium with a micrometer-scale roughness by plasma etching and then by depositing a hydrophobic thin film thereon, is used as a gas diffusion layer, thereby increasing hydrophobicity due to the micro-nano dual structure and the hydrophobic thin film. When this highly hydrophobic porous medium is used as a gas diffusion layer for a fuel cell, it is possible to reduce water flooding by efficiently discharging water produced by an electrochemical reaction of the fuel cell and to improve the performance of the fuel cell by facilitating the supply of reactant gases such as hydrogen and air (oxygen) to a membrane-electrode assembly (MEA).

Abstract: A process is provided for etching a silicon-containing substrate. In the process, the surface of the substrate is cleaned. A film of alumina is deposited on the cleaned substrate surface. A silver film is deposited above the film of alumina. An etchant comprising HF is contacted with the silver film.

Abstract: Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.