Abstract: A through wiring substrate includes a substrate having a first face and a second face; and a through-wire formed by filling, or forming a film of, an electrically-conductive substance into a through-hole, which penetrates between the first face and the second face. The through-hole has a bend part comprising an inner peripheral part that is curved in a recessed shape and an outer peripheral part that is curved in a protruding shape, in a longitudinal cross-section of the through-hole, and at least the inner peripheral part is formed in a circular arc shape in the longitudinal cross-section.

Abstract: In a current collector laminating step, a current-collector laminate unit 30 composed of current-collector materials 31 and 32 and a film material 33 is formed. Resist layers 34 having a predetermined pattern are formed on both surfaces of the current-collector laminate unit 30. An etching process is performed with the resist layers 34 used as a mask, whereby through-holes 20a and 23a are formed on the respective current-collector materials 31 and 32. The resist layers 34 are removed from the current-collector laminate unit 30. Since the etching process is performed on the plural current-collector materials 31 and 32, productivity of an electrode can be enhanced. During the application of the slurry, the film material 33 prevents the leakage of the electrode slurry. Therefore, the current-collector laminate unit 30 can be conveyed in the horizontal direction, whereby the productivity of the electrode can be enhanced.

Abstract: A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of H2O or CH4 during the He treatment. The low k dielectric layer is then treated with a H2 plasma which converts some of the Si—O and Si—CH3 bonds near the surface to Si—H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two H2 treatment are performed.

Abstract: Printed circuit boards have circuit layers with one or more via filled holes with copper wraps and methods of manufacturing the same. An embodiment of the present invention provides a method to enhance the consistency of the wraparound plating of through-hole vias of printed circuit boards with (requiring) via filling to provide extra reliability to the printed circuit boards and enables the designers and/or manufacturers of printed circuit boards to design and manufacture boards with relatively fine features and/or tight geometries.

Abstract: In a manufacturing method for an interposer, a seed layer is formed at an opening portion in a through hole on back surface side of a substrate, an electrode layer for electroplated coating is formed based on the seed layer, and an electroplated coating layer is formed to fill the through hole from the electrode layer for electroplated coating layer to a front surface side. As a result, a manufacturing method for an interposer is provided in which the manufacturing process is simple and the void is not generated inside of the through hole.

Abstract: A manufacturing method of forming an electrical circuit on a non-conductive carrier comprises following steps. After providing an electrically non-conductive carrier, catalysts are dispersed on or in the electrically non-conductive carrier. A predetermined track structure is formed on the electrically non-conductive carrier to expose the catalysts on the surface of the predetermined track structure. The surface of the predetermined track structure containing the catalysts is metalized to form a conductor track.

Abstract: Methods for forming anisotropic nanotube fabrics are disclosed. In one aspect, a nanotube application solution is rendered into a nematic state prior to its application over a substrate. In another aspect, a pump and narrow nozzle assembly are employed to realize a flow induced alignment of a plurality of individual nanotube elements as they are deposited onto a substrate element. In another aspect, nanotube adhesion promoter materials are used to form a patterned nanotube application layer, providing narrow channels over which nanotube elements will self align during an application process. Specific dip coating processes which are well suited for aiding in the creation of anisotropic nanotube fabrics are also disclosed.

Abstract: A method according to embodiments of the present invention comprises providing a magnetic stack comprising a magnetic layer sub-stack comprising magnetic layers and a bottom conductive electrode and a top conductive electrode electrically connecting the magnetic layer sub-stack at opposite sides thereof; providing a sacrificial pillar on top of the magnetic stack, the sacrificial pillar having an undercut with respect to an overlying second sacrificial material and a sloped foot with increasing cross-sectional dimension towards the magnetic stack, using the sacrificial pillar for patterning the magnetic stack, depositing an insulating layer around the sacrificial pillar, selectively removing the sacrificial pillar, thus creating a contact hole towards the patterned magnetic stack, and filling the contact hole with electrically conductive material.

Abstract: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.

Abstract: A piezoelectric electronic component for use in a cellular phone or the like and capable of achieving reductions in size and profile is provided. A piezoelectric element oscillating in response to application of an input signal and outputting an output signal corresponding to the oscillations is provided on a substrate. The piezoelectric element includes a pad, the pad inputting and outputting the input and output signals. A shell member serving as a sealing member and having an insulation film covering the piezoelectric element is provided on the substrate, the shell member being remote from the piezoelectric element. The shell member includes a through hole above the pad, and the through hole is occluded with an electrode.

Abstract: A method for producing an article having a decorative coating includes depositing at least a first coating layer onto at least a portion of a substrate using a physical or chemical vapor deposition method in a vacuum chamber at sub-atmospheric pressure, the first coating layer comprising a first material having a first color. The method also includes patterning the first coating layer using a non-uniform patterning process to form a patterned coating layer having penetrations through which a portion of an underlying surface is visible, the underlying surface comprising a second material and having a second color that is visually contrasting to the first color. The patterned first coating layer comprises a decorative pattern comprising features distinguishable by an unaided human eye.

Abstract: A tunable liquid crystal optical device defining an optical aperture and having a layered structure. The device includes a film electrode formed on a surface of a first substrate and covered by a second substrate, and a contact structure filling a volume within the layered structure and contacting the film electrode. The contact structure is located outside of the optical aperture and provides an electrical connection surface much larger than a thickness of the film electrode, such that reliable electrical connections may be made to the electrode, particularly in the context of wafer scale manufacturing of such a device.

Abstract: A pixel structure of a transflective liquid crystal display array substrate includes a first patterned conductive layer, a second patterned conductive layer, a transparent patterned conductive layer, a passivation layer, and a patterned reflective metal layer. A first part of the second patterned conductive layer and a first part of the first patterned conductive layer form a first storage capacitor. The first part of the second patterned conductive layer and the transparent patterned conductive layer form a second storage capacitor. The passivation layer is formed to cover the patterned transparent conductive layer and has an opening to expose a part of the patterned transparent conductive layer. The patterned reflective metal layer is formed to cover the passivation layer and electrically connected with the patterned transparent conductive layer via the opening. A method for fabricating the pixel structure of the transflective liquid crystal display array substrate is also disclosed.

Abstract: Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.

Abstract: A method for making a leadless chip carrier (LCC) for use in electronic packages having a core layer stripped of copper cladding, containing drilled clearance holes within, a layer of resin coated copper (RCC) placed on the upper surface of the core layer and a second layer of RCC placed on the lower surface of the core layer. The layers are laminated together with the RCC filling the clearance holes during lamination. A pattern is etched on the RCC and vias are drilled through the filled clearance holes and pre-plated with seed copper layers. The seed copper layers in the vias are then covered by a layer of copper plating to meet the requirements of the core buildup layer, and resin inhibiting conductive anodic filament (CAF) growth within the structure.

Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.

Abstract: A method of manufacturing a mounting substrate, the method including: providing an insulation layer, the insulation layer having a circuit pattern formed in one side thereof; forming at least one bonding pad in the other side of the insulation layer, the bonding pad electrically connected with the circuit pattern; and etching the bonding pad such that a surface of the bonding pad is recessed from a surface of the insulation layer by a predetermined depth.

Abstract: A printed circuit board fabrication method allows a fabrication time and a fabrication cost to be reduced. The fabrication method of the printed circuit board includes steps of forming a resist layer on a surface of the printed circuit board whose surface is made of an insulator, of forming a hole that is connected from the surface of the resist layer to a conductor pattern of an inner layer and a hole and grooves having a depth not connected with the conductor layer of the inner layer by irradiating lasers, of filling a conductive material into the holes and the grooves to form a conductor pattern and of removing the resist layer to project a portion of the conductor pattern out of the surface of the insulating layer.

Abstract: A method for manufacturing a multilayer printed wiring board which enables the dielectric layers to have excellent thickness uniformity, the capacitor circuits to have high registration accuracy and the unnecessary dielectric layer is removed as large as possible; and a multilayer printed wiring board with an embedded capacitor circuit manufactured by the method.

Abstract: Disclosed is an article comprising a layer of nonconductive polymeric material comprising a plurality of integral polymer conduit channels containing a substantially transparent conductive material.

Abstract: A method of manufacturing a wiring substrate of the present invention, includes the steps of forming a seed layer on an underlying layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a copper plating layer in the opening portion by an electroplating, removing the plating resist, wet-etching the seed layer using the copper plating layer as a mask to obtain the wiring layer, roughening a surface of the wiring layer by a blackening process, and forming an insulating layer on the wiring layer, wherein a surface of the copper plating layer is soft-etched simultaneously in the step of etching the seed layer, whereby a soft etching step of the wiring layer carried out prior to the step of the blackening process is omitted.

Abstract: A method for manufacturing a multilayer printed circuit board includes the following steps. A number of laminate units are provided. Each of the laminate units includes an electrically conductive layer with a circuit pattern defined therein, and a release layer releasably attached to the electrically conductive layer. A number of insulation layers are provided. Each of the insulation layers definies a metalized through hole therein. The electrically conductive layers and the insulation layers are stacked alternately one on another such that adjacent electrically conductive layers are insulated by one insulation layer and the metalized through holes electrically connects the circuit patterns of the adjacent electrically conductive layers. In the stacking step, the release layer is removed from the laminate unit after the electrically conductive layer is stacked onto the respective insulation layer, thereby obtaining a pre-laminated multilayer printed circuit board.

Abstract: A semiconductor printed circuit board assembly (PCBA) and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of dielectric substrate placed on the core layer. A second layer of dielectric substrate is placed on the lower surface of the core layer of CIC. The layers are laminated together. Blind vias are laser drilled into the layers of dielectric substrate. The partially completed PCBA is subjected to a reactive ion etch (RIE) plasma as a first step to clean blind vias in the PCBA. After the plasma etch, an acidic etchant liquid solution is used on the blind vias. Pre-plating cleaning of blind vias removes a majority of oxides from the blind vias. Seed copper layers are then applied to the PCBA, followed by a layer of copper plating that can be etched to meet the requirements of the PCBA.

Abstract: In a through hole closing process, a metal plate is attached to one surface of a conductive base member having a plurality of through holes by the use of a magnet, in a copper plating process, a copper plating layer is formed on the conductive base member and the metal plate exposed within the through holes, from the side of the conductive base member where the metal plate is not attached, thereby to fill up the through holes, in a film forming process, a Pd alloy film is formed by plating on the surface of the conductive base member after removal of the metal plate, and in a removal process, the copper plating layer is removed by selective etching, thereby to produce a hydrogen production filter that is used in a reformer a fuel cell so as to be capable of stably producing high purity hydrogen gas.

Abstract: An apparatus includes a sensor that receives a first electrical signal and provides a second electrical signal in response to the first electrical signal. The second electrical signal is based on at least one parameter monitored by the sensor. The apparatus also includes an antenna that converts first wireless signals into the first electrical signal and that converts the second electrical signal into second wireless signals. The antenna includes a substrate, conductive traces, and conductive interconnects. The conductive traces are formed on first and second surfaces of the substrate. The conductive interconnects couple the conductive traces, and the conductive interconnects and the conductive traces form at least one helical arm of the antenna. The conductive traces could be formed in various ways, such as by etching or direct printing. The conductive interconnects could also be formed in various ways, such as by filling vias in the substrate or direct printing.

Abstract: The invention relates to an active matrix liquid crystal display device which uses a switching device to control a pixel, and an object is to provide a liquid crystal display device which has an excellent viewing angle property and high brightness and a fabrication method of the same. A TFT substrate has a structure which reduces the film thickness of a protective insulating film in a control capacitance part in which control capacitance is formed and the film thickness of a protective insulating film in an auxiliary capacitance part in which auxiliary capacitance is formed thinner than the film thickness of a protective insulating film which covers a TFT and the other elements.

Abstract: A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.

Abstract: Luminescence test measurements are conducted using an assay module having integrated electrodes with a reader apparatus adapted to receive assay modules, induce luminescence, preferably electrode induced luminescence, in the wells or assay regions of the assay modules and measure the induced luminescence.

Abstract: An electrospray ion source for a mass spectrometer includes an electrode comprising at least a first plurality of protrusions protruding from a base, each protrusion of the at least a first plurality of protrusions having a respective tip; a conduit for delivering an analyte-bearing liquid to the electrode; and a voltage source, wherein, in operation of the electrospray ion source, the analyte-bearing liquid is caused to move, in the presence of a gas or air, from the base to each protrusion tip along a respective protrusion exterior so as to form a respective stream of charged particles emitted towards an ion inlet aperture of the mass spectrometer under application of voltage applied to the electrode from the voltage source.

Abstract: There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.

Abstract: A traveling wave device includes a slow wave circuit supported by a dielectric membrane. The dielectric membrane can have a thickness substantially smaller than a wavelength of operation of the traveling wave device.

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom.

Abstract: The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.

Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

Abstract: In a method of manufacturing a wiring board, the method includes: (i) forming a plurality of conductive patterns to come into contact with a support plate; (ii) forming a resin layer to cover the plurality of conductive patterns and to come into contact with the support plate; (iii) forming another conductive pattern connected to at least one of the plurality of conductive patterns; and (iv) removing the support plate. A first area of the support plate coming into contact with at least one of the plurality of conductive patterns in step (i) is different in surface roughness from a second area of the support plate coming into contact with the resin layer in step (ii).

Abstract: Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.

Abstract: A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate.

Abstract: A capacitor includes a first electrode. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The capacitor includes a second electrode. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures. The capacitor includes an insulating structure between the first electrode and the second electrode. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other thereby providing higher capacitance density.

Abstract: A solid polymer electrolyte composite membrane and method of manufacturing the same. According to one embodiment, the composite membrane comprises a thin, rigid, dimensionally-stable, non-electrically-conducting support, the support having a plurality of cylindrical, straight-through pores extending perpendicularly between opposing top and bottom surfaces of the support. The pores are unevenly distributed, with some or no pores located along the periphery and more pores located centrally. The pores are completely filled with a solid polymer electrolyte, the solid polymer electrolyte including a dispersed reduced noble metal or noble metal oxide. The solid polymer electrolyte may also be deposited over the top and/or bottom surfaces of the support.

Abstract: A process of an embedded circuit structure is provided. A complex metal layer, a prepreg, a supporting board, another prepreg and another complex metal layer are laminated together, wherein each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the outer surfaces of the inner metal layers is less than the roughness of the second outer surfaces of the outer metal layers, and the outer surfaces of the outer metal layers after laminating are exposed outwards. Each of two patterned photoresist layers is respectively formed on the outer surfaces of the outer metal layers. A metal material is created on portions of the outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers. The patterned photoresist layers are then removed to form a laminating structure.

Abstract: A printed circuit board includes a multiple-layer electrical circuit board and a conductive arm, wherein the conductive arm has an unconnected end located opposite to the connected end of the conductive arm, wherein the conductive arm has a front side and a backside located opposite to the front side of the conductive arm, wherein the backside of the conductive arm is located adjacent to the multiple layer electrical circuit board. The unconnected end of the conductive arm includes a dimple portion formed integrally with and as a unitary part of a remaining portion of the conductive arm, the dimple portion being out of plane with in plane portions of the connected end of the conductive arm so that the dimple portion is at a greater distance from the circuit board than the in plane portions of the conductive arm, the dimple portion being connected to the in plane portions of the conductive arm via an integrally formed and unitary riser portion.

Abstract: A substrate having a blind hole and a method for forming the blind hole. The method includes: (a) providing a substrate having a lower dielectric layer, a copper layer, and an upper dielectric layer; and (b) forming an upper dielectric layer through hole and a copper layer through hole by etching through the upper dielectric layer and the copper layer with laser, and forming a cavity on the lower dielectric layer by using the laser, in which the aperture of the cavity on the upper surface of the lower dielectric layer is larger than that of the copper layer through hole. Therefore, a blind hole space in a shape of a rivet is formed, so that after the blind hole space is electroplated with an electroplating copper layer, the bonding force between the electroplating copper layer and the copper layer is enhanced.

Abstract: Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two or more wires and a second layer of two or more address wires that overlays the first layer. The nanoscale device may also include an intermediate layer positioned between the first layer and the second layer. Two or more redundant electrical component patterns may be fabricated within the intermediate layer so that one or more of the electrical component patterns is aligned with the first and second layers.

Abstract: A pattern forming apparatus comprises a surface treatment system and an ink jet system 14, where a solvent is sprayed from a solvent spray nozzle of the surface treatment system to surface of a glass substrate where a bus line pattern groove is formed. The ink is discharged from an ink discharge nozzle of the ink jet system into the groove of bus line pattern on a glass substrate, and a bus line pattern is formed.

Abstract: There is provided a method of manufacturing a circuit board having a first fixed contact and a second fixed contact that extend substantially orthogonal to each other on the same surface, the life span required for the first fixed contact being longer than that required for the second fixed contact. The method includes: etching a copper foil formed on the entire surface of an insulating substrate to form the patterns of the first and second fixed contacts; polishing the surface of the insulating substrate with buff to remove an oxide film adhered to the copper foil; and sequentially forming a nickel layer having a thickness of about 1 to about 5 ?m and a gold layer having a thickness of about 0.01 to about 0.5 ?m on each of the first and second fixed contacts. In the method, the buffing direction is substantially aligned with a direction in which a first movable contact slides on the first fixed contact.

Abstract: A memory cell (and method of fabricating the memory cell) includes a stencil layer having a first opening, a phase-change material layer formed on a first electrode layer, and an electrically conductive layer formed on the first electrode layer, the electrically conductive layer having a pillar-shaped portion which is formed on the phase-change material layer and fills the first opening.

Abstract: An inkjet head having an electrostatic actuator and a manufacturing method of the same are disclosed. The inkjet head having an electrostatic actuator, comprising a stator, on which is formed a plurality of comb pattern shaped first protrusion parts and second protrusion parts in both directions, and a rotor consisting of a first component and a second component, the ends of which join with the diaphragm, wherein a third protrusion part is formed on the first component, facing the first protrusion parts and meshing with the first protrusion parts without contact; and a fourth protrusion part is formed on the second component, facing the second protrusion parts and meshing with the second protrusion parts without contact, may decrease the size of the head composition and may increase the electrostatic force so that a large displacement may be obtained with little voltage to increase the ink discharge pressure.

Abstract: A device for controlling the flow of electric current is provided. The device comprises a first conductor as thin film form; a second conductor switchably coupled to the first conductor to alternate between an electrically connected state with the first conductor and an electrically disconnected state with the first conductor. At least one conductor further comprises an electrical contact, the electrical contact comprising a solid matrix comprising a plurality of pores; and a filler material disposed within at least a portion of the plurality of pores. The filler material has a melting point of less than about 575 K. A method to make an electrical contact is provided. The method includes the steps of: providing a substrate; providing a plurality of pores on the substrate; and disposing a filler material within at least a portion of the plurality of pores. The filler material has a melting point of less than about 575 K.

Abstract: A circuit board (2) includes an insulation layer (7) where a via conductor (10) is embedded. The via conductor (10) includes: a first conductor portion (10a) having an lower portion narrower than an upper portion; and a second conductor portion (10b) which is formed immediately below the first conductor portion (10a), connected to the first conductor portion (10a), and has a maximum width greater than the upper end width of the first conductor portion (10a). The insulation layer (7) has a plurality of indentations (T1a, T1b) on the surface in contact with the via conductor (10). Convex portions (T2a, T2b) of the via conductor are arranged in the indentations (T1a, T1b).

Abstract: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming an annular groove that surrounds the conductive metal on the first surface of the substrate; (e) forming an insulating material in the central groove and the annular groove; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material.