Abstract: A connecting device for power semiconductor modules with compensation for mechanical stresses includes a sleeve connected to a substrate and having a region with a given very small diameter. A wire pin is provided for insertion into the region of the sleeve during operation to form an electrical connection for a board. The wire pin has a diameter greater than the given diameter for clamping the wire pin upon insertion in the region. Axial freedom of movement of the wire pin in the sleeve makes it possible to avoid mechanical stresses resulting from different material characteristics when a temperature change takes place.

Abstract: A power semiconductor module comprises a metal base, plural wiring substrates provided on said the base, a first wiring substrate of the wiring substrates having a power circuit portion including a power semiconductor device, and substrate containing portions having a resin portion in which one of the wiring substrates is contained. The one of the wiring substrates is positioned in self-alignment on the metal substrate on the basis of an inner wall of the resin portion of the substrate-containing portion.

Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, (as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.

Abstract: A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies in its portion is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on respective of main plane of the semiconductor element and a main electrode plate.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

Abstract: A power semiconductor module in which at least one semiconductor chip with which contact is made by pressure is electrically connected via a contact element to a main connection. The contact element has two planar contact surfaces, between which a spring element is located. Irrespective of the individual position and height of a chip, the respective spring element ensures a standard contact force. Overloading of the semiconductor chips when the module is being clamped in is prevented by ceramic supporting elements.

Abstract: A connecting device for power semiconductor modules with compensation for mechanical stresses includes a sleeve connected to a substrate and having a region with a given very small diameter. A wire pin is provided for insertion into the region of the sleeve during operation to form an electrical connection for a board. The wire pin has a diameter greater than the given diameter for clamping the wire pin upon insertion in the region. Axial freedom of movement of the wire pin in the sleeve makes it possible to avoid mechanical stresses resulting from different material characteristics when a temperature change takes place.

Abstract: A design for an overvoltage protection circuit can be used to fabricate several different circuits incorporating different protection techniques. The design is suitable for use in a single device, which can be easily and inexpensively packaged and protected from the environment. Three terminal protection circuits can have three terminals on an upper surface of a substrate, or one terminal on a lower surface of the substrate, using a single modular design. Additional circuitry can be included to sense for high current conditions which are caused by overvoltages too low to trigger the normal overvoltage protection circuits.

Abstract: The present invention relates to a power transistor module for radio frequency applications, particularly for use in an amplifier stage in a radio base station or in a ground transmitter for TV or radio, wherein said power transistor module comprises a support plate, a power transistor chip arranged thereon, outer electrical connections projecting from the module for external connection and inner electrical connections connected between said transistor chip and said outer connections, at least one of said inner electrical connections comprising a first conductor pattern arranged on a flexible foil. The invention further comprises a power amplifier comprising said module, a method in the fabrication of said module, a method in the fabrication of a power amplifier, where said module is electrically connected to a circuit board mounted at a heat sink and to be mounted at said heat sink, and finally to a power amplifier manufactured according to the method.

Abstract: A semiconductor device including (a) a base plate, (b) an insulation substrate including of an insulator plate with a front electrode and a back electrode bonded thereon and fixed onto the base plate by the back electrode, (c) a semiconductor element fastened onto the insulation substrate by the front electrode, (d) an insulating cover covering the semiconductor element, and (e) electrodes that are led from the semiconductor element to the outside of the insulating cover. The back electrode is larger than the insulator plate, and the base plate has a through hole that is smaller than the back electrode and larger than the insulator plate. The insulation substrate is positioned in the through hole and is fastened onto the back surface of the base plate by the periphery of the back electrode. The insulation substrate can make direct contact with a heat sink without the base plate intervening therebetween, and thereby thermal resistance between the semiconductor element and the heat sink is decreased.

Abstract: A voltage-driven power semiconductor device includes a voltage-driven IEGT chip, a collector electrode plate, an emitter electrode plate, and an inductance material. The collector electrode plate is connected to the collector of the IEGT chip, and press-contacts the IEGT chip from its collector side. The emitter electrode plate press-contacts the IEGT chip from its emitter side. The inductance material has an inductance component and connects the emitter of the IEGT chip and the emitter electrode plate. In the voltage-driven power semiconductor device having this arrangement, an induced electromotive force is generated in the inductance material arranged between the emitter of the IEGT chip and the emitter electrode plate. This induced electromotive force can suppress a steep current change (di/dt) upon an OFF operation, and can further suppress a steep voltage change (dv/dt) caused by the current change (di/dt).

Abstract: High power semiconductor module device constituted in such a manner that a circuit board to which semiconductor pellets are bonded is bonded onto a heat sink, and an electrically insulating case with elasticity which has a tubular portion surrounding the sides of the circuit board is mounted on the heat sink, wherein there is provided a push member which is composed of an electrically insulating material and pushes the respective pellet wholly or partially from above with a predetermined pressure. By thus pushing the pellet by means of the push member, the destruction of the module device due to the thermal fatigue of the bonded portions of the circuit board and the pellets, the bonded portion of the circuit board and heat sink, and the bonded portions of the bonding wires is prevented even when the temperature of the whole module is repeatedly raised and lowered by the repetition of heating and cooling during the operation of the pellets.

Abstract: A pressure assembled power module is provided with first and second die, the first and second die being stacked atop one another and sandwiched between first and second conductive sheets, where the die are separated by a relatively flat central conductive lead. Integral to the central conductive lead are spring elements which bias the die against both the conductive sheets and the central conductive lead. Consequently, electrical and thermal interconnections are achieved between semiconductor devices and between the semiconductor devices and a heat sink or substrate.

Abstract: A power semiconductor switching device comprises a mounting board (110) on which a reverse bias driving circuit (20) for applying a reverse bias between the control electrode and one of two main electrodes of a GTO element (11) housed in a flat package is contained. The mounting board (110) has a through hole through which the main electrode of the GTO element (11) penetrates so that the flat package is located in the proximity of the through hole and the perimeter of the through hole partially surrounds the flat package, and a conducting member formed on one surface of the mounting board (110) and electrically connected to the control electrode of the GTO element (11).

Abstract: In a gate unit (47) for a hard-driven GTO (10), at least some of the electronic components (37, . . , 42) needed for driving are arranged on a printed circuit board (34). The printed circuit board (34) encloses the GTO (10), in order to achieve low-inductance contact, in a plane lying between the anode side and the cathode side of the GTO (10) parallel to the semiconductor substrate (17) of the GTO (10) and is directly connected to the cathode contact (14) and the gate connection (22) of the GTO (10). A compact structure with, at the same time, improved mechanical stability is achieved in such a gate unit in that the components (37, . . , 42) are arranged on the printed circuit board (34) around the GTO (10), in the immediate vicinity of the GTO (10).

Abstract: A monolithic assembly of thyristors having a common cathode and a single gate includes a lightly-doped substrate, several anode regions, on the front surface side, a cathode gate layer on the rear surface side of the substrate, a cathode layer on the rear surface side of the layer coated with a cathode metallization, a well extending from the front surface to the layer, a gate metallization formed on the upper surface of the well, and means for increasing the leakage resistance between the cathode layer and the cathode gate layer.

Abstract: A semiconductor component includes an insulating housing. A plurality of sheet-metal mounting plates are disposed in one and the same plane and are electrically separated from one another in the housing. Semiconductor switches of a rectifier bridge are electrically conductively secured to the mounting plates. Sheet-metal connection leads are electrically connected to the semiconductor switches. At least one sheet-metal connection lead is electrically connected to the mounting plates.

Abstract: An optically-triggered silicon controlled rectifier (SCR) (21) having a number of semiconductor layers (23, 24, 31) diffused into an N type substrate (22). Specifically, the SCR is formed by diffusing a first P+ layer (23) into an upper surface of the substrate. Then, an N+ layer (24) is diffused into a portion of an upper surface of the first P+ layer. An oxide layer (25) which is permeable to optical radiation is formed on the first P+ layer. A conductive cathode terminal (26) is then deposited on the N+ layer. Therefore, a trench (30) is etched in the lower surface of the substrate. The trench is defined by a depth and a surface. A second P+ layer (31) is diffused into the surface of the trench. The depth of the trench substantially defines a spacing between the first and second P+ layers. The chip is soldered onto a pedestal (33) formed on a lead frame (34). The solder is deposited in the trench and contacts the second P+ layer to form an anode terminal (36).

Abstract: In a semiconductor device comprising a semiconductor chip on which semiconductor elements are formed, the semiconductor device further comprises a thermal resistance detector for detecting an increase of thermal resistance of a heat radiating path which is provided to radiate the heat generated in the semiconductor device during operation, and a thermal resistance detection result output circuit for outputting a result of a detection by the thermal resistance detector to an output of the semiconductor device. The semiconductor device can detect at the early stage the increase of the thermal resistance of the heat radiating path, and the deterioration of the semiconductor device due to the crack in the solder layer bonding the chip mounting insulation substrate and heat sink during the operation of the device.

Abstract: A power semiconductor module is specified in which at least one semiconductor chip, which is fitted on a baseplate, is made contact with by a respective contact plunger. The position of the contact plungers can be set individually in a manner corresponding to a distance between the semiconductor chips and a main connection which accommodates the contact plungers. The contact plungers are either subjected to pressure by means of a spring or fixed by means of a solder layer.

Abstract: In a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional units is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates are connected, through

Abstract: A module-type semiconductor device in which a plurality of IGBTs are incorporated in a package in such a way so as to provide a highly reliable pressure contact type semiconductor device having improved heat dissipation performance and small internal wiring inductance. A plurality of IGBTs are incorporated and arranged in a flat package with a hermetic structure consisting of common electrode plates exposed to top and bottom face sides, and an insulating outer frame interposed between the common electrodes plates and seal-joining those electrode plates. Contact terminal bodies which serve as both pressing members and heat radiators are interposed between the top-face-side common electrode plate and emitter electrodes of the respective opposing IGBTs. The emitter electrodes of the IGBTs and the common electrode, and the collector electrodes and the bottom-face-side common electrode, are directly brought in pressure contact with each other.

Abstract: In a power semiconductor device having a power circuit 1 and a control circuit 2 incorporated in a resin case 4, said circuits being mounted on different substrates 1a and 2a and interconnected internally, and power terminals 6 and control terminals 7 connected to the power and control circuits, respectively, being drawn out of the case, the power terminals 6, the control terminals 7 and lead pins 13 are preliminarily molded by an insert technique together with the case as the power terminals 6 and the control terminals 7 are arranged at the peripheral edge of the case 4 whereas the lead pins 13 for establishing interconnection between the power and control circuits are arranged on a pin block 12 provided at the middle stage within the case, and the substrate 1a for the power circuit is mounted on a heat dissipating metal base 11 combined with the bottom side of the case 4 and the substrate 2a for the control circuit on the pin block 12, with the power terminals, control terminals and the pin block being sold

Abstract: An optically-triggered silicon controlled rectifier (SCR) device (21) mounted on a lead frame (34). The SCR device contains a cathode layer (24), an optical gate or control layer (23), and an anode layer (31) formed on a semiconductor substrate (22). The device is soldered onto a pedestal (33) formed on the lead frame. To connect the device to the lead frame, solder is deposited upon the anode layer and the solder fixes the anode layer to the pedestal on the lead frame. The pedestal may be formed by etching or stamping a depression (35) in the lead frame. The device is centered on the pedestal such that the edges of the device are located adjacent the depression, and are spaced from the lead frame.

Abstract: A semiconductor rectifying module has a metal base, a dielectric heat conducting spacer arranged on the metal base and rectifying elements of anode and cathode groups arranged with their cathodes and anodes on the spacer, the rectifying elements being composed of a semiconductor with at least two layers having alternating conductivity types, each of the rectifying elements being surrounded by its side surface by a side layer of a first type conductivity semiconductor material while an original material is a second type conductivity semiconductor material, and being provided with an upper closed separating groove with an external part bordering at least the side layer.

Abstract: The gate lead for a center gate thyristor consists of a contact disk connected to the end of an elongated flexible conductive lead wire which is insulated over its major length. The lead is threaded through the central opening in a plunger which is received in a central opening in the pole piece and terminates in a contact disk which is captured against the bottom of the plunger. A compression spring is captured between the other end of the cylinder and the plunger, thereby to press the contact disk into high pressure contact with the gate electrode on the junction when the device is assembled. The opposite end of the gate lead wire is connected to a terminal which can be easily connected to the interior end of the gate pin which extends through the insulation housing of the assembly.

Abstract: In a bidirectional semiconductor switch which can be switched on and off, printed conductors which form the main term terminals (1, 2) and the control terminals (3, 4) are applied to a baseplate (9). Applied to the printed conductors, which form the main terminals (1, 2), are at least two reverse-blocking semiconductor components (5a-h) which can be switched on and off. The control electrodes (8a, 8e) and the second main electrodes (7a, 7e) of the semiconductor components (5a-h) are interconnected in such a way that the semiconductor switch has the required bidirectional switching function.

Abstract: A semiconductor integrated circuit is provided which can have a high holding current without the penalty of a high gate current. Such a circuit includes a PNPN device and junction bipolar transistor in which a further doped region of the same conductivity type as the transistor collector region and more heavily doped than the collector region prevents the devices affecting each other. The junction bipolar transistor has a current gain of at least 10 and base-collector and base-emitter junctions with reverse breakdown voltages of at least 50 volts. A PN diode can also be used in the circuit.

Abstract: An emitter switched thyristor without parasitic thyristor latch-up susceptibility includes a thyristor having an anode region, a first base region, a second base region in the first base region and an emitter region of first conductivity type in the second base region. An electrical connection is provided between the emitter region and the cathode contact by a field effect transistor in the first base region. The transistor is positioned adjacent the second base region and includes a source electrically connected to the emitter region by a metal strap on the surface of the substrate. The drain of the transistor is electrically connected to the cathode contact and has a conductivity type opposite the conductivity type of the first base region. Accordingly, the cathode contact and anode contact are not separated by a four layer parasitic thyristor. Parasitic latch-up operation is thereby eliminated.

Abstract: Plural modular elementary semiconductor power components are respectively contained within plural semiconductor chip regions of a same semiconductor slice. A metallic layer covers a first surface of the semiconductor slice and is commonly connected to anode electrodes of the plural elementary power components. Plural space apart quadrangular metallic layer regions respectively cover the plural semiconductor chip regions on a second surface of the semiconductor slice and are respectively connected to cathode electrodes of the plural elementary power components. Plural first metallic tracks are spaced apart from and surround the respective plural metallic layer regions on the second surface of the semiconductor slice. Each respective first metallic track is connected to a control electrode of the elementary power component contained within the semiconductor chip regions surrounded by the respective first metallic track.

Abstract: The invention relates to a new arrangement of at least one valve stack (2) for high voltage direct current in a valve hall (1). Said valve stack (2) has a voltage to ground which, in operation, increases along the stack (2). The invention comprises arranging the stack (2) in a substantially lying position at such a distance from the floor and roof (9), respectively, of the valve hall (1) that the smallest electrical flashover distance between live parts on the stack (2) and said floor and roof (9), respectively, is at least contained. Further, the electrical connection is arranged via bushings through the roof (9) of the valve hall (1).

Abstract: In a large-area controlled-turn-off high-power semiconductor component containing a multiplicity of finely structured individual components, a semiconductor device (12) is formed by a multiplicity of small-area semiconductor chips (7) which are accommodated alongside one another in a common housing (13) and connected in parallel. This achievement avoids problems of yield with structures which are becoming finer.

Abstract: An AC solid state relay in a single inline package (SIP) comprised of dual silicon controlled rectifiers (SCRs) with a supporting circuitry mounted directly on an alumina substrate with molecularly bonded copper metalization layers and heat spreader all coated in a thermally conductive epoxy. And a DC solid state relay in a single inline package (SIP) comprised of an NPN power transistor with a supporting circuitry mounted directly on an alumina substrate with molecularly bonded copper metalization layers and heat spreader all coated in a thermally conductive epoxy.