With Housing Or External Electrode Patents (Class 257/177)
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Patent number: 8703599Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.Type: GrantFiled: November 27, 2012Date of Patent: April 22, 2014Assignee: Micron Technology, Inc.Inventor: Setho Sing Fee
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Patent number: 8633511Abstract: A semiconductor device provided with: an island and an island which are separated from each other; leads which approach the islands at one end; a control element which is attached to the island and is connected to a lead through a thin metal wire; and a switching element which is attached to the island and is connected to the lead through a metal wire. Further, the thin metal wire and the thin metal wire are arranged so as to the intersect.Type: GrantFiled: February 25, 2010Date of Patent: January 21, 2014Assignee: ON Semiconductor Trading, Ltd.Inventors: Masakazu Watanabe, Takashi Kuramochi, Masahiro Hatanai
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Patent number: 8610261Abstract: A power semiconductor device includes a power semiconductor module having cylindrical conductors which are joined to a wiring pattern so as to be substantially perpendicular to the wiring pattern and whose openings are exposed at a surface of transfer molding resin, and an insert case having a ceiling portion and peripheral walls, the ceiling portion being provided with external terminals that are fitted into, and passed through, the ceiling portion, the external terminals having outer-surface-side connecting portions at the outer surface side of the ceiling portion and inner-surface-side connecting portions at the inner surface side of the ceiling portion. The power semiconductor module is set within the insert case such that the inner-surface-side connecting portions of the external terminals are inserted into the cylindrical conductors.Type: GrantFiled: October 20, 2009Date of Patent: December 17, 2013Assignee: Mitsubishi Electric CorporationInventors: Seiji Oka, Yoshiko Obiraki, Takeshi Oi
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Patent number: 8587124Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.Type: GrantFiled: June 4, 2008Date of Patent: November 19, 2013Assignee: Teramikros, Inc.Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
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Patent number: 8519433Abstract: The present disclosure provides a semiconductor switching device including a substrate having deposited thereon a cathode, an anode and a gate of the semiconductor switching device, and a connection means for electrically connecting the cathode in the gate of the semiconductor switching device to an external circuit unit. The connection includes a cathode-gate connection unit having a coaxial structure including a gate conductor and a cathode conductor for electrically connecting the cathode and the gate of the semiconductor switching device to the external circuit unit.Type: GrantFiled: June 10, 2010Date of Patent: August 27, 2013Assignee: ABB Research LtdInventors: Didier Cottet, Thomas Stiasny, Tobias Wikstroem
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Publication number: 20130207121Abstract: A power conversion device includes a power conversion semiconductor element having an electrode, an electrode conductor electrically connected to the electrode of the power conversion semiconductor element and including a side face and an upper end portion having a substantially flat upper end face, and a seal material formed of resin to cover the power conversion semiconductor element and the side face of the electrode conductor. The substantially flat upper end face of the electrode conductor is exposed from an upper surface of the seal material, and the upper end portion of the electrode conductor having the substantially flat upper end face has a projecting portion projecting sideward.Type: ApplicationFiled: March 27, 2013Publication date: August 15, 2013Applicant: KABUSHIKI KAISHA YASKAWA DENKIInventor: KABUSHIKI KAISHA YASKAWA DENKI
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Patent number: 8502385Abstract: A power semiconductor device has the power semiconductor elements having back surfaces bonded to wiring patterns and surface electrodes, cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, a transfer mold resin having concave parts which expose the upper surfaces of the communication parts and cover the insulating layer, the wiring patterns, and the power semiconductor elements. External terminals have one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, a bent area which is bent in an L shape and is embedded in the concave part of the transfer mold resin.Type: GrantFiled: June 1, 2011Date of Patent: August 6, 2013Assignee: Mitsubishi Electric CorporationInventors: Seiji Oka, Tetsuya Ueda
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Patent number: 8461462Abstract: A circuit substrate includes a resin layer; and an inorganic insulating layer including a groove portion penetrating the inorganic insulating layer in a thickness direction thereof. A part of the resin layer is in the groove portion.Type: GrantFiled: September 28, 2010Date of Patent: June 11, 2013Assignee: Kyocera CorporationInventor: Katsura Hayashi
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Patent number: 8461623Abstract: A power semiconductor module (1) includes a first MOS transistor (16) connected to a positive side power supply terminal via a first conductor pattern (11), a first free wheeling diode (17) connected to the positive side power supply terminal via a second conductor pattern (12), a second MOS transistor (18) connected to a negative side power supply terminal via a third conductor pattern (13), and a second free wheeling diode (19) connected to the negative side power supply terminal via a fourth conductor pattern (14). These semiconductor elements (16-19) are connected to a load side output terminal via a common fifth conductor pattern (15). The semiconductor element (16, 17) connected to the positive side power supply terminal and the semiconductor element (18, 19) connected to the negative side power supply terminal are arranged alternately, substantially linearly.Type: GrantFiled: April 23, 2009Date of Patent: June 11, 2013Assignee: Mitsubishi Electric CorporationInventor: Shuhei Nakata
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Patent number: 8426889Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.Type: GrantFiled: May 23, 2011Date of Patent: April 23, 2013Assignee: Murata Manufacturing Co., Ltd.Inventors: Jun Adachi, Jun Urakawa, Issei Yamamoto
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Patent number: 8338890Abstract: A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.Type: GrantFiled: November 30, 2009Date of Patent: December 25, 2012Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Shinya Sato, Hiroyuki Takamiya
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Patent number: 8319333Abstract: In the power semiconductor module, a wiring metal plate electrically connects between power semiconductor elements joined to the circuit pattern, and between the power semiconductor elements and the circuit pattern. Cylindrical main terminals are joined, substantially perpendicularly, to the wiring metal plate and the circuit pattern, respectively. A cylindrical control terminal is joined, substantially perpendicularly, to one of the power semiconductor elements.Type: GrantFiled: October 20, 2009Date of Patent: November 27, 2012Assignee: Mitsubishi Electric CorporationInventors: Seiji Oka, Yoshiko Obiraki, Takeshi Oi
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Patent number: 8304889Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.Type: GrantFiled: March 26, 2010Date of Patent: November 6, 2012Assignee: Hitachi, Ltd.Inventors: Kazuhiro Oyama, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
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Patent number: 8299601Abstract: A power semiconductor module includes: a circuit board having a metal base plate, a high thermal conductive insulating layer, and a wiring pattern; power semiconductor elements electrically connected to the wiring pattern; tubular external terminal connection bodies provided to the wiring pattern for external terminals; and a transfer mold resin body encapsulated to expose through-holes in the metal base plate and used to fixedly attach cooling fins to the face of the metal base plate on the other side with attachment members, the face of the metal base plate on the other side, and top portions of the tubular external terminal connection bodies, to form insertion holes for the attachment members communicating with the through-holes and having a larger diameter than the through-holes, and to cover the one side and side faces of the metal base plate and the power semiconductor elements.Type: GrantFiled: August 4, 2009Date of Patent: October 30, 2012Assignee: Mitsubishi Electric CorporationInventors: Seiji Oka, Yoshiko Obiraki, Takeshi Oi
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Patent number: 8299603Abstract: A power semiconductor device in which transfer molding resin seals: a metallic circuit substrate; a power semiconductor element joined to a wiring pattern; and a side surface of a cylindrical external terminal communication section provided on the wiring pattern and to which an external terminal can be inserted and connected. The cylindrical external terminal communication section is substantially perpendicular to a surface on which the wiring pattern is formed. An outer surface of a metal plate of the metallic circuit substrate and a top portion of the cylindrical external terminal communication section are exposed from the transfer molding resin. The transfer molding resin is not present within the cylindrical external terminal communication section.Type: GrantFiled: January 18, 2008Date of Patent: October 30, 2012Assignee: Mitsubishi Electric CorporationInventors: Seiji Oka, Osamu Usui, Yasushi Nakayama, Yoshiko Obiraki, Takeshi Oi
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Patent number: 8283763Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.Type: GrantFiled: June 13, 2007Date of Patent: October 9, 2012Assignee: Hitachi, Ltd.Inventors: Kazuhiro Oyama, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
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Patent number: 8257102Abstract: A dual pole busbar power connector including opposing elements configured to form a slot configured to receive a dual-pole blade therebetween. The slot extends from busbars to opposing element distal ends. The opposing elements each includes: a first contact extending into the slot from the opposing element; and a second contact extending into the slot from the opposing element and disposed farther from a slot busbar end than the first contact. When the dual-pole blade is inserted in the slot the first contact contacts a respective blade element at a location in the slot more proximate the slot busbar end than a slot distal end.Type: GrantFiled: June 3, 2010Date of Patent: September 4, 2012Assignee: General Electric CompanyInventors: Eladio Clemente Delgado, Ljubisa Stevanovic, Richard Alfred Beaupre
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Patent number: 8258618Abstract: The power semiconductor module includes: a circuit substrate; power semiconductor elements joined to element mounting portions of the wiring pattern on the circuit substrate; the cylindrical external terminal communication section joined to the wiring pattern; circuit forming means for connecting between portions that require electrical connection therebetween; and transfer molding resin for sealing these components. The cylindrical external terminal communication section is a metal cylinder, and the cylindrical external terminal communication section has a hole filled with gel.Type: GrantFiled: October 12, 2009Date of Patent: September 4, 2012Assignee: Mitsubishi Electric CorporationInventors: Yoshiko Obiraki, Seiji Oka, Takeshi Oi
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Patent number: 8253236Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.Type: GrantFiled: April 14, 2011Date of Patent: August 28, 2012Assignee: Mitsubishi Electric CorporationInventors: Takeshi Oi, Seiji Oka, Yoshiko Obiraki, Osamu Usui, Yasushi Nakayama
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Patent number: 8237232Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: GrantFiled: March 17, 2011Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Patent number: 8159072Abstract: The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip. The conductive element has a root portion to hold the rectification chip. The coupling collar is located at one end of the base to hold a package. The coupling collar has a plurality of anchor portions in contact with the package. Each anchor portion has a convex portion and a concave portion extended to two ends of the coupling collar. The convex portion and concave portion of two neighboring anchor portions are formed in a staggered manner. The cross section area of the convex portion on the annular edge of the coupling collar is different from the cross section area of the inner wall of the coupling collar. Hence fabrication and assembly are easier. Turning and loosening of the package can be prevented.Type: GrantFiled: December 18, 2009Date of Patent: April 17, 2012Inventor: Wen-Huo Huang
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Patent number: 8076696Abstract: A device is provided that includes a first conductive substrate and a second conductive substrate. A first power semiconductor component having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal can also be electrically coupled to the first conductive substrate, while a negative terminal can be electrically coupled to the second power semiconductor component, and an output terminal may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.Type: GrantFiled: October 30, 2009Date of Patent: December 13, 2011Assignee: General Electric CompanyInventors: Richard Alfred Beaupre, Eladio Clemente Delgado, Ljubisa Dragoljub Stevanovic
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Patent number: 8008699Abstract: Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.Type: GrantFiled: March 10, 2010Date of Patent: August 30, 2011Assignee: Renesas Electronics CorporationInventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
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Patent number: 7932588Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: GrantFiled: January 28, 2010Date of Patent: April 26, 2011Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Patent number: 7910952Abstract: One aspect relates to a power semiconductor arrangement includes a power semiconductor module which is mechanically connected to a heat sink. In order to improve the thermal cycling stability of the connection between a baseplate of the module and a circuit carrier connected thereto, recesses are provided in the baseplate. One aspect further relates to a power semiconductor module.Type: GrantFiled: September 28, 2007Date of Patent: March 22, 2011Assignee: Infineon Technologies AGInventors: Roman Tschirbs, Reinhold Bayerer
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Patent number: 7880283Abstract: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.Type: GrantFiled: April 24, 2007Date of Patent: February 1, 2011Assignee: International Rectifier CorporationInventor: Weidong Zhuang
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Patent number: 7759697Abstract: A semiconductor device is provided which comprises a thermally radiative and electrically conductive support plate 1; and a regulatory semiconducting element 2 mounted on one main surface of support plate 1 through an insulator 3. Insulator 3 comprises an insulative layer 3a mounted on support plate 1 and an adiabatic layer 3b interposed between insulative layer 3a and regulatory semiconducting element 2 to fully protect regulatory semiconducting element 2 from heated environment therearound in the semiconductor device.Type: GrantFiled: March 28, 2005Date of Patent: July 20, 2010Assignee: Sanken Electric Co., Ltd.Inventor: Takaaki Yokoyama
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Patent number: 7750461Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.Type: GrantFiled: April 11, 2003Date of Patent: July 6, 2010Assignee: Curamix Electronics GmbHInventors: Jürgen Schulz-Harder, Peter Haberl
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Patent number: 7745944Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.Type: GrantFiled: August 31, 2005Date of Patent: June 29, 2010Assignee: Micron Technology, Inc.Inventor: Setho Sing Fee
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Patent number: 7737551Abstract: A semiconductor power module has at least one power semiconductor chip (2) which can be controlled by the field effect and has a plurality of fail-safe, small-area SiC power diodes (D1 to D8). The function of a large-area SiC power diode chip which is susceptible to failure is distributed over these small-area, parallel-connected SiC power diode chips (D1 to D8) in such a way that their total area of active SiC diode areas (F1 to F8) corresponds to an area extent of a large-area non-fail-safe SiC power diode chip.Type: GrantFiled: July 3, 2006Date of Patent: June 15, 2010Assignee: Infineon Technologies AGInventor: Ralf Otremba
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Patent number: 7732929Abstract: A power semiconductor component (30) with power semiconductor chip stack (14) has a base power semiconductor chip (16) and a power semiconductor chip (17) stacked on the rear side of the base power semiconductor chip (16), a rewiring structure for the electrical coupling of the power semiconductor chips being arranged within the rear side metallization.Type: GrantFiled: November 21, 2006Date of Patent: June 8, 2010Assignee: Infineon Technologies AGInventors: Ralf Otremba, Xaver Schloegel
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Patent number: 7719027Abstract: The present invention provides an integrated circuit and the method of implementing the same. The integrated circuit includes a die, a base, a covering material and a plurality of pins. The die has at least a first function and a second function and includes a plurality of signal pads and at least a switching pad. The die receives and outputs signals through the signal pads, and the switching pad is utilized to switch the functions of the die. The base is utilized to support the die, and the covering material is utilized to cover the die and the base. One terminal of each pin is inside the covering material and coupled to the corresponding signal pad, and the other terminal of each pin is outside the covering material. The signal pads are connected to the circuits outside the integrate circuit through the pins.Type: GrantFiled: January 22, 2007Date of Patent: May 18, 2010Assignee: MStar Semiconductor, Inc.Inventor: ShouFang Chen
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Patent number: 7696532Abstract: A power semiconductor module (1) with a housing (2) and at least one semiconductor chip (3, 3?) located in it is devised. At least one semiconductor chip (3, 3?) has a first main electrode side (31) and a second main electrode side (32) opposite the first main electrode side, the first main electrode side (31) making thermal and electrical contact with the first base plate (4, 4?). The first cooling device (6) makes thermal and electrical contact with the side of the first base plate (41) facing away from the first main electrode side. The second main electrode side (32) makes thermal and electrical contact with a second base plate (5, 5?). A second cooling device (7) makes thermal contact with the side of the second base plate (51) facing away from the second main electrode side. The heat sink (65) of the first cooling device is supported against the housing (2).Type: GrantFiled: December 16, 2005Date of Patent: April 13, 2010Assignee: ABB Research LtdInventors: Wolfgang Knapp, Stefanie Apeldoorn
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Patent number: 7692293Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.Type: GrantFiled: December 17, 2004Date of Patent: April 6, 2010Assignee: Siemens AktiengesellschaftInventors: Walter Apfelbacher, Norbert Reichenbach, Johann Seitz
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Patent number: 7687885Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.Type: GrantFiled: May 30, 2007Date of Patent: March 30, 2010Assignee: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
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Patent number: 7679173Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: GrantFiled: January 24, 2007Date of Patent: March 16, 2010Assignee: Renesas Technology Corp.Inventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Patent number: 7667316Abstract: A semiconductor integrated circuit includes a power transistor formed on a semiconductor substrate, a plurality of first metal patterns and a plurality of second metal patterns which are formed right above the power transistor and function as a first electrode and as a second electrode of the power transistor, respectively, a plurality of first buses each electrically connected with, of a plurality of first metal patterns, a corresponding first metal pattern, a plurality of second buses each electrically connected with, of a plurality of second metal patterns, a corresponding second metal pattern, wherein one contact pad is provided to each of a plurality of first buses and a plurality of second buses.Type: GrantFiled: October 30, 2007Date of Patent: February 23, 2010Assignee: Panasonic CorporationInventors: Shingo Fukamizu, Yutaka Nabeshima, Takashi Katsuyama
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Patent number: 7659559Abstract: Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.Type: GrantFiled: November 4, 2008Date of Patent: February 9, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventor: Keun-hyuk Lee
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Patent number: 7632718Abstract: A semiconductor power component using flat conductor technology includes a vertical current path through a semiconductor power chip. The semiconductor power chip includes at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a flat conductor chip island of a flat conductor leadframe and the top side electrode is electrically connected to an internal flat conductor of the flat conductor leadframe via a connecting element. The connecting element includes a bonding strip extending from the top side electrode to the internal flat conductor and further includes, on the top side of the bonding strip, bonding wires extending from the top side electrode to the internal flat conductor.Type: GrantFiled: August 16, 2006Date of Patent: December 15, 2009Assignee: Infineon Technologies AGInventor: Khalil Hosseini
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Patent number: 7615852Abstract: The standard housing (27) of a semiconductor component (21), preferably a power semiconductor component features a plurality of external leads (1-5). Between adjacent external leads (2-3 and 4-5) for identical supply potentials or signals, mechanically reinforcing flat conductor webs (28) electrically connecting the external leads (2-3 and 4-5) are located within and/or outside the standard housing (27).Type: GrantFiled: April 21, 2006Date of Patent: November 10, 2009Assignee: Infineon Technologies AGInventor: Ralf Otremba
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Patent number: 7612448Abstract: A power module includes a power semiconductor, a non-power semiconductor, one resin substrate, and a cooling device. The power semiconductor and the non-power semiconductor configure a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate. The cooling device is disposed in order to cool the power semiconductor.Type: GrantFiled: December 1, 2005Date of Patent: November 3, 2009Assignee: Daikin Industries, Ltd.Inventors: Junichi Teraki, Mitsuhiro Tanaka
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Patent number: 7573107Abstract: A power module that includes a power circuit assembly in which power components are electrically and mechanically connected without wires.Type: GrantFiled: September 23, 2005Date of Patent: August 11, 2009Assignee: International Rectifier CorporationInventors: Alberto Guerra, Norman G. Connah, Mark Steers, George Pearson
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Patent number: 7569920Abstract: An electronic component includes a vertical semiconductor power transistor and a further semiconductor device arranged on the transistor to form a stack. The first vertical semiconductor power transistor has a semiconductor body having a first side and a second side and device structures, at least one first electrode positioned on the first side and at least one second electrode positioned on the second side. The semiconductor body further has at least one electrically conductive via. The via extends from the first side to the second side of the semiconductor body and is galvanically isolated from the device structures of the semiconductor body and from the first electrode and the second electrode.Type: GrantFiled: May 10, 2006Date of Patent: August 4, 2009Assignee: Infineon Technologies AGInventors: Ralf Otremba, Klaus Schiess
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Patent number: 7566967Abstract: In one embodiment, a semiconductor package structure includes a plurality of upright clips having ends with mounting surfaces for vertically mounting the package to a next level of assembly. A semiconductor chip is interposed between the upright clips together with one or more spacers.Type: GrantFiled: January 22, 2008Date of Patent: July 28, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Stephen St. Germain, Francis J. Carney, Bruce Alan Huing
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Patent number: 7542317Abstract: The power conversion apparatus uses the semiconductor device. Said semiconductor device includes a first group of power semiconductor elements at least one of which is electrically connected between a first potential and a third potential, a second group of power semiconductor elements at least one of which is electrically connected between a second potential and the third potential, and a third group of power semiconductor elements at least one of which is electrically connected between the first potential and the third potential. The second group is disposed between the first group and third group. Thereby, a low-loss semiconductor device having both inductance reducibility and heat generation balancing capability and also an electric power conversion apparatus using the same is provided.Type: GrantFiled: August 10, 2006Date of Patent: June 2, 2009Assignee: Hitachi, Ltd.Inventors: Katsunori Azuma, Toshiaki Morita, Hiroshi Hozoji, Kazuhiro Suzuki, Toshiya Satoh, Osamu Otsuka
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Publication number: 20090095979Abstract: A power module includes a substrate having first and second main substrate surfaces; a semiconductor device disposed on the first main substrate surface, and having a first main surface on which a first main electrode is formed, and a second main surface on which a second main electrode in contact with the first main substrate surface is formed; a heat conduction portion disposed on the first main substrate surface in a residual region of a region on which the semiconductor device is disposed; and an upper cooling portion disposed on the heat conduction portion.Type: ApplicationFiled: October 1, 2008Publication date: April 16, 2009Applicant: Rohm Co., Ltd.Inventors: Masao Saito, Takukazu Otsuka, Keiji Okumura
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Patent number: 7514778Abstract: A power semiconductor device is disclosed. In one embodiment, the power semiconductor device includes a plurality of device components that are contact-connected by bonding wires having different thicknesses. The surface of at least one bonding wire serves as a contact area for at least one further bonding wire, the bonding wire that serves as contact area being thicker than the bonding wire contact-connected thereon.Type: GrantFiled: September 26, 2005Date of Patent: April 7, 2009Assignee: Infineon Technologies AGInventors: Ralf Otremba, Khalil Hosseini
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Patent number: 7508077Abstract: A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first metal layer provided on a major surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate; a second metal layer provided on the first metal layer and primarily composed of aluminum; a third metal layer provided on the second metal layer and primarily composed of molybdenum or titanium; and a solder bonding metal layer provided on the third metal layer and including at least a fourth metal layer which is primarily composed of nickel, ion or cobalt.Type: GrantFiled: July 1, 2005Date of Patent: March 24, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Watanabe, Tetsuya Fukui
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Patent number: 7470939Abstract: A semiconductor device is disclosed that includes a first and a second semiconductor package. Each semiconductor package includes a semiconductor element, a plurality of electrode members, and an encapsulating member. The semiconductor elements are interposed between the respective electrode members, and the electrode members are in electrical communication with and provide heat transfer for the respective semiconductor element. The encapsulating member encapsulates the respective semiconductor element between the respective electrode members, and an outer surface of each of the electrode members is exposed from the respective encapsulating member. Each semiconductor package includes a connecting terminal electrically coupled to one of the electrode members and extending outward so as to be exposed from the respective encapsulating member. The connecting terminals are electrically connected by abutment or via a conductive junction material.Type: GrantFiled: July 12, 2006Date of Patent: December 30, 2008Assignee: DENSO CORPORATIONInventors: Akira Mochida, Kuniaki Mamitsu, Kenichi Oohama
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Patent number: 7462888Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.Type: GrantFiled: September 13, 2007Date of Patent: December 9, 2008Assignee: The Kansai Electric Power Co., Inc.Inventor: Yoshitaka Sugawara