Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract: An infrared transmission large-area shutter is provided. The infrared transmission large-area shutter includes a first contact layer on a substrate, a plurality of stacks formed in a two-dimensional (2D) array pattern on a first region of the first contact layer, each stack comprising a lower reflection layer, an active layer, an upper reflection layer, and a second contact layer which are formed sequentially in this order on the first contact layer, a first electrode formed on the first contact layer, a plurality of second electrodes on the second contact layers, a first polymer layer that surrounds sidewalls of the plurality of stacks on the first contact layer, and a second polymer layer, which is transparent to infrared rays, to cover the second electrode on the second contact layer. A through hole corresponding to the plurality of stacks is formed in the substrate.

Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.

Abstract: Provided are a light receiving element etc. which have a high responsivity over the near- to mid-infrared region and stably have a high quality while maintaining the economical efficiency. The light receiving element includes an InP substrate that is transparent to light having a wavelength of 3 to 12 ?m, a middle layer that is epitaxially grown on the InP substrate, a GaSb buffer layer located in contact with the middle layer, and a light-receiving layer that is epitaxially grown on the GaSb buffer layer and that has a type-II multiple quantum well structure. The GaSb buffer layer is epitaxially grown on the middle layer while exceeding a range of a normal lattice-matching condition.

Abstract: A method of forming CMOS structures with selective tensile strained NFET fins and relaxed PFET fins includes performing a first, partial fin etch on a tensile strained silicon layer of a semiconductor substrate; selectively oxidizing bottom surfaces of the tensile strained silicon layer in a PFET region of the semiconductor substrate, thereby causing PFET silicon fins defined in the PFET region to become relaxed; and performing a second fin etch to define NFET silicon fins in an NFET region of the semiconductor substrate, wherein the NFET silicon fins remain tensile strained.

Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.

Abstract: A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

Abstract: In at least one embodiment, the semiconductor layer sequence (1) is provided for an optoelectronic semiconductor chip (10). The semiconductor layer sequence (1) contains at least three quantum wells (2) which are arranged to generate electromagnetic radiation. Furthermore, the semiconductor layer sequence (1) includes a plurality of barrier layers (3), of which at least one barrier layer is arranged between two adjacent quantum wells (2) in each case. The quantum wells (2) have a first average indium content and the barrier layers (3) have a second, smaller, average indium content. A second average lattice constant of the barrier layers (3) is thereby smaller than a first average lattice constant of the quantum wells (2).

Abstract: A solid-state imaging device includes a Multi-Quantum Wells (MQW) structure which combines and uses a non-Group IV lattice matching-based compound semiconductor with an absolute value of a mismatch ratio of less than 1% on a silicon substrate so as to have sensitivity to at least infrared light.

Abstract: A structure comprised of an InAsSb layer adjacent to a GaSb layer, with the adjacent InAsSb and GaSb layers repeating to form a superlattice (SL). The structure is preferably an unstrained SL, wherein the composition of the InAsSb layer is InAs0.91Sb0.09; the InAs0.91 Sb0.09 layers are preferably lattice-matched to the GaSb layers. The SL structure is preferably arranged such that the Sb component of the InAsSb layers reduces the strain in the SL structure so that it is less than that found in an InAs/GaSb Type-II Strained Layer Superlattice (SLS). The present SL structure is suitably employed as part of an infrared photodetector.

Abstract: A thin layer substrate has a plurality of micron sized electrically conductive whisker components which are arranged in parallel and extending from one surface of the substrate to another surface to provide electrically conductive paths through the substrate. Such a substrate may be usable for micron sized LEDs.

Abstract: This process comprises steps of: a) providing a first substrate comprising the active layer made of a first material of Young's modulus E1 and of thickness h1; b) providing a second substrate made of a second material of Young's modulus E2 and of thickness h2; c) bending the first substrate and the second substrate such that they each have a curved shape of a radius of curvature R; d) joining the second substrate to the active layer such that the second substrate closely follows the shape of the first substrate; and e) re-establishing the initial at-rest shape of the second substrate, the process being noteworthy in that the second material of the second substrate is a flexible material respecting the relationship E2/E1<10?2, in that the thickness of the second substrate respects the relationship h2/h1?104, and in that the radius of curvature respects the relationship R = h 2 2 ? ? ? .

Abstract: There is provided a power semiconductor module in which power semiconductor elements, integration of which may be difficult due to heating, are modularized. The power semiconductor module includes: a heat dissipation substrate electrically connected to a common connection terminal; and a plurality of electronic elements disposed on the heat dissipation substrate, wherein the electronic elements have varying spaces therebetween.

Abstract: A strained silicon material layer is bonded to a relaxed silicon material layer. The strained silicon material and any defect containing region formed during bonding are completely removed from a second device region, while a portion of the strained silicon material layer remains in a first device region. A relaxed silicon material portion is epitaxially formed on an exposed portion of the relaxed silicon material layer. A high performance nFET device, in which leakage is not a main concern, can be formed on the remaining portion of the strained silicon material layer in the first device region, and a pFET device or a low leakage nFET device can be formed on the epitaxially formed relaxed silicon material portion.

Abstract: One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer.

Abstract: A semiconductor device includes: a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.

Abstract: A device that includes a pattern of strained material and relaxed material on a substrate, a strained device in the strained material, and a non-strained device in the relaxed material. The strained material may be silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. Carbon-doped silicon or germanium-doped silicon may be used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

Abstract: A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer.

Abstract: A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract: A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×1019 atoms/cm3 and 5×1020 atoms/cm3, and the first and second relatively-highly silicon-doped regions have silicon concentrations that exceed 1×1018 atoms/cm3.

Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.

Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.

Abstract: A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including AlxGa1-xN(0?x?1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.

Abstract: A layered group III-nitride article includes a single crystal silicon substrate, and a highly textured group III-nitride layer, such as GaN, disposed on the silicon substrate. The highly textured group III-nitride layer is crack free and has a thickness of at least 10 ?m. A method for forming highly textured group III-nitride layers includes the steps of providing a single crystal silicon comprising substrate, depositing a nanostructured InxGa1-xN (1?x?0) interlayer on the silicon substrate, and depositing a highly textured group III-nitride layer on the interlayer. The interlayer has a nano indentation hardness that is less than both the silicon substrate and the highly textured group III-nitride layer.

Abstract: Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).

Abstract: An electrochemically-gated field-effect transistor includes a source electrode, a drain electrode, a gate electrode, a transistor channel and an electrolyte. The transistor channel is located between the source electrode and the drain electrode. The electrolyte completely covers the transistor channel and has a one-dimensional nanostructure and a solid polymer-based electrolyte that is employed as the electrolyte.

Abstract: Embodiments of strain-balanced superlattice infrared detector devices and their fabrication are disclosed. In one embodiment, an infrared detector device includes a first contact layer, and absorber superlattice region, a wider gap unipolar barrier region, and a second contact layer. The absorber superlattice region has a period defined by a first InAs layer, strain-balancing structure, a second InAs layer, and an InAsSb layer. The strain-balancing structure comprises an arbitrary alloy layer sequence containing at least one constituent element of aluminum or phosphor, e.g., InGaAs, AlInAs InAsP. In another embodiment, the absorber superlattice region has a period defined by a first InAs layer, first strain-balancing structure, a second InAs layer, a first GaSb layer, a second strain-balancing structure, and a second GaSb layer. The first strain-balancing structure includes at least one constituent element of aluminum or phosphor, e.g., InGaAs, AlInAs InAsP.

Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material.

Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.

Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.

Abstract: Virtual substrates made by hydride vapor phase epitaxy are provided comprising a semiconductor growth substrate and a substantially strain-relaxed metamorphic buffer layer (MBL) structure comprising one or more layers of a semiconductor alloy on the growth substrate. The MBL structure is compositionally graded such that its lattice constant transitions from a lattice constant at the interface with the growth substrate that is substantially the same as the lattice constant of the growth substrate to a lattice constant at a surface opposite the interface that is different from the lattice constant of the growth substrate. The virtual substrates comprise relatively thick MBL structures (e.g., >20 ?m) and relatively thick growth substrates (e.g., >0.

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Abstract: A device comprises insulation regions disposed in a substrate and a semiconductor fin extending above top surfaces of the insulation regions. The semiconductor fin comprises a first material. A semiconductor region comprising a second material extends from a first side of the semiconductor fin over a top of the fin to a second side of the fin. A strain buffer layer is disposed between, and contacts, the semiconductor fin and the semiconductor region. The strain buffer layer comprises an oxide, and a bottommost surface of the strain buffer layer is vertically spaced apart from the top surfaces of the insulation regions.

Abstract: A dual-band infrared detector structure based on Type-II superlattices (T2SL) has been developed and experimentally validated. The structure according to the principles of the present invention is designed for a single Indium bump architecture and utilizes a T2SL barrier design that omits the traditional p-n junction region. The barrier design comprises multiple periods where each period comprises multiple monolayers doped P type. By selecting the composition, number of monolayers per period and number of periods, a transition region is created in the conduction band between a first absorber layer and a second absorber layer that allows operation at low biases (<100 mV for both bands) and exhibits a dark current density in the longer wavelength band comparable to that obtained with single-color detectors.

Abstract: The present invention provides a Group III nitride semiconductor light-emitting device which is intended to relax stress applied to a light-emitting layer. The light-emitting device includes an MQW layer, and an n-side superlattice layer formed below the MQW layer. The n-side superlattice layer is formed by repeatedly depositing layer units, each unit including an InGaN layer, a GaN layer, and an n-GaN layer which are sequentially deposited from the side of the sapphire substrate. In the n-side superlattice layer, an InGaN layer more proximal to the MQW layer has a higher In compositional proportion. The In compositional proportion of the InGaN layer (which is most proximal to the MQW layer) of the n-side superlattice layer is 70% to 100% of the In compositional proportion of the InGaN layer (which is most proximal to the n-side superlattice layer) of the MQW layer.

Abstract: A device includes a substrate, insulation regions extending into the substrate, and a semiconductor fin higher than top surfaces of the insulation regions. The semiconductor fin has a first lattice constant. A semiconductor region includes sidewall portions on opposite sides of the semiconductor fin, and a top portion over the semiconductor fin. The semiconductor region has a second lattice constant different from the first lattice constant. A strain buffer layer is between and contacting the semiconductor fin and the semiconductor region. The strain buffer layer includes an oxide.

Abstract: In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized.

Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: For a nitride semiconductor light emitting device, a c-axis vector of hexagonal GaN of a support substrate is inclined to an X-axis direction with respect to a normal axis Nx normal to a primary surface. In a semiconductor region an active layer, a first gallium nitride-based semiconductor layer, an electron block layer, and a second gallium nitride-based semiconductor layer are arranged along the normal axis on the primary surface of the support substrate. A p-type cladding layer is comprised of AlGaN, and the electron block layer is comprised of AlGaN. The electron block layer is subject to tensile strain in the X-axis direction. The first gallium nitride-based semiconductor layer is subject to compressive strain in the X-axis direction. The misfit dislocation density at an interface is smaller than that at an interface. A barrier to electrons at the interface is raised by piezoelectric polarization.