Abstract: A device for generating terahertz radiation. The device comprising a dipole generating layer, a coupling block and an extraction block. The coupling block is transparent to laser light and is in contact with the surface of the dipole generating layer to couple light from a laser to the surface of the dipole generating layer, when the device is in use. The extraction block is located in contact with the surface of the dipole generating layer to provide an emission extraction surface. The refractive indices of the dipole forming layer, the coupling block and the extraction block are substantially equal. In this way, the dipole which is generated upon illumination of the dipole generating layer by a laser, has an axis which is not perpendicular to the emission.

Abstract: A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1-R)N semiconductors having different compositions and an intermediate layer of GaN or other Ga-rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth is removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

Abstract: Semiconductor quantum well devices and methods of making the same are described. In one aspect, a device includes a quantum well structure that includes semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells. Each of the quantum wells includes a quantum well layer interposed between barrier layers. One of the semiconductor layers that functions as a barrier layer of one of the light-hole quantum wells also functions as the quantum well layer of one of the heavy-hole quantum wells. Another of the semiconductor layers that functions as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.

Abstract: A semiconductor photodetection device includes a photodetection layer formed of an alternate and repetitive stacking of an optical absorption layer accumulating therein a compressive strain and a stress-compensating layer accumulating therein a compensating tensile strain, wherein the optical absorption layer has a thickness larger than a thickness of the stress-compensating layer.

Abstract: A microelectronic device includes a substrate, and a patterned feature located over the substrate and a plurality of doped regions, wherein the patterned feature includes at least one electrode. The microelectronic device includes at least one sill region for the enhancement of electron and/or hole mobility.

Abstract: Disclosed is a natural-superlattice homologous single-crystal thin film, which includes a complex oxide which is epitaxially grown on either one of a ZnO epitaxial thin film formed on a single-crystal substrate, the single-crystal substrate after disappearance of the ZnO epitaxial thin film and a ZnO single crystal. The complex oxide is expressed by the formula: M1M2O3 (ZnO)m, wherein M1 is at least one selected from the group consisting of Ga, Fe, Sc, In, Lu, Yb, Tm, Er, Ho and Y, M2 is at least one selected from the group consisting of Mn, Fe, Ga, In and Al, and m is a natural number of 1 or more. A natural-superlattice homologous single-crystal thin film formed by depositing the complex oxide and subjecting the obtained layered film to a thermal anneal treatment can be used in optimal devices, electronic devices and X-ray optical devices.

Abstract: The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may further include at least one pair of oppositely-doped regions therein defining at least one semiconductor junction.

Abstract: A structure for the n-type contact layer in the GaN-based MQW LEDs is provided. Instead of using Si-doped GaN as commonly found in conventional GaN-based MQW LEDs, the n-type contact layer provided by the present invention achieves high doping density (>1×1019 cm?3) and low resistivity through a superlattice structure combining two types of materials, AlmInnGa1-m-nN and AlpInqGa1-p-qN (0?m,n<1, 0<p,q<1, p+q?1, m<p), each having its specific composition and doping density. In addition, by controlling the composition of Al, In, and Ga in the two materials, the n-type contact layer would have a compatible lattice constant with the substrate and the epitaxial structure of the GaN-based MQW LEDs. This n-type contact layer, therefore, would not chap from the heavy Si doping, have a superior quality, and reduce the difficulties of forming n-type ohmic contact electrode. In turn, the GaN-based MQW LEDs would require a lower operation voltage.

Abstract: A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon germanium. The p-legs includes alternating layers of B4C and B9C. In preferred embodiments the layers are about 100 angstroms thick. Applicants have fabricated and tested a first Si/SiGe (n-leg) and B4C/B9C (p-leg) quantum well thermocouple. Each leg was only 11 microns thick on a 5 micron Si substrate. Nevertheless, in actual tests the thermocouple operated with an amazing efficiency of 14 percent with a Th of 250 degrees C. Thermoelectric modules made according to the present invention are useful for both cooling applications as well as electric power generation. This preferred embodiment is a thermoelectric 10×10 egg crate type module about 6 cm×6 cm×0.

Abstract: An InGaAlAs-based buried type laser is expected to improve properties of the device, but generates defects at a re-growth interface and is difficult to realize a long-term reliability necessary for optical communication, due to inclusion of Al in an active layer. A semiconductor optical device and an optical module including a package substrate and a semiconductor optical device mounted on the package substrate are provided, whereby there are realized the improvement of device properties and the long-term reliability through the use of an Al composition ratio-reduced tensile strained quantum well layer.

Abstract: A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rare earth ion.

Abstract: The invention concerns a superluminescent light emitting diode (SLED) comprising a semiconductor heterostructure forming a PN junction and a waveguide. The semiconductor heterostructure includes a gain region with a contact means for biasing the PN junction so as to produce light emission including stimulated emission from an active zone of the gain region, and in the active zone a plurality of quantum dot layers, each quantum dot layer made up of a plurality of quantum dots and a plurality of adjoining layers, each adjoining layer adjacent to one of said quantum dot layers. The material composition or a deposition parameter of at least two adjoining layers is different. This ensures an enhanced emission spectral width.

Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.

Abstract: A metamorphic device including a substrate structure upon which a semiconductor device can be formed. In the metamorphic device, a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading layer which grades past the desired lattice constant is configured at a low temperature. A reverse grading layer grades the lattice constant back to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in at least the grading layer and the reverse grading layer. Thereon a strained layer superlattice is created upon which a high-speed photodiode or other semiconductor device can be formed.

Abstract: A method of forming a MOSFET device is provided. The method includes providing a substrate. The method includes forming on the substrate a relaxed SiGe layer having a Ge content between 0.51 and 0.80. Furthermore, the method includes depositing on the relaxed SiGe layer a ?-Si layer.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: There is disclosed an apparatus including a substrate defining an interior of the apparatus, a device exterior to the substrate including a gate electrode, and a straining layer exterior to the gate electrode and exterior to the substrate.

Abstract: A semiconductor laser device having an active region including alternating layers of at least one quantum well layer and a plurality of barrier layers, where two of the plurality of barrier layers are the outermost layers of the alternating layers. Each of the at least one quantum well layer has a compressive strain, and each of the plurality of barrier layers has a tensile strain. In the active region, a strain buffer layer having an intermediate strain is formed between each quantum well layer and each of two barrier layers adjacent to the quantum well layer. Interfacial strain is thus reduced, improving high-output-power characteristics.

Abstract: Reflecting layers in first, second and third regions are separated from a reflecting layer in the surrounding region by a separating groove. The first region is folded in a valley shape from a substrate at a groove, the first region and the second region are folded in a valley shape at a groove, the third region is folded in a valley shape from the substrate at a groove, and the second region and the third region are folded in a mountain shape by a line.

Abstract: A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.

Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

Abstract: A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping to be formed using a standard technique such as ion implantation, and further allows the high-mobility channel to be in close proximity to the counter doping without degradation of the mobility.

Abstract: A photodetector device includes a plurality of Ge epilayers that are grown on a substrate and annealed in a defined temperature range. The Ge epilayers form a tensile strained Ge layer that allows the photodetector device to operate efficiently in the C-band and L-band.

Abstract: Tensile or compressive stress may be added in one or more selected locations to the biaxial residual stress existing in the channel of a semiconductor device, such as a MOSFET. The periphery of the active area containing the channel is modified by following layout procedures that result in forming outward protrusions of or inward depressions in the periphery of the active area and its surrounding shallow trench isolation during generally otherwise conventional fabrication of the device.

Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: An InAs/GaAs quantum dot light emitting diode and a method of fabricating the same are disclosed. The InAs/GaAs quantum dot light emitting diode which is formed by turning off an As shutter and using As background concentration for epitaxy, comprises a Si-doped GaAs substrate, a N-type structure, an undoped quantum well, aseries of quantum dot layers, spacer layers, a barrier layer and a P-type structure.

Abstract: An intentional recess or indentation is created in a region of semiconductor material that will become part of a channel of a metal oxide semiconductor (MOS) transistor structure. A layer is created on a surface of the recess to induce an appropriate type of stress in the channel.

Abstract: An n-type strained silicon MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon regions are provided in the silicon geranium layer at opposing sides of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon regions. By forming the shallow source and drain extensions in silicon regions rather than in silicon germanium, source and drain extension distortions caused by the enhanced diffusion rate of arsenic in silicon germanium are avoided.

Abstract: A semiconductor laser device includes a resonant cavity formed on a GaAs substrate, the resonant cavity including a quantum well (QW) active layer structure having a GaInNAs(Sb) well layer and a pair of barrier layers. The QW structure has a conduction band offset energy (?Ec) equal to or higher than 350 milli-electron-volts (meV) between the well layer and the barrier layers, and each of the barrier layers a tensile strain equal to or lower than 2.5%.

Abstract: The invention discloses improved structures of light-processing (e.g. light-emitting and light-absorbing/sensing) devices, in particular Vertical Cavity Surface Emitting Lasers (VCSELs), such as may find use in telecommunications applications. The disclosed VSCAL devices and production methods provide for an active region having a quantum well structure grown on GaAs-containing substrates, thus providing processing compatibility for light having wavelength in the range 1.0 to 1.6 ?m. The active region structure combines strain-compensating barriers with different band alignments in the quantum wells to achieve a long emission wavelength while at the same time decreasing the strain in the structure. The improved functioning of the devices disclosed results from building them with multicomponent alloy layers having a large number of constituents.

Abstract: A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rare earth ion.

Abstract: A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.

Abstract: A heterojunction bipolar transistor is presented, comprising a substrate having formed thereon a heterojunction bipolar transistor layer structure, and including an emitter layer. The emitter layer includes a strained, n-doped compound of indium arsenic and phosphorus. The transistor further comprises, between the substrate and emitter layer, a subcollector layer, a collector layer, a base layer, and an optional spacer layer. The emitter layer may include a graded portion. A contact layer is formed on the emitter layer to provide contacts for the device.

Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0?x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1-x2-y2Gex2Cy2 layer (0<x2?1 and 0?y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.

Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

Abstract: A photodetector device includes a plurality of Ge epilayers that are grown on a substrate and annealed in a defined temperature range. The Ge epilayers form a tensile strained Ge layer that allows the photodetector device to operate efficiently in the C-band and L-band.

Abstract: A semiconductor device comprises a first Si1−&agr;Ge&agr; film, a first cap film, a second Si1−&bgr;Ge&bgr; film (&bgr;<&agr;≦1) and a second cap film formed in this order on a substrate whose surface is formed of silicon, wherein the first Si1−&agr;Ge&agr; film is relaxed to have substantially the same lattice constant as that of the second Si1−&bgr;Ge&bgr; film in a horizontal plane.

Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a graded base layer formed from antimony. The graded base allows the heterojunction bipolar transistor to establish a quasi-electric field to yield an improved cutoff frequency.

Abstract: An optical semiconductor device comprising: an active region; and a p-doped cladding region disposed on one side of the active region; wherein an electron-reflecting barrier is provided on the p-side of the active region for reflecting both &Ggr;-electrons and X-electrons, the electron-reflecting barrier providing a greater potential barrier to &Ggr;-electrons than the p-doped cladding region.

Abstract: A strained silicon layer fabrication and a method for fabrication thereof employ a strained insulator material layer formed over a strained silicon layer in turn formed upon a strained silicon-germanium alloy material layer which is formed upon a relaxed material substrate. The strained insulator material layer provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.