Abstract: A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.

Abstract: A dielectric device has a multi-layer oxide artificial lattice. The artificial lattice is a stacked structure with a plurality of dielectrics. The dielectric film is deposited at a single atomic layer thickness or at a unit lattice thickness. The dielectric film is formed by repeatedly depositing with layer-by-layer growth process at least two dielectric materials having dielectric constant different from each other at least one time in a range of the single atomic layer thickness to 20 nm or by depositing at least two dielectric materials in a predetermined alignment adapted for a functional device, thereby forming one artificial lattice having an identical directional feature. By utilizing the stress applied to an interfacial surface of the consisting layers in the artificial oxide lattice, the dielectric constant and tunability are greatly improved, so the artificial lattice can be adapted for high-speed switching and high-density semiconductor devices and high-frequency response telecommunication devices.

Abstract: A semiconductor apparatus includes a substrate, a buffer layer made of a monocrystal semiconductor material and formed on the substrate, a strained-Si layer formed on the buffer layer and having a lattice constant different from that of the buffer layer, a monocrystal insulating film formed on the strained-Si layer and made of a material having a rare earth structure with a lattice constant different from that of Si, and an electrode formed on the insulating film.

Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.

Abstract: An integrated circuit device comprises an insulation layer formed on a substrate, a plurality of lattice relaxed SiGe layers each formed in an island form on the insulation layer, wherein a maximum size of the island form thereof is 10 &mgr;m or less, one of a strained Si layer, a strained SiGe layer and a strained Ge layer formed on at least one of the plurality of lattice relaxed SiGe layers, and a field effect transistor having a gate electrode and source and drain regions, wherein the gate electrode is formed on one of the strained Si layer, the strained SiGe layer and the strained Ge layer with a gate insulation film is disposed therebetween, and the source and drain regions is formed to sandwich a channel region formed below the gate electrode with the gate insulation film disposed therebetween.

Abstract: The invention relates to a device comprising microstructures or nanostructures on a support, characterized in that the support comprises: a) a substrate (1) comprising at least one part composed of a crystalline material, this part having a surface (2) with a stress field or a topology associated with a stress field, the stress field being associated with dislocations, b) an intermediate layer (3) bonded to the surface (2), and having a thickness and/or composition and/or a surface state enabling transmission of said stress field through this layer as far as its free face that supports microstructures or nanostructures (4).

Abstract: The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The source/drain regions can extend into the Si/Ge. The memory or logic devices further include an insulative material over the floating gate or plate, and a control gate separated from the floating gate or plate by the insulative material. The crystalline Si/Ge can have a relaxed crystalline lattice, and a crystalline layer having a strained crystalline lattice can be formed between the relaxed crystalline lattice and the floating gate or plate. The devices can be fabricated over any of a variety of substrates. The floating plate option can provide lower programming voltage and orders of magnitude superior endurance compared to other options.

Abstract: A semiconductor device wherein some parts of a circuit are disposed on Si—Ge regions and others are implemented in Silicon substrate regions of the chip. The Si—Ge region provides that carrier flow is forced to the surface channel region which helps reduce short channel effects. A method of making such a semiconductor device is also provided and includes steps of forming a thermal oxide layer on a Silicon substrate, masking at least a portion of the thermal oxide layer, removing at least a portion of the thermal oxide layer in order to expose a portion of the Silicon substrate, epitaxially growing an Si—Ge layer on the exposed portion of the Silicon substrate, epitaxially growing a Silicon layer on the Si—Ge layer, and continuing manufacture of the device by forming a circuit on the Si—Ge regions and non-Si—Ge regions of the semiconductor device.

Abstract: A method for aligning quantum dots effectively controls a growth position of the quantum dots for obviating an irregularity of a position of spontaneous formation quantum dots, and thus aligns the quantum dots in one-dimension (1-D) or two-dimension (2-D). A semiconductor device fabricated using the method manufactures a superlattice layer layer for adjusting an internal strain distribution by alternately depositing two semiconductor materials having different lattice constant, and grows spontaneous formation quantum dots on the superlattice layer. As a result, a strained force caused by the superlattice layer influences on the quantum dots so that the quantum dots can be regularly aligned.

Abstract: A solid-state image sensor able to adjust sensitivity in a wide range without causing flicker or stripes, even when the illumination source is a fluorescent lamp, has been disclosed. The solid-state image sensor comprises: plural pixels and; a gain variable amplifier that amplifies signals sequentially read from the plural pixels at a fixed cycle time and the amplification factor of which can be varied, and the storage time of the pixel can be set to an arbitrary value, wherein the sensor comprises: a brightness/illumination flicker detection section; and a control section that varies the storage time step by step to one of plural flicker-less times in accordance with the detected brightness and the illumination flicker as well as varying the amplification factor of the amplifier in accordance with the detected brightness and the storage time.

Abstract: Semiconductor structure and method of fabricating a semiconductor structure are provided that include a substrate having a first in-plane unstrained lattice constant, a first layer comprising a first semiconductor material on the substrate and having a second in-plane unstrained lattice constant that is different from the first in-plane unstrained lattice constant and a variable mismatch layer comprising a second semiconductor material disposed between the substrate and the first layer. The variable mismatch layer is configured to reduce stress in the first layer to below a level of stress resulting from growth of the first layer directly on the substrate. The variable mismatch layer may be a layer having a strained in-plane lattice constant that substantially matches the unstrained lattice constant of the first layer.

Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.

Abstract: The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich lattice mismatched layer grown on top of the substrate having a different lattice constant, which does not contain any processing steps before of after the lattice-mismatched layer growth. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched layer in no strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions.

Abstract: A substrate including a base substrate, an interfacial bonding layer disposed on the base substrate, and a thin film adaptive crystalline layer disposed on the interfacial bonding layer. The interfacial bonding layer is solid at room temperature, and is in liquid-like form when heated to a temperature above room temperature. The interfacial bonding layer may be heated during epitaxial growth of a target material system grown on the thin film layer to provide the thin film layer with lattice flexibility to adapt to the different lattice constant of the target material system.

Abstract: A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

Abstract: First and second well layers of a light emitting device emit light of different peak wavelengths so as to produce a mixed light, such as white light having high luminous intensity and high luminous efficiency. A color rendering property of the device can be controlled by adjusting the ratio of the growth numbers of the first and second well layers, and/or the thickness of the barrier layers sandwiching the well layers. The color rendering property can also be controlled by forming the second well layer so as to have a degree of asperity greater than that of the first well layer, or so that a degree of area occupied by dished portions having a thickness which is less than half of an average thickness over a total surface is not less than 10%.

Abstract: A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.

Abstract: Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: A method for growing strain-engineered, self-assembled, semiconductor quantum dots (QDs) into ordered lattices. The nucleation and positioning of QDs into lattices is achieved using a periodic sub-surface lattice built-up on a substrate, stressor layer, and spacer layer. The unit cell dimensions, orientation and the number of QDs in the basis are tunable. Moreover, a 2D lattice can be replicated at periodic intervals along the growth direction to form a three-dimensional (3D) lattice of QDs.

Abstract: A semiconductor device includes group III-V layers formed over a substrate. At least one of the group III-V layers is doped with a dopant. The dopant includes a first dopant and one of a second dopant and an isovalent impurity. The first dopant has a covalent radius different in size than the covalent radii of each of the second dopant and the isovalent impurity.

Abstract: A nitride semiconductor light-emitting device has an active layer of a single-quantum well structure or multi-quantum well made of a nitride semiconductor containing indium and gallium. A first p-type clad layer made of a p-type nitride semiconductor containing aluminum and gallium is provided in contact with one surface of the active layer. A second p-type clad layer made of a p-type nitride semiconductor containing aluminum and gallium is provided on the first p-type clad layer. The second p-type clad layer has a larger band gap than that of the first p-type clad layer. An n-type semiconductor layer is provided in contact with the other surface of the active layer.

Abstract: A single electron tunneling transistor which has a multi-layer structure exhibiting a single electron tunneling effect even with processing accuracy of not greater than 0.1 &mgr;m. The multi-layer structure of the single electron tunneling transistor is characterized by alternately growing an electrically conductive layer and a tunneling barrier layer. The number of layers is 50 or more. The structure has a minute tunneling junction having an area on the order of 1 &mgr;m square.

Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.

Abstract: A quantum semiconductor device includes intermediate layers of a first semiconductor crystal having a first lattice constant and stacked repeatedly, and a plurality of quantum dots of a second semiconductor crystal having a second lattice constant different from the first lattice constant. The quantum dots are dispersed in each of the intermediate layers and form a strained heteroepitaxial system with respect to the corresponding intermediate layer. Each of the quantum dots has a height substantially identical with a thickness of the corresponding intermediate layer.

Abstract: An optical semiconductor device having a plurality of GaN-based semiconductor layers containing a strained quantum well layer in which the strained quantum well layer has a piezoelectric field that depends on the orientation of the strained quantum well layer when the quantum layer is grown. In the present invention, the strained quantum well layer is grown with an orientation at which the piezoelectric field is less than the maximum value of the piezoelectric field strength as a function of the orientation. In devices having GaN-based semiconductor layers with a wurtzite crystal structure, the growth orientation of the strained quantum well layer is tilted at least 1° from the {0001} direction of the wurtzite crystal structure. In devices having GaN-based semiconductor layers with a zincblende crystal structure, the growth orientation of the strained quantum well layer is tilted at least 1° from the {111} direction of the zincblende crystal structure.

Abstract: In the manufacture of a semiconductor laser device, sequentially grown on a sapphire substrate in the following order are a buffer layer, a first undoped GaN layer, a first super lattice defect reducing layer, a second undoped GaN layer, a second super lattice defect reducing layer, a third undoped GaN layer, a third super lattice defect reducing layer and a fourth undoped GaN layer. A device structure is then formed thereon. The first to third super lattice defect reducing layers each include five pairs of InGaN and AlGaN films alternately placed on one another in this order.

Abstract: An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.

Abstract: A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or buried channel MOSFETS. In another exemplary embodiment, the FETs are interconnected to form an inverter.

Abstract: A semiconductor optical amplifier includes a plurality of active layers of bulk crystal with at least one intervening spacer for optical amplification, wherein each of the active layers accumulates a tensile strain therein.

Abstract: A method and device for converting light from a first wavelength to a second wavelength. The method comprises the steps of exciting an electron in a quantum dot with an incident infrared photon having the first wavelength, the excited electron having a first energy, tunneling the excited electron through a barrier into a stress induced quantum dot, and recombining the excited electron with a hole in the stress induced quantum dot, therein producing a photon having the second wavelength, typically in the visible range.

Abstract: A semiconductor substrate, a field effect transistor, a method of forming a SiGe layer and a method of forming a strained Si layer using the same, and a method of manufacturing a field effect transistor are provided, which enable the threading dislocation density of the SiGe layer to be reduced and the surface roughness to be minimized. On top of a Si substrate 1 is provided a SiGe buffer layer 2, 12 constructed of a plurality of laminated layers comprising alternating layers of a SiGe gradient composition layer 2a, 12a in which the Ge composition ratio increases gradually from the Ge composition ratio of the base material, and a SiGe constant composition layer 2b, 12b which is provided on top of the gradient composition layer and in which the Ge composition ratio is equal to that of the upper surface of the gradient composition layer.

Abstract: A light emitting diode with strained layer superlatices (SLS) crystal structure is formed on a substrate. A nucleation layer and a buffer layer are sequentially formed on the substrate, so as to ease the crystal growth for the subsequent crystal growing process. An active layer is covered between an upper and a lower cladding layers. The active later include III-N group compound semiconductive material. A SLS contact layer is located on the upper cladding layer. A transparent electrode is located on the contact later to serve as an anode. Another electrode layer has contact with the buffer layer, and is separated from the lower and upper cladding layers.

Abstract: A nitride compound semiconductor element having improved characteristics, productivity and yield. A nitride compound semiconductor element comprises: a sapphire substrate; a first single crystalline layer of AIN formed on said sapphire substrate; a second single crystalline layer formed on said first single crystalline layer, said second single crystalline layer being made of AlxGal1-xN(0.8≦x≦0.97) and having a thickness of equal to or more than 0.3 &mgr;m and equal to or less than 6 &mgr;m; and a device structure section of a nitride semiconductor formed on said second single crystalline layer.

Abstract: An integrated circuit device comprises an insulation layer formed on a substrate, a plurality of lattice relaxed SiGe layers each formed in an island form on the insulation layer, wherein a maximum size of the island form thereof is 10 &mgr;m or less, one of a strained Si layer, a strained SiGe layer and a strained Ge layer formed on at least one of the plurality of lattice relaxed SiGe layers, and a field effect transistor having a gate electrode and source and drain regions, wherein the gate electrode is formed on one of the strained Si layer, the strained SiGe layer and the strained Ge layer with a gate insulation film is disposed therebetween, and the source and drain regions is formed to sandwich a channel region formed below the gate electrode with the gate insulation film disposed therebetween.

Abstract: Presented is an LED device that produces white light by performing phosphor conversion on substantially all of the primary light emitted by the light emitting structure of the LED device. The LED device comprises a light emitting structure and at least one phosphor-converting element located to receive and absorb substantially all of the primary light. The phosphor-converting element emits secondary light at second and third wavelengths that combine to produce white light. Some embodiments include an additional phosphor-converting element, which receives light from a phosphor-converting element and emits light at a fourth wavelength. In the embodiments including an additional phosphor-converting element, the second, third, and fourth wavelengths combine to produce white light. Each phosphor-converting element includes at least one host material doped with at least one dopant. The phosphor-converting element may be a phosphor thin film, a substrate for the light emitting structure, or a phosphor powder layer.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers (22) by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (24) on a silicon wafer (22). The accommodating buffer layer (24) is a layer of monocrystalline oxide spaced apart from the silicon wafer (22) by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer.

Abstract: A heat dissipating element (e.g., a heat sink) is held in an initial position closer to a heat generating structure (e.g., a microprocessor) and in a subsequent position farther from the microprocessor. A thermal interface material (e.g., a thermal grease) spans the gap, but is not held under compression, between the heat sink and the microprocessor.

Abstract: A gallium nitride group compound semiconductor photodetector includes a substrate and a multilayer structure provided on the substrate. The multilayer structure includes an n-type gallium nitride group compound semiconductor layer, a p-type gallium nitride group compound semiconductor layer, and a light detecting layer provided between the n-type gallium nitride group compound semiconductor layer and the p-type gallium nitride group compound semiconductor layer. The light detecting layer has a quantum well structure includes a quantum well layer of InxGa1−xN (0<x<1) and a barrier layer of InyGa1−y−zAlzN (0≦y<1, 0≦z≦1, y+z<1).

Abstract: An (Al,Ga,In)P semiconductor laser device has an optical region disposed between n-type and p-type cladding layers. An active region containing quantum well active layers and barrier layers disposed alternately with the quantum well layers is provided within the optical guiding region. Strained layers of InxGal−xP are used as the barrier layers. The active region is thus aluminium-free, and this reduces the oxygen impurity concentration in the active region thereby improving the performance and reliability of the laser. An aluminium-free spacer layer can be provided between one of the cladding layers and the quantum well active layer disposed closest to that cladding layer. The invention may be applied to other semiconductor devices, for example such as an LED.

Abstract: An intersubband light emitting element includes a semiconducting substrate, a first layer composed of a first semiconducting material, and a second layer composed of second semiconducting material. The first layer makes a heterojunction with the second layer. The top of a valence band of the first semiconducting material is higher in energy than the bottom of a conduction band of the second semiconducting material. The element further includes a third layer making a heterojunction with the first or second layer. The third layer has a superlattice structure. One of the first and second layer is provided on the semiconducting substrate directly or through at least one semiconducting layer.

Abstract: The present invention discloses a device and a method for producing an oxidizable digital alloy that is sufficiently strain-compensated to provide for substantially defect-free growth on indium phosphide. The device comprises a layer of semiconductor material, a first layer, and a second layer. The first layer is indium arsenide and is coupled to the layer of semiconductor material, wherein the first layer of indium arsenide is under a compressive strain by a lattice mismatch between the layer of semiconductor material and the first layer of indium arsenide. The second layer is aluminum arsenide and is coupled to the layer of indium arsenide, wherein the second layer of aluminum arsenide is under a tensile strain by a lattice mismatch between the second layer and the first layer. The first layer and the second layer comprise a digital alloy of aluminum indium arsenide, and create a quasi-strain-compensated substantially defect-free alloy on the layer of semiconductor material therein.

Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: Nitrogen-containing III-V alloy semiconductor materials have both a conduction band offset &Dgr;Ec and a valence band offset &Dgr;Ev large enough for the practical applications to light emitting devices. The semiconductor materials are capable of providing laser diodes, having excellent temperature characteristics with emission wavelengths in the red spectral region and of 600 nm or smaller, and high brightness light emitting diodes with emission wavelengths in the visible spectral region. The light emitting device is fabricated on an n-GaAs substrate, which has the direction normal to the substrate surface is misoriented by 15° from the direction normal to the (100) plane toward the [011] direction. On the substrate, there disposed by MOCVD, for example, are an n-GaAs buffer layer, an n-(Al0.7Ga0.3)0.51In0.49P cladding layer, an (Al0.2Ga0.8)0.49In0.51N0.01P0.99 active layer, a p-(Al0.7Ga0.3)0.51In0.49P cladding layer, and a p-GaAs contact layer.

Abstract: A semiconductor photonic device includes a substrate having a cleavage plane perpendicular to a principal plane thereof; a ZnO film on the substrate; and a compound semiconductor layer expressed by InxGayAlzN (x+y+z=1, 0≦x≦1, 0≦y ≦1, 0≦z≦1).

Abstract: A semiconductor device includes a quantum well lamination structure having at least one quantum well layer and at least two barrier layers alternately laminated, the quantum well layer forming a quantum well relative to electron and hole and the barrier layer forming a potential barrier relative to electron and hole. The height of the quantum well layer and the height of the potential barrier of a valence band at the interface between the quantum well layer and the barrier layer are set so that the number of quantum levels relative to hole on the valence band side of the quantum well layer is two or three in the state that the intensity of an electric field generated in the quantum well layer is zero. The semiconductor device is provided with a means for applying an electric field in the quantum well lamination structure in a thickness direction.

Abstract: A semiconductor device includes a compound semiconductor substrate having a resistivity less than 1.0×108 Ohm-cm at least at one surface thereof, a buffer layer formed on the compound semiconductor substrate and having a super lattice structure, and an active layer formed on the buffer layer and having an active element formed therein.

Abstract: The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly.

Abstract: An undoped Ge sacrificial layer with an uneven surface (about 1 nm), a relaxed undoped Si0.7Ge0.3 buffer layer (50 nm), an n-type Si0.7Ge0.3 carrier supply layer, an undoped Si0.7Ge0.3 spacer layer, an undoped strained Si channel layer (10 nm), an undoped Si0.7Ge0.3 cap layer (20 nm), and an undoped strained Si cap layer (2 nm) are sequentially stacked on a p-type Si substrate. Therefore, a buffer layer can be made thin and of low dislocation density since a semiconductor device has a strained semiconductor layer applied with a tensile strain or a compressive strain.

Abstract: A ridge laser that includes a Group III-V semiconductor material substrate; a first selectively oxidized at least one strain-compensated superlattice of Group III-V semiconductor material; a multiple quantum well active region; a second selectively oxidized at least one strain-compensated superlattice of Group III-V semiconductor material; a Group III-V semiconductor material cap layer; and a contact material. Each at least one strain-compensated superlattice includes at least two monolayers of a Group III-V semiconductor material and at least two monolayers of an aluminum-bearing Group III-V semiconductor material.