Abstract: A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source/drain regions and a stress film formed so as to cover the gate electrode portion and the source/drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source/drain regions.

Abstract: An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.

Abstract: Using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise having a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.

Abstract: A semiconductor device includes a semiconductor layer, and a first transistor and a second transistor that are formed using the semiconductor layer, wherein each conductance of the first and second transistors changes complementarily to each other according to a curvature of the semiconductor layer.

Abstract: A semiconductor device includes a first well region 3a; a second well region 3b; a first active region 21a surrounded by an isolation region 2; a second active region 21b surrounded by the isolation regions 2 and 2B; a first MIS transistor MP2 of a second conductivity type formed on the first active region 21a; and including a source/drain region formed of a Si mixed crystal layer buried in a recess; a second MIS transistor MN2 of a first conductivity type formed on the second active region 21b; and an isolation MIS transistor DP2 of the second conductivity type formed on the first active region 21a. The source/drain region of the first MIS transistor is not in contact with the isolation region 2 located at an end of the first active region 21a in a gate length direction.

Abstract: A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern extends in the first direction across the first conductive type active region and second conductive type active region. A first contact region is adjacent the first end of the first conductive type active region in the first direction. A second contact region is adjacent the second end of the second conductive type active region in the first direction.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract: There is provided an engineering change order (ECO) cell, which includes: a function circuit including at least one PMOS transistor with a P-diffusion layer and a first poly gate, at least one NMOS transistor with an N-diffusion layer and a second poly gate; a first power layer supplying the at least one PMOS transistor with a first power voltage; and a second power layer supplying the at least one NMOS transistor with a second power voltage. The first poly gate of the PMOS transistor is isolated from the second poly gate of the NMOS transistor.

Abstract: A semiconductor device in accordance with an exemplary aspect of the present invention includes: an even number of transistor pairs; connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and inter-gate wiring lines connected to the connection nodes, each inter-gate wiring line connecting a gate of the p-type transistor of one of the transistor pairs disposed in the subsequent stage of one of the transistor pairs for which each connection node is provided, wherein the n-type transistor of a first transistor pair is disposed in a p-well region different from both a p-well region in which the n-type transistor of a second transistor pair disposed in two stages preceding of the first transistor pair is disposed and a p-well region in which the n-type transistor of a third transistor pair disposed in two stages subsequent of the first transistor pair is disposed.

Abstract: A CMOS image sensor includes a photodiode, and a plurality of transistors for transferring charges accumulated at the photodiode to one column line, wherein at least one transistor among the plurality of transistors has a source region wider than a drain region, for increasing a driving current.

Abstract: A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose a region under the first gate electrode in a direction of gate length. The first gate electrode includes: a first silicide film formed on the first gate insulating film and containing nickel silicide having a first composition ratio of nickel to silicon as a main component; a conductive film formed on the first silicide film; and a second silicide film formed on the conductive film and containing nickel silicide having a second composition ratio of nickel to silicon as a main component. The second composition ratio is larger than the first composition ratio.

Abstract: A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell has: a p-type MOS transistor having first diffused regions and a first gate electrode; an n-type MOS transistor having second diffused regions and a second gate electrode with STI disposed for device isolation between the n-type MOS transistor and the p-type MOS transistor substantially in parallel with the first borderlines; dummy p-type MOS transistors having third gate electrodes disposed on the second borderlines so as to be adjacent to the first diffused regions of the p-type MOS transistor, the third gate electrodes being connected to power supply wiring so as to turn off the dummy p-type MOS transistors; and dummy n-type MOS transistors having fourth gate electrodes disposed on the second borderlines so

Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.

Abstract: A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front gate region formed on a gate insulating film formed on one of side surfaces of the semiconductor region such that the source region and the drain region are separated from each other by the front gate region, and a back gate region formed on a gate insulating film formed on an opposite side surface of the semiconductor region such that the source region and the drain region are separated from each other by the back gate region. Each memory cell shares the back gate region with a memory cell adjacent in a row direction.

Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.

Abstract: On a semiconductor substrate, a gate electrode is disposed obliquely across the boundary between an N-type region and a P-type region, and thereby an effective gate width of a region, in which the boundary between the N-type region and the P-type region intersects with the gate electrode, is wider than that of the gate electrode. Accordingly, the occurrence of abnormal resistance, which makes it difficult for an electric current to flow in the gate electrode on the boundary between the N-type region and the P-type region, may be effectively suppressed without physically widening the gate width. Moreover, widening of the gate width of the gate electrode may be eliminated in suppressing the occurrence of abnormal resistance and it is not necessary to enlarge the areas of the N-type region and the P-type region, thereby inevitable enlargement of the overall size of the semiconductor device being avoided.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a substantially equal and minimum size across the gate electrode level region. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. The cell includes an equal number of PMOS and NMOS transistor devices. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features within the gate electrode level region extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device.

Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features within the gate electrode level region extend over the p-type diffusion regions to form respective PMOS transistor devices. Also, some of the conductive features within the gate electrode level region extend over the n-type diffusion regions to form respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.

Abstract: This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures are disclosed that use alignment-independent processing steps. One of these processes uses one, low-accuracy imprinting step and further alignment-independent processing steps.

Abstract: A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor.

Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.

Abstract: A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a control voltage is applied and which has a plurality of fingers. The low finger NMOS transistor has a first terminal connected to a low power source, a gate to which the control voltage is applied and which has a plurality of fingers, and a second terminal connected to a second terminal of the PMOS transistor. The number of the fingers of the gate of the NMOS transistor is smaller than the number of fingers of the gate of the PMOS transistor and the length of each of the fingers of the NMOS transistor is greater than the length of each of the fingers of the PMOS transistor.

Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.

Abstract: SRAM devices and methods of fabricating the same are disclosed, by which a process margin and a degree of device integration are enhanced by reducing the number of contact holes of an SRAM device unit cell using local interconnections. A disclosed example device includes first and second load elements; first and second drive transistors; a common gate electrode connected in one body to a gate electrode of the first load element and a gate electrode of the first drive transistor to apply a sync signal to the gate electrodes; the common gate electrode overlapping with a junction layer of the second load element and a junction layer region of the second drive transistor; the common gate electrode being electrically connected to an upper line via a plug in one contact hole.

Abstract: A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating film (partial separation insulating film), and a contact portion. Here, the active region is formed within the surface of the SOI layer. In addition, the first insulating film is formed on one side of the active region from the surface of SOI layer to the buried insulating film. In addition, the second insulating film is formed on the other side of the active region from the surface of SOI layer to a predetermined depth that does not reach the buried insulating film. In addition, the contact portion is provided toward the side where the first insulating film exists, off the center of the active region in a plan view.

Abstract: A semiconductor device includes a first transistor unit including first field effect transistors with first gate electrodes electrically connected together, first sources electrically connected together, and first drains electrically connected together, the first gate electrodes being electrically connected to the first drains, a second transistor unit including second field effect transistors with second gate electrodes electrically connected together, second sources electrically connected together, and second drains electrically connected together, the second gate electrodes being electrically connected to the first gate electrodes, and dummy gate electrodes electrically isolated from the first gate electrodes and the second gate electrodes. The first gate electrodes, the second gate electrodes, and the dummy gate electrodes are arranged parallel to one another, and at least one dummy gate electrode is located between any one of the first gate electrodes and any one of the second gate electrodes.

Abstract: A semiconductor device that can prevent an unnecessary current path from being formed so that a normal signal is transmitted is provided. The semiconductor device comprises an N? region formed in a surface region of a P type substrate, a P region formed in the surface region, the P region included in the N? region or adjacent to the N? region, one or more semiconductor elements each of which has a first N type region and a second N type region formed in a portion of the P region, the first N type region and the second N type region being separated from each other, a first electrode formed on the first N type region, a second electrode formed on the second N type region, and a gate electrode formed over a surface of the P region between the first N type region and the second N type region. The first N type region and the second N type region are surrounded by the P region and separated from the N? region.

Abstract: A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate and is electrically coupled to the bond pad. The bond pad structure further includes a first passivation layer over the first dielectric layer wherein the first passivation layer has at least a portion under a middle portion of the bond pad. At least part of an active circuit is located under the bond pad.

Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: In automatic placing and routing, a standard cell 101 is composed of a P-channel transistor region 102 and an N-channel transistor region 103. The P-channel transistor region 102 has a P-channel functional transistor forming region 104, and the N-channel transistor region 103 has an N-channel functional transistor forming region 105. In a space region of the N-channel transistor region 103 other than the N-channel functional transistor forming region 105, a power source capacitor forming region 106 is formed at a portion of the P-channel transistor region 102 opposing the P-channel functional transistor forming region 104. In this region, a power source capacitor is formed to suppress the IR-Drop of a power source wiring line.

Abstract: A semiconductor device includes a plurality of PMOS transistors formed on a semiconductor substrate; and a plurality of NMOS transistors formed on the semiconductor substrate. The plurality of PMOS transistors are electrically isolated from each other by a device isolation structure formed in the semiconductor substrate. The plurality of NMOS transistors are continuously formed in a first direction such that a sequence of N-type diffusion layers of the plurality of NMOS transistors extends in the first direction. One of the plurality of PMOS transistors and one of the plurality of NMOS transistors share a gate electrode.

Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

Abstract: In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

Abstract: In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

Abstract: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.