Abstract: A solid-state imaging apparatus, controlling a potential on a semiconductor substrate for an electronic shutter operation, includes: a first semiconductor region of the first conductivity type for forming a photoelectric conversion region; a second semiconductor region of the first conductivity type, formed separately from the photoelectric conversion region, for accumulating carriers; a third semiconductor region of a second conductivity type arranged under the second semiconductor region, for operating as a potential barrier; a fourth semiconductor region of the second conductivity type extending between the first semiconductor region and the semiconductor substrate, and between the third semiconductor region and the semiconductor substrate; and a first voltage supply portion for supplying a voltage to the third semiconductor region; wherein the first voltage supply portion includes a fifth semiconductor region of the second conductivity type arranged in the pixel region, and a first electrode connected to

Abstract: A part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first transfer gate electrode functions as a first transfer channel, and the surface buried region directly under a second transfer gate electrode functions as a second transfer channel. Signal charges are alternately transferred to an n-type first floating drain region and a second floating drain region through the first and second floating transfer channels.

Abstract: In a solid-state image pickup device, it is difficult to match an optimum incidence angle corresponding to an image height of a pixel array region with light incidence characteristics of a camera lens, thereby causing image quality deterioration due to sensitivity shading. Respective microlenses are disposed in a two-dimensional manner, i.e., in a row and a column directions. In particular, the microlenses are disposed such that each side of a disposition region where the microlenses are disposed has a concave curve with respect to a line connecting adjacent vertexes of the disposition region. In other words, a distance AH (AV) between center points of a pair of facing sides of the disposition region is set to be smaller than a distance BH (BV) between neighboring vertexes of the disposition region.

Abstract: It is a principle object of the present invention to reduce a voltage drop of a common power supply wiring in a plurality of amplification circuits to suppress crosstalk generated in other signal output lines.

Abstract: A lateral power semiconductor device has a substrate and an isolation layer formed over the substrate for reducing minority carrier storage in the substrate. A well region is formed over the isolation layer. A source region, drain region, and channel region are formed in the well. A first region is formed on a surface of the lateral power semiconductor device adjacent to the source region. The lateral power semiconductor device has a body diode between the first region and drain region. The isolation layer confines the minority carrier charge from the body diode to a depth of less than 20 ?m from the surface of the lateral power semiconductor device. In one embodiment, the isolation layer is a buried oxide layer and the substrate is an n-type or p-type handle wafer. Alternatively, the isolation layer is an epitaxial layer and the substrate is made with N+ or P+ semiconductor material.

Abstract: Disclosed herein is a solid-state image pickup device, including, a light receiving pixel section, a black level reference pixel section, a multi-layer wiring line section, a first light blocking film, a second light blocking film, a third light blocking film, and a fourth light blocking layer.

Abstract: A solid-state imaging device includes a semiconductor substrate and a plurality of photoelectric conversion elements provided in the semiconductor substrate, wherein the plurality of photoelectric conversion elements include: effective photoelectric conversion elements which are photoelectric conversion elements for obtaining an imaging signal corresponding to light from a subject; and OB photoelectric conversion elements which are photoelectric conversion elements for obtaining a reference signal of an optical black level, and the solid-state imaging device further includes a first shielding layer provided at least over the effective pixel area as defined herein and having an opening provided at least over a part of the effective photoelectric conversion elements, and a second shielding layer provided over the OB pixel area as defined herein and electrically separated from the first shielding layer.

Abstract: In a solid state image pickup apparatus with a photodetecting device and one or more thin film transistors connected to the photodetecting device formed in one pixel, a part of the photodetecting device is formed over at least a part of the thin film transistor, and the thin film transistor is constructed by a source electrode, a drain electrode, a first gate electrode, and a second gate electrode arranged on the side opposite to the first gate electrode with respect to the source electrode and the drain electrode, and the first gate electrode is connected to the second gate electrode every pixel, thereby, suppressing an adverse effect of the photodetecting device on the TFT, a leakage at turn-off TFT, variation in a threshold voltage of the TFT due to an external electric field, and accurately transferring photo carrier to a signal processing circuit.

Abstract: The object of the invention is to provide a semiconductor device that can form photodiodes that do not short circuit, without damage that causes leakage, despite formation of the opening part, and its manufacturing method. The second semiconductor layer (12, 16) of the second conductivity type is formed on the main surface of the first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) formed at least on the second semiconductor layer separate the device into the regions of plural photodiodes (PD1-PD4). Conductive layer 18 is formed on the second semiconductor layer 16 in a pattern that is divided for each of the photodiodes and is connected to the second semiconductor layer 16 along the outer periphery with respect to all of the plural photodiodes. Insulation layer (19, 21) is formed on the entire surface to cover conductive layer 18.

Abstract: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination.

Abstract: A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer.

Abstract: A layout for placing a circuit having a plurality of transistors in a small-width region. A search section inputs data on a circuit and searches for a set of routes formed so that passage through a transistor occurs only one time and so that the combination of routes covers the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes. A width determination section determines the layout width from source and drain electrodes, the region between the source and drain electrodes, the region between adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms a layout in which the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region.

Abstract: An image sensor includes a reset transistor, reset gate electrodes and a potential shift circuit. The reset transistor includes a reset gate and a reset drain, and resets charges detected by a charge detection device. The reset gate electrodes control a potential of the reset gate. The potential shift circuit initializes output signals in response to a shift pulse, and outputs the output signals to the reset gate electrodes in response to a reset pulse.

Abstract: A solid-state image pickup device includes a semiconductor substrate including a substrate main body having P-type impurities and a first N-type semiconductor layer provided on the substrate main body, an image pickup area including a plurality of photoelectric converters in which the plurality of photoelectric converters include second N-type semiconductor layers, the second N-type semiconductor layers being provided on a surface portion of the first N-type semiconductor layer independently of one another, and a first peripheral circuit area including a first P-type semiconductor layer formed on the first N-type semiconductor layer. The solid-state image pickup device further includes a second peripheral circuit area including a second P-type semiconductor layer formed on the first N-type semiconductor layer and connected to the substrate main body.

Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion units configured to generate signal charge from light received at light-receiving surfaces thereof, the plurality of photoelectric conversion units being provided in the image-sensing area of a substrate; a charge reading unit configured to read signal charge generated by the photoelectric conversion units, a charge readout channel area thereof being provided in the image-sensing area of the substrate; a transfer register unit configured to transfer signal charge read from the plurality of photoelectric conversion units by the charge reading unit, a charge transfer channel area thereof being provided in the image-sensing area of the substrate; and a light-shielding unit that is provided in the image-sensing area of the substrate and that has an opening through which light is transmitted formed in an area corresponding to a light-receiving surface of a respective photoelectric conversion unit.

Abstract: A demodulation pixel architecture allows for demodulating an incoming modulated electromagnetic wave, normally visible or infrared light. It is based on a charge coupled device (CCD) line connected to a drift field structure. The drift field is exposed to the incoming light. It collects the generated charge and forces it to move to the pick-up point. At this pick-up point, the CCD element samples the charge for a given time and then shifts the charge packets further on in the daisy chain. After a certain amount of shifts, the multiple charge packets are stored in so-called integration gates, in a preferred embodiment. The number of integration gates gives the number of simultaneously available taps. When the cycle is repeated several times, the charge is accumulated in the integration gates and thus the signal-to-noise ratio increases. The architecture is flexible in the number of taps. A dump node can be attached to the CCD line for dumping charge with the same speed as the samples are taken.

Abstract: A pixel of a complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of photodiodes for sensing light to thereby generate photoelectric charges in different regions; a plurality of transfer transistors for transferring photoelectric charges of corresponding photodiodes in response to a first control signal; a floating diffusion region for receiving photoelectric charges transferred by the plurality of transfer transistors; a rest transistor connected between a power supply voltage and the floating diffusion region for resetting the floating diffusion region by controlling a voltage loaded on the floating diffusion region in response to a second control signal; a drive transistor connected between the power supply voltage and the floating diffusion region to serve as a source follower buffer amplifier; and a select transistor connected between the drive transistor and a pixel output terminal for performing an addressing operation in response to a third control signal.

Abstract: An object of the present invention is to prevent a sensitivity difference between pixels. There are disposed plural unit cells each including plural photodiodes 101A and 101B, plural transfer MOSFETs 102A and 102B arranged corresponding to the plural photodiodes, respectively, and a common MOSFET 104 which amplifies and outputs signals read from the plural photodiodes. Each pair within the unit cell, composed of the photodiode and the transfer MOSFET provided corresponding to the photodiode, has translational symmetry with respect to one another. Within the unit cell, there are included a reset MOSFET and selecting MOSFET.

Abstract: A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio of the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. Also disclosed are methods for forming the retrograde well.

Abstract: Provided are a doping mask and methods of manufacturing a charge transfer image device and a microelectronic device using the same. The method includes forming a photoresist film on an entire surface of a substrate or sub-substrate having a peripheral circuit region and a pixel region, removing the photoresist film on an upper surface of the substrate intended for the peripheral circuit region and patterning the photoresist film on an upper surface of the substrate intended for the pixel region to form a photoresist pattern having an array of openings with a predetermined pitch, implanting ions at the same concentration level into the entire surface of the substrate using the photoresist pattern as a doping mask, and diffusing the implanted ions by annealing. The pitch is determined so that ions implanted through each opening diffuse toward those implanted through an adjacent one to form wells.

Abstract: In a case when a structure of forming a p+ layer on a substrate rear surface side is employed in order to prevent dark current generation from the silicon boundary surface, various problems occur. According to this invention, an insulation film 39 is provided on a rear surface on a silicon substrate 31 and a transparent electrode 40 is further provided thereon, and by applying a negative voltage with respect to the potential of the silicon substrate 31 from a voltage supply source 41 to the insulation film 39 through the transparent electrode 40, positive holes are accumulated on a silicon boundary surface of the substrate rear surface side and a structure equivalent to a state in which a positive hole accumulation layer exists on aforesaid silicon boundary surface is to be created. Thus, various problems in the related art can be avoided.

Abstract: A solid-state imaging device includes: a semiconductor substrate; photoelectric conversion elements; vertical charge transfer paths that transfer charges generated in photoelectric conversion elements, in a vertical direction; a horizontal charge transfer path that transfers the charges transferred in vertical charge transfer paths, in a horizontal direction orthogonal to the vertical direction; a plurality of charge accumulating sections between the vertical charge transfer paths and the horizontal charge transfer path; a plurality of electrodes disposed above the respective charge accumulating sections, the plurality of electrodes being classified into a plurality of kinds of electrodes; wirings corresponding to the respective kinds of electrodes and extending in the horizontal direction above the plurality of electrodes; and a planarizing layer disposed between the wirings and an uneven surface caused by the plurality of electrodes that are present in areas overlapping the wirings, so as to planarize the u

Abstract: A solid-state imaging device includes a semiconductor substrate and a plurality of photoelectric conversion elements provided in the semiconductor substrate, wherein the plurality of photoelectric conversion elements include: effective photoelectric conversion elements which are photoelectric conversion elements for obtaining an imaging signal corresponding to light from a subject; and OB photoelectric conversion elements which are photoelectric conversion elements for obtaining a reference signal of an optical black level, and the solid-state imaging device further includes a first shielding layer provided at least over the effective pixel area as defined herein and having an opening provided at least over a part of the effective photoelectric conversion elements, and a second shielding layer provided over the OB pixel area as defined herein and electrically separated from the first shielding layer.

Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21<channel 22<channel 23, 25 A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.

Abstract: It is an object of the present invention to provide a solid-state imaging device that can achieve a high sensitivity, finer pixels for increasing the number of pixels, a high-speed operation, and high image quality, and a method for manufacturing the same. There are provided a plurality of photoelectric conversion portions arranged in a matrix on a substrate, a vertical transfer channel arranged between vertical columns of the photoelectric conversion portions, a plurality of vertical transfer electrodes for transferring a charge of the photoelectric conversion portions to the vertical transfer channel, a light-shielding film that is laminated on the vertical transfer electrodes via a first insulating film and has a plurality of window portions, each defining a light-receiving portion of each of the photoelectric conversion portions, and a shunt wiring that is arranged in a region overlapping the vertical transfer channel and is insulated from the light-shielding film by a second insulating film.

Abstract: A semiconductor apparatus has a substrate to which is attached a thin semiconductor film including at least one semiconductor device. An interconnecting line links the semiconductor film with electrical circuitry on the substrate. The interconnecting line includes a pad located on the substrate, between the thin semiconductor film and the electrical circuitry. The pad, which is wider than other parts of the interconnecting line, can be used as a probe pad for testing the apparatus, and in particular for testing the electrical circuitry on the substrate before the thin semiconductor film is attached.

Abstract: A method of manufacturing a solid image pick-up device comprising a photoelectronic conversion portion, a charge transfer portion and a peripheral circuit portion, the method comprising: forming a pattern comprising a first layer silicon conductive film to a surface of a semiconductor, the first layer silicon conductive film forming: a first electrode; and a first layer interconnection for the photoconductive conversion portion and the peripheral circuit portion; forming an insulative film at least to a side wall of the first electrode; forming a second silicon conductive film being to form a second electrode to the semiconductor substrate; coating a resist over the semiconductor substrate by a spin coating method; and planarizing the second layer silicon conductive film by a resist etching-back method, wherein the pattern further comprises at least one dummy pattern, and a surface level of the resist is not below a predetermined value over the semiconductor substrate.

Abstract: A device separation insulating film and a device separation semiconductor layer are provided for a device separation section for separating adjacent devices from each other, end portions of the device separation insulating film and end portions of the device separation semiconductor layer are provided to overlap each other in order to surround two sides of an outer-periphery of the voltage conversion section and also to surround a channel section of the charge transfer device and the light receiving devices and an end portion of the device separation insulating film facing an end face of the light receiving device is arranged inwardly below a control electrode with respect to an end face of the control electrode on the light receiving device side.

Abstract: A solid-state image pickup element equipped with a film stack, a color filter, and a microlens on a semiconductor substrate equipped with a light receiving section, comprises a first film with a high refractive index and a second film with a low refractive index adjacently arranged on the semiconductor substrate in this order viewing from the semiconductor substrate side, each of which has at least one layer respectively. Thereby it makes possible to reduce the loss of incident light, and to achieve the enhancement in photoelectric conversion efficiency.

Abstract: A charge transfer device includes a charge transfer unit transferring signal charges, and an electric charge-voltage conversion unit detecting signal charges transferred from a last stage of the charge transfer unit via an output gate unit. An electrode in a last stage of the charge transfer unit is divided into first and second electrodes. A predetermined fixed potential is applied to the first electrode disposed on a side of the electric charge-voltage conversion unit. A transfer clock is applied to the second electrode disposed on a side opposite to the charge transfer unit.

Abstract: A solid-state image pick-up device of a photoelectric converting film lamination type including a semiconductor substrate and at least three layers of photoelectric converting films each of which is interposed between a common electrode film and pixel electrode films. The pixel electrode films correspond to pixels respectively, and at least three layers of photoelectric converting films are laminated through insulating layers. The at least three layers of photoelectric converting films are above the semiconductor substrate. Sets of the pixel electrode films are provided on each of the at least three layers of photoelectric converting films, and electric charge storage portions formed on the semiconductor substrate are connected through sets of columnar contact electrodes. Resistance values of the sets of columnar contact electrodes are equal to each other.

Abstract: A semiconductor structure, having a doped well region being formed in a substrate layer and a transistor having a terminal provided within said doped well region. The semiconductor structure also includes an oxide layer formed over the substrate layer, the doped well region, a poly silicon region, and the terminal of the transistor. The oxide layer including a step region being located where a height of the oxide layer transitions from a height associated with the doped well region to a height associated with the terminal of the transistor.

Abstract: PROBLEM To provide a high quality solid state image pickup device. SOLUTION Impurities are implanted into a semiconductor substrate to form vertical transfer channels for transferring electric charges in a first direction and to form a drain near each of the vertical transfer channels via a gate which forms a barrier. A first silicon oxide film, a silicon nitride film and a second silicon oxide film are deposited in this order from the bottom, on the surfaces of the vertical transfer channels, gates and drains. A first layer vertical transfer electrode is formed on the second silicon oxide film above the vertical transfer channel, and an insulating film if formed on the surface of the first layer vertical transfer electrode. The second silicon oxide film and silicon nitride film are etched in such a manner that the silicon nitride film covers the vertical transfer channel and extends above the gate excepting a portion near the drain.

Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Abstract: In a charge transfer device which has many two-layered transfer electrodes, 8L disposed along a charge transfer direction X above a transfer channel is driven with two-phase driving pulses supplied to the transfer electrodes of the second layer, the transfer channel below the last-stage transfer electrode disposed at the last stage of the charge transfer direction X is constructed to have three-step potential, and the potential is set to be stepwise deeper from the upstream side to the downstream side in the charge transfer direction X.

Abstract: A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 ?m. At least one dielectric layer is disposed on the substrate covering the pixel. A color filter is disposed on the least one dielectric layer. A microlens array is disposed on the color filter of the pixel, and the sum of the thickness of all dielectric layers and the color filter divided by the pixel width is equal to or less than approximately 1.87.

Abstract: A solid state image pickup device comprising: a semiconductor substrate having a surface layer; charge storage regions disposed in the surface layer; vertical channels disposed in the surface layer adjacent to respective columns of the charge storage regions; vertical transfer electrodes formed above the semiconductor substrate, crossing the vertical channels; a horizontal channel disposed in the surface layer coupled to the vertical channels, having a first portion with transfer stages, each including a barrier region and a well region, and a second portion constituting a gate region with gradually decreasing width, and including an upstream region and a downstream region of different effective impurity concentration, establishing a built-in potential; horizontal transfer electrodes disposed above respective transfer stages of the horizontal channel; an output gate electrode disposed above the gate region; a floating diffusion region disposed in the surface layer coupled to the gate region of the horizontal

Abstract: A solid-state imaging element converts light intensity into an electric charge signal and stores the thus-converted electric charge signal through use of a plurality of photoelectric conversion elements arranged in a square lattice pattern on the surface of a semiconductor substrate in a row direction and a column direction. Vertical transfer sections transfer the electric charges from the first and second photoelectric conversion elements in the column direction. The vertical transfer section comprises a first electric charge reading region for reading electric charge from the first photoelectric conversion element to a vertical transfer channel; and a second electric charge reading region for reading electric charge from the second photoelectric conversion element. The first and second electric charge reading regions are provided at positions corresponding to a vertical transfer electrode, which are activated in difference phases.

Abstract: Provided are a doping mask and methods of manufacturing a charge transfer image device and a microelectronic device using the same. The method includes forming a photoresist film on an entire surface of a substrate or sub-substrate having a peripheral circuit region and a pixel region, removing the photoresist film on an upper surface of the substrate intended for the peripheral circuit region and patterning the photoresist film on an upper surface of the substrate intended for the pixel region to form a photoresist pattern having an array of openings with a predetermined pitch, implanting ions at the same concentration level into the entire surface of the substrate using the photoresist pattern as a doping mask, and diffusing the implanted ions by annealing. The pitch is determined so that ions implanted through each opening diffuse toward those implanted through an adjacent one to form wells.

Abstract: The CCD image sensor addresses the problem of noise, due to background charge generated by Compton scattering of gamma rays. In applications, in which an imager must operate in a high-radiation environment, such background noise reduces the video signal/noise. This imager reduces the amount of charge collected from Compton events, while giving up very little sensitivity to photons in the visible/near IR.

Abstract: A programmable resistance memory element comprising an adhesion layer between the programmable resistance material and at least one of the electrodes. Preferably, the adhesion layer is a titanium rich titanium nitride composition.

Abstract: An image sensor includes a substrate of the first conductivity type; a channel of the first conductivity type that spans at least a portion of the substrate; a well of the second conductivity type that is positioned between the channel and substrate for a predetermined portion and that is not between the substrate and the channel for a predetermined portion all of which well is substantially continuous; and a connection to the well; wherein a resistance of the well not between the substrate and the channel is substantially equal to or greater than twenty five percent of a total resistance of the well between the channel and the substrate.

Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).

Abstract: A solid-state imaging device includes a plurality of vertical charge transferring portions, and a horizontal charge transferring portion connected to at least one end of each of the vertical charge transferring portions.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 ?m2 to about 10 ?m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: The invention relates to a nonvolatile NOR two-transistor semiconductor memory cell, an associated semiconductor memory device and a method for the fabrication thereof, in which one-transistor memory cells are located in an active region formed in annular fashion and are driven via associated word lines. In this case, the source regions of the one-transistor memory cells are connected via a source line, while the drain regions are connected via corresponding drain lines. A reduced space requirement for the two-transistor semiconductor memory cell is obtained in particular on account of the annular structure of the active regions.

Abstract: Large area, fast frame rate, charge coupled devices (CCDs) are provided. Interline transfer CCDs can have interleaved pinned photodiodes and vertical shift registers. The interline transfer CCDs are ideal for producing high frame rate video images from a continuous light source. The photodiodes transfer charge indicative of the previous video frame to an adjacent vertical shift register with little or no lag, while light from the current video frame is integrating in the photodiodes. The charge signals only have to travel a short distance from a photodiode to an adjacent vertical shift register. The charge signals indicative of each video frame are then shifted out of the vertical shift registers. Each vertical shift register has a doping gradient that increases the charge transfer rate. All of these factors provide a fast and efficient video frame rate, even in a large area CCD.

Abstract: Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted.

Abstract: A progressive all-pixel scanning type solid-state image sensor adapted for curtailing the power consumption therein by lowering its read voltage with another advantage of reducing the pixel size. The image sensor comprises pixels arrayed to form a matrix, vertical transfer registers corresponding respectively to individual columns of the pixels, read gates formed correspondingly to the individual pixels for reading out signal charges from the pixels to the vertical transfer registers, and a means for applying phase-shifted read pulses respectively to plural kinds of read gate electrodes in the read gates.

Abstract: The invention relates to very small-sized color image sensors.