Abstract: An active pixel array has the signal output of each pixel connected to a first column conductor, and a reset switch connected to a second column conductor. The first and second column conductors are connected to a read-reset amplifier. The read-reset amplifier operates in a first mode in which a reset voltage is applied to the second column line, and in a second mode in which pixel output signals are buffered from the first column line. The read-reset amplifier can also operate as a comparator forming part of an ADC circuit.

Abstract: Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.

Abstract: A method of fabricating a non-volatile memory is provided. A longitudinal strip of stacked layer is formed over a substrate. The longitudinal strip is a stacked layer including a gate dielectric layer, a conductive layer and a cap layer. A buried bit line is formed in the substrate on each side of the longitudinal strip. The longitudinal strip is patterned to form a plurality of stacked blocks. Thereafter, a dielectric layer is formed over the substrate. The dielectric layer exposes the cap layer of the stacked blocks. Some cap layers of the stacked blocks are removed to expose the conductive layer underneath. A word line is formed over the dielectric layer to connect stacked blocks in the same row serially together.

Abstract: The present invention relates to an image recording device (10), comprising: an image section (11) with a number of picture elements (pixels) arranged in rows and columns; a storage section (12) with image storage elements arranged in rows and columns for (temporarily) at least partially storing charge absorbed by the pixels, wherein the charge is transferred to the storage elements; wherein one or more gates close to the transition (13) between the image section and the storage section are lengthened.

Abstract: A semiconductor energy detector having a region for detection and charge accumulation/transfer where a two-dimensional pixel array is formed on a surface of a semiconductor substrate on which energy rays become incident, is characterized in that the region for detection and charge accumulation/transfer comprises a plurality of transfer electrodes formed in each pixel, and an excess charge removing means arranged in correspondence with one of the transfer electrodes in each pixel.

Abstract: The invention relates to an image sensor device comprising a substrate, formed in CMOS technology, in particular, with an integrated semiconductor structure (ASIC) and, arranged above that, an optically active thin-film structure comprising in each case at least one layer made of doped and undoped amorphous silicon, spatially adjacent pixels in each case being formed in the horizontal plane, which pixels each have an optoelectronic transducer for converting incident light into an electric current proportional to the incident quantity of light and also a charge store assigned to the optoelectronic transducer, the charge state of which charge store can be varied in a manner dependent on the light incident on the assigned optoelectronic transducer.

Abstract: The present invention is directed to a photogate based pixel cell with an electronic shutter and which provides relatively low lag and high sensitivity for sensing infrared light reflected from objects. Additionally, this invention eliminates the need for a transfer gate in the pixel cell. In one embodiment, the reset and shutter transistors are implemented with PMOS transistors so that the pixel cell can have an increased dynamic range and a relatively high voltage swing. In another embodiment, the actual size of each pixel cell can be further reduced when the reset gate and the electronic shutter are implemented with NMOS transistors. Also, when a P− well is not disposed beneath the photogate, the ability of the pixel cell to sense infrared light is improved. Correlated double sampling can be used to improve the accuracy of the signal read out from the pixel cell.

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract: A readout gate electrode is selectively formed on a silicon substrate. An N-type drain region is formed at one end of the readout gate electrode, and an N-type signal storage region is formed at the other end thereof. A P+-type surface shield region is selectively epitaxial-grown on the signal storage region, and a silicide block layer is formed on the surface shield region to cover at least part of the signal storage region. A Ti silicide film is selective epitaxial-grown on the drain region.

Abstract: A solid state image sensing device and method of making same. The device includes a sensor portion, a vertical transfer register having a transfer electrode, a shunt interconnection of a refractory metal, and a light shielding film is provided. The shunt interconnection and the light shielding film are insulated from one another with an oxide film, an insulating film to serve as a stopper film at the time of pattering the oxide film is formed under the oxide film and the shunt interconnection, and the oxide film and the insulating film are not provided under the projecting portion of the light shielding film.

Abstract: A TDI sensor includes a column of pixels ordered from an initial pixel to a final pixel where each pixel includes reticulated clock conductors arranged to define a reticulation area and a pixel charge handling capacity. The reticulation area of a pixel increases from the final pixel to the initial pixel, and the pixel charge handling capacity increases from the initial pixel to the final pixel. The sensor includes a first bus structure of polysilicon, where the bus structure includes register element sets and each register element set includes a plurality of clock conductors. Each register element set includes a corresponding pixel reticulation area, and the pixel reticulation area of a first register element set is unequal to a pixel reticulation area of another register element set. The sensor also includes a second bus structure of metal disposed substantially diagonally to the first bus structure. The second bus structure includes clock bus sets, and each clock bus set includes bus conductors.

Abstract: Disclosed is a color linear image sensor having a small line-to-line distance, which comprises signal charge storage sections adjacent to light receiving sections. Signal charges are read by signal charge reading sections from the signal charge storage sections to signal charge transfer sections, and thereby residual images are prevented from being generated. Each of the signal charge reading sections is electrically connected with a portion of the signal charge transfer section which is adjacent to the signal charge reading section, and driving pulses are made common (&phgr;1 (TG)). Alternatively, each of the signal charge storage sections is electrically connected with a portion of the signal charge transfer section which is not adjacent to the signal charge reading section, and driving pulses are made common ((&phgr;2 (ST)). Accordingly, the number of wiring lines (pulse lines) arranged between the light receiving sections of respective colors is reduced by one.

Abstract: In production of a solid-state image pickup device including a semiconductor substrate, a photoelectric converter element group including a plurality of photoelectric converter elements formed in one column in one surface of the semiconductor substrate, a charge transfer path to transfer signal charge accumulated in the photoelectric converter elements, and readout gates to read signal charge from photoelectric converter elements to feed the charge to the charge transfer path, an ON or ONO film electrically insulates each transfer electrode constituting the charge transfer path from the semiconductor substrate and an oxide insulating film insulates a readout gate electrode constituting the readout gate from the semiconductor substrate to thereby improve electric characteristics of the solid-state image pickup device.

Abstract: A semiconductor memory device and a method of manufacturing the same improves an efficiency of injection of channel hot electrons while suppressing injection of drain avalanche hot carriers. In the semiconductor memory device, a first nitrided oxide film (RNO film) containing a first content of hydrogen is formed at a drain avalanche hot carrier injection region. Thereby, injection of drain avalanche hot carriers is effectively suppressed during a data writing operation. A second nitrided oxide film (NO film) containing a second content of hydrogen larger than the first content is formed at a channel hot electron injection region. Thereby, an efficiency of injection of channel hot electrons is improved during the data writing operation.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: A process for producing a solid image pickup device is demanded that can enhance a photoelectric conversion region by forming an overflow barrier layer at a deep position and can prevents generation of radiation due to the use of resist as a mask. Upon producing a solid image pickup device having a vertical overflow drain structure, ion implantation is conducted on an entire of a silicon substrate without using a resist mask, so as to form an overflow barrier layer. It is also possible that a trench is formed in a peripheral part of the silicon substrate to surround a pixel region and to separate the overflow barrier layer into the pixel region and an outer peripheral part, and an impurity diffusion layer having a conductive type different from that of the overflow barrier layer is formed on an inner surface of the trench.

Abstract: A charge transfer device has a charge transfer region under charge transfer electrodes for stepwise conveying charge packets through potential wells to a floating diffusion region, and the charge transfer region has a boundary sub-region contracting toward the floating diffusion region, wherein the final potential well is created at a certain portion in said boundary sub-region close to the floating diffusion region so that each charge packet travels over a short distance, thereby enhancing a charge transfer efficiency.

Abstract: A charge coupled device includes first and second pluralities of column registers and first and second register segments. The first plurality of column registers are splayed with respect to and on one side of a column direction line, and the second plurality of column registers are splayed with respect to and on another side of the column direction line. The first register segment is coupled to the first plurality of column registers, and the second register segment is coupled to the second plurality of column registers. The second register segment is spaced apart from the first register segment so as to define a layout area between the first and second register segments where at least one of an isolation register element and an output node is disposed. Each column register of the first plurality of column registers includes a plurality of column element wells.

Abstract: Disclosed is a photoelectric transducer having a photodiode that is formed on a second-conductivity-type well and is composed of a first-conductivity-type region to accumulate signal charge when light is supplied and a first second-conductivity-type region formed on the first-conductivity-type region. The first second-conductivity-type region is separated from a second-conductivity-type device separation region and is connected to the second-conductivity-type device separation region at part of the circumference of the first second-conductivity-type region through a second second-conductivity-type region that is formed to be at least partially shallower than the first second-conductivity-type region. Also, disclosed is a solid-state image sensing device equipped with the photoelectric transducer.

Abstract: A charge coupled device has an n-type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p-type local impurity region is formed in such a manner as to form a p-n junction together with the n-type charge accumulating layer and the n-type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.

Abstract: An amplifier type solid-state imaging device is operated in a capacitor load operation system. This solid-state imaging device is made high in reliability and an arrangement of the horizontal output circuit portion is simplified. The solid-state imaging device includes a plurality of pixel MOS transistors each of which is connected between a voltage source (VDD) and a vertical signal line, a control electrode thereof being connected to a scanning line and charges generated by photoelectric conversion being accumulated near the channel thereof, a load capacitor element connected between the vertical signal line and a first potential, and a reset MOS switch for resetting the load capacitor element to a reset potential. A potential of the vertical signal line is also reset. When a signal is read out, the potential of the load capacitor element is set to substantially the same potential as the channel potential of the pixel MOS transistor.

Abstract: An image sensor having a plurality of pixels arranged in a series of row and columns comprising: a semiconductor substrate having a plurality of pixels formed in rows and columns with at least two row adjacent pixels and at least two column adjacent pixels formed within the substrate; and at least one electrical function integrated within the adjacent pixels that is shared between the adjacent pixels. The electrical function can be either a contact region or an electrical circuit used in implementing either a photogate, a transfer gate, a reset gate, a row select gate, an amplifier drain, an output node, a floating diffusion contact, a reset drain, a lateral overflow gate, an overflow drain or an amplifier.

Abstract: An image pickup element unit and peripheral circuits are formed on a common semiconductor substrate. The image pickup element unit comprises sensors which converts incident lights into charges. The peripheral circuits comprise contact holes therein and transfer signals to external components via the contact holes. A tungsten film which works as both a photo shield and a barrier metal film is formed on the semiconductor substrate so that each of the sensors has its opening portion and the contact holes are filled with the tungsten film. An aluminum film which works as wiring is formed on the tungsten film filing the contact holes. A tungsten silicide layer is formed at conjunction portion between the tungsten film in the contact holes and the semiconductor substrate. Contacts comprising the tungsten film and the tungsten silicide layer show excellent ohmic contact characteristics.

Abstract: In an amplifier-type solid-state image sensor device, each unit cell comprises a photoconverter and a signal scanning circuit in an image sensing region on a semiconductor substrate, a metal film has an opening region for defining regions where light is radiated in the photoconverters of the unit cells, and a center position of the opening region of the metal film is displaced to the side of the center of the image sensing region with respect to a center portion of the photoconverter, so that the amount of light entering the center of the semiconductor chip and the peripheral portions of the semiconductor chip can be made equal, thereby obtaining substantially the same sensitivity at the center and peripheral portions of the semiconductor chip.

Abstract: An anti-reflective layer is formed on the sidewalls of metal interconnects in an integrated circuit containing photodetector devices. After fabricating the photodetector devices, the metal interconnects are formed. An anti-reflective layer is formed over the interconnects and is directionally etched so that a portion of the anti-reflective layer remains covering the interconnect sidewalls, thereby reducing optical cross-talk in the photodetector devices due to sidewall reflection.

Abstract: A semiconductor memory device and a method of manufacturing the same improves an efficiency of injection of channel hot electrons while suppressing injection of drain avalanche hot carriers. In the semiconductor memory device, a first nitrided oxide film (RNO film) containing a first content of hydrogen is formed at a drain avalanche hot carrier injection region. Thereby, injection of drain avalanche hot carriers is effectively suppressed during a data writing operation. A second nitrided oxide film (NO film) containing a second content of hydrogen larger than the first content is formed at a channel hot electron injection region. Thereby, an efficiency of injection of channel hot electrons is improved during the data writing operation.

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Abstract: In an organic electroluminescence display device having organic EL elements stacked on a substrate having a plurality of thin-film transistors formed on it, a plurality of pixel electrodes each being electrically connected to either one of the source region and the drain region of each of the thin-film transistors are provided on a flattening layer, and an electron injection layer of an electric insulator such as lithium fluoride is formed commonly on the plurality of pixel electrodes. And an organic layer including a light-emission layer and a hole injection layer are formed on this electron injection layer.

Abstract: The present invention relates to electro optical devices with a reduced filter thinning on the edge pixels and a method for reducing the thinning of filter layers on the pixels closest to the edge of an electro optical device such as a photosensitive chip, as would be used, for example, in a full-color digital copier or scanner. A semiconductor wafer includes a main surface defining a plurality of chip areas and tab regions separated by grooves, wherein the chip areas include inner photosites, outer photosites and bonding pads. A plurality of dams are deposited over the main surface in the tab regions, and a clear layer is deposited over the main surface exclusive of the bonding pads. Alternatively, a clear layer is deposited over the main surface exclusive of the bonding pads, and a plurality of tabs is then deposited in the tab regions on the main surface.

Abstract: A charged coupled device is disclosed including an asymmetrical split with independent control over the regions on opposite sides of the split. The charge coupled device is configurable for use in multiline or kinetic spectroscopy, and includes two separate horizontal registers with optional charge dump regions for improving efficiency.

Abstract: A semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a precursor, such as a metal halide (e.g., BaF.sub.2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of the temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.

Abstract: A solid-state imaging device that prevents the transfer errors of the signal charges from vertical charge-transfer sections to a horizontal charge-transfer section. A first plurality of buried channel regions in vertical charge-transfer sections are connected to a second buried channel region in a horizontal charge-transfer section so that the interfaces between the first plurality of buried channel regions and the second buried channel region are located to be aligned with the corresponding ends of the first plurality of gate electrodes. Thus, no potential dip nor potential barrier are generated in the vicinity of the interfaces between the first plurality of buried channel regions and the second buried channel region.

Abstract: An integrated circuit device structure comprises a semiconductor plateau containing an active region subjacent its front side, an electrode structure at the front side of the plateau, and an insulating layer surrounding the semiconductor plateau. A front side bus at the front side of the insulating layer is connected to the electrode structure. The front side bus extends over an elongate aperture in the insulating layer and is connected through the aperture to a back side bus over substantially the entire length of the front side bus.

Abstract: Circuitry is employed to provide an array of photoelements for generating an electrical signal from light energy. The circuit is essentially comprised of a plurality of photoelements including a light-receiving portion, which may include a phototransistor for receiving light and generating electrical energy therefrom, and a non-light-receiving portion, which may include amplification circuitry for properly biasing the phototransistor base and for amplifying the light signal. Within the array, geometric centers of vertically and horizontally adjacent phototransistors are equidistant from one another to form a symmetrical array of photoelements. A relatively high fill factor is achieved by an efficient, symmetrical layout of the photoelements within the array. One main advantage of the high fill factor of the symmetrical array is that it generates a greater light signal than related designs, which eliminates the need for optical magnification of pixels on an original sheet of paper.

Abstract: A CCD area sensor comprising two horizontal transfer registers and a charge discharging section comprising a sweep-out electrode adjacent to the side of a horizontal register opposite to an image section and drain section, wherein the horizontal transfer register has a multi-channel structure comprising two transfer channels and a distribution electrode.

Abstract: By incorporating an ITO electrode which is more transparent than polysilicon, and designing the pixel such that it has asymmetric gates with as much as possible of its light sensitive region covered by an ITO electrode, light sensitivity is increased. To solve the problem of impurity diffusion from the ITO electrode into the silicon below, the conventional Silicon Dioxide gate dielectric was replaced with an Oxide/Nitride/Oxide stack. Employing at least some polysilicon electrodes with ITO electrodes is desirable to allow entrance passages through which hydrogen passivation can be accomplished. The pixel architecture can be designed to increase sensitivity further by other design choices. The first of these choices is to incorporate a lenslet on each pixel such that as much as possible of the light falling on the pixel is made to pass through the portion of the pixel covered with ITO.

Abstract: The amplification type solid-state imaging device of this invention includes amplification type photoelectric converting elements arranged in a matrix.

Abstract: The present invention is directed to an improved CCD utilizing a potential gradient along the lengths of the various channels of the CCD during charge transfer to cause generated electrical charge to migrate along the length of the channel to a summing well. The potential gradient is formed by biasing the opposing ends of the electrodes overlying the lengths of the various channels with different voltages.

Abstract: A solid state image pickup device includes a semiconductor substrate, a CCD channel region in the semiconductor substrate, a plurality of polygates over the CCD channel regions, and a photoelectric conversion region having a portion above an uppermost surface of the semiconductor substrate.

Abstract: In order to realize a multi-function sensor in which a reduction of a CMOS sensor and an addition of pixel signals are performed in a pixel portion and, further, an addition and a non-addition can be arbitrarily performed, there is provided a solid state image pickup apparatus in which charges generated by a photoelectric converting device are perfectly transferred to a floating diffusion portion through a transfer switch and a change in electric potential of the floating diffusion portion is outputted to the outside by a source-follower amplifier. A few photoelectric converting devices are connected to one floating diffusion portion through the transfer switch. One set of a few source-follower amplifiers are formed for a few pixels. The photoelectric converting device is constructed by an MOS transistor gate and a depletion layer under the gate.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: An active type photoelectric conversion device includes a pixel having a photoelectric conversion area and a gate area which are formed in a surface portion of a semiconductor substrate of a first conductivity type.

Abstract: A charge-coupled device including, a light-receiving part having a glass and receiving an image, a photo chromic layer formed on the glass and being progressively colored according to a level of brightness of the image, to control an amount of transmitted light such that the amount of light transmitted for bright parts and dark parts of an image are substantially equalized, and a frame located on sides of the light receiving part.

Abstract: In a CMOS area sensor, in order to enable an image signal of only a portion in the area to be read out on a block unit basis, there is provided a photoelectric converting apparatus of an amplifying type having two-dimensional sensor pixels, a transfer circuit for transferring pixel signals of the sensor pixels, and two-dimensional memory pixels for recording the transferred pixel signals, wherein two switches for writing or resetting are provided for at least ones of the sensor pixels and the memory pixels, one of the switches is controlled by a vertical selection circuit, and the other switch is controlled by a horizontal selection circuit.

Abstract: A charge-coupled device image sensor includes a substrate, a buried channel region of a first conductivity type, formed in the substrate to a predetermined depth, for transferring signal charges, a first high concentration impurity region of a second conductivity type, formed in the substrate adjacent to the buried channel region, forming a channel stop, a first surface channel region of the second conductivity type, formed on the buried channel region, for transferring dark current charges, a second high concentration impurity region of the first conductivity type, formed on the first high concentration impurity region, for removing dark current charges from the surface channel region, and a second surface channel region of the second conductivity type formed to a predetermined depth in the substrate between the second high concentration impurity region and the first surface channel region.

Abstract: By incorporating an ITO electrode which is more transparent than polysilicon, and designing the pixel such that it has asymmetric gates with as much as possible of its light sensitive region covered by an ITO electrode, light sensitivity is increased. To solve the problem of impurity diffusion from the ITO electrode into the silicon below, the conventional Silicon Dioxide gate dielectric was replaced with an Oxide/Nitride/Oxide stack. Employing at least some polysilicon electrodes with ITO electrodes is desirable to allow entrance passages through which hydrogen passivation can be accomplished. The pixel architecture can be designed to increase sensitivity further by other design choices. The first of these choices is to incorporate a lenslet on each pixel such that as much as possible of the light falling on the pixel is made to pass through the portion of the pixel covered with ITO.

Abstract: A CCD pixel 10 has an antiblooming structure including a lateral overflow drain 36 of one conductivity. The drain 36 is mounted on one side by a heavy dope channel stop region. The rest of drain 36 is bounded by a heavily doped container region 38 that is formed in the same opening that is used to form LOD 36.

Abstract: Charge coupled device (CCD) solid-state image sensors comprise a substrate including a plurality of sensor groups. Each sensor group consists of N photodiodes and 2N+1 transfer electrodes, where N is at least two. By providing, for example, two photodiodes and five transfer electrodes in a group, improved area efficiency may be provided along with efficient manufacturing and driving. Three insulated patterned conductive layers are formed on a gate insulating layer, to define the first through fifth transfer electrodes on the transfer region.

Abstract: A multiple-frame image sensor comprising a full-frame CCD sensor of two-story construction having an overlying photosensitive layer that converts input radiation to electric charge and an underlying CCD structure which functions to collect and store the charge for read-out of more than one charge packet per pixel, with the pixels being of minimum size. The sensor structure is rendered capable of handling more than one photosignal charge packet per pixel in an area-efficient way through the use of ripple clocking, so that in a preferred embodiment a 4-poly, 7-phase ripple-clocked vertical CCD register is fabricated with 7 gates, one of which is run vertically to create openings, e.g., between the 1 and 6 gates, that pass electrode contacts to N+ sources in the channel stops of the register to form photosignal charge packets in the region between the stops. The ripple-gating controls the movement of the charge packets for storage along the CCD channel until 3 charge packet read-out.

Abstract: The amplification type solid-state imaging device of this invention includes amplification type photoelectric converting elements arranged in a matrix.