Field Effect Device Patents (Class 257/24)
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Publication number: 20150034906Abstract: A semiconductor device and a method for fabricating the same are disclosed. In the method, a substrate structure is provided, including a substrate and a fin-shaped buffer layer formed on the surface of the substrate. A QW material layer is formed on the surface of the fin-shaped buffer layer. A barrier material layer is formed on the QW material layer. The QW material layer is suitable for forming an electron gas therein. Thereby the short-channel effect is improved, while high mobility of the semiconductor device is guaranteed. In addition, according to the present disclosure, thermal dissipation of the semiconductor device may be improved, and thus performance and stability of the device may be improved.Type: ApplicationFiled: May 19, 2014Publication date: February 5, 2015Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: De Yuan XIAO
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Patent number: 8946679Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.Type: GrantFiled: August 21, 2013Date of Patent: February 3, 2015Assignee: Intel CorporationInventor: Ravi Pillarisetty
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Patent number: 8946680Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.Type: GrantFiled: August 10, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Isaac Lauer, Amlan Majumdar, Jeffrey Sleight
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Patent number: 8941094Abstract: Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.Type: GrantFiled: September 2, 2010Date of Patent: January 27, 2015Assignee: Nantero Inc.Inventors: C. Rinn Cleavelin, Thomas Rueckes, H. Montgomery Manning, Darlene Hamilton, Feng Gu
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Patent number: 8940576Abstract: The present invention provides practical methods for n-type doping of graphene, either during graphene synthesis or following the formation of graphene. Some variations provide a method of n-type doping of graphene, comprising introducing a phosphorus-containing dopant fluid to a surface of graphene, under effective conditions to dope the graphene with phosphorus atoms or with phosphorus-containing molecules or fragments. It has been found that substitutional doping with phosphine can effectively modulate the electrical properties of graphene, such as graphene supported on Si or SiC substrates. Graphene sheet resistances well below 200 ohm/sq, and sheet carrier concentrations above 5×1013 cm?2, have been observed experimentally for n-doped graphene produced by the disclosed methods. This invention provides n-doped graphene for various electronic-device applications.Type: GrantFiled: September 22, 2011Date of Patent: January 27, 2015Assignee: HRL Laboratories, LLCInventors: Steven S. Bui, Jeong-Sun Moon
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Patent number: 8937299Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.Type: GrantFiled: August 14, 2013Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Anirban Basu, Cheng-Wei Cheng, Amlan Majumdar, Ryan M. Martin, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
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Publication number: 20150014632Abstract: Methods of manufacture of advanced electronic and photonic structures including heterojunction transistors, transistor lasers and solar cells and their related structures, are described herein. Other embodiments are also disclosed herein.Type: ApplicationFiled: October 1, 2014Publication date: January 15, 2015Inventor: Matthew H. Kim
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Publication number: 20150014630Abstract: A tunneling device may include a tunnel barrier layer, a first material layer including a first conductivity type two-dimensional material on a first surface of the tunnel barrier layer and a second material layer including a second conductivity type two-dimensional material on a second surface of the tunnel barrier layer. The tunneling device may use a tunneling current through the tunnel barrier layer between the first material layer and the second material layer.Type: ApplicationFiled: February 25, 2014Publication date: January 15, 2015Applicants: Sungkyunkwan University Foundation for Corporate Collaboration, Samsung Electronics Co., Ltd.Inventors: Jun-hee CHOI, Won-jong YOO, Seung-hwan LEE, Min-sup CHOI, Xiao Chi LIU, Ji-a LEE
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Publication number: 20150014631Abstract: GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.Type: ApplicationFiled: February 12, 2013Publication date: January 15, 2015Inventors: Jonas Ohlsson, Mikael Bjork
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Patent number: 8932919Abstract: A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet.Type: GrantFiled: November 21, 2012Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Damon B. Farmer, Aaron D. Franklin, Sataoshi Oida, Joshua T. Smith
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Patent number: 8927967Abstract: An electrochemically-gated field-effect transistor includes a source electrode, a drain electrode, a gate electrode, a transistor channel and an electrolyte. The transistor channel is located between the source electrode and the drain electrode. The electrolyte completely covers the transistor channel and has a one-dimensional nanostructure and a solid polymer-based electrolyte that is employed as the electrolyte.Type: GrantFiled: April 24, 2013Date of Patent: January 6, 2015Assignee: Karlsruhe Institute of TechnologyInventors: Subho Dasgupta, Horst Hahn, Babak Nasr
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Patent number: 8927966Abstract: A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer.Type: GrantFiled: October 18, 2012Date of Patent: January 6, 2015Assignee: Tsinghua UniversityInventors: Libin Liu, Renrong Liang, Jing Wang, Jun Xu
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Publication number: 20150001468Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.Type: ApplicationFiled: September 12, 2014Publication date: January 1, 2015Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
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Patent number: 8921830Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.Type: GrantFiled: May 2, 2012Date of Patent: December 30, 2014Assignee: Intel CorporationInventors: Chi On Chui, Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
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Publication number: 20140353588Abstract: A device to produce an output based on interference of electron waves is disclosed. Said device comprised out of two areas having different medium properties for propagation of an electron wave, where the first of said areas is connected to a source to inject electrons and the second of said areas is connected to a drain to collect electrons while said electrons have a propagation path through the device starting at the source and ending at the drain. Said areas are designed in a manner to result in advancing and reflected waves having interleaved sections along said path which yield interference, either constructive or destructive, thus determining the transport probability of the electron through the device. Said device is operated either as a switch, in a first embodiment, by adding a control gate, or as a detector, in a second embodiment, used for measurement of external particle ensemble properties.Type: ApplicationFiled: June 3, 2013Publication date: December 4, 2014Inventor: DAN BERCO
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Patent number: 8901538Abstract: A nano resonator includes a substrate, a first insulating layer disposed on the substrate, a first source disposed on the first insulating layer at a first position, a first drain disposed on the first insulating layer at a second position spaced apart from the first position so that the first drain faces the first source, a first nano-wire channel having a first end connected to the first source and a second end connected to the first drain, and having a doping type and a doping concentration that are identical to a doping type and a doping concentration of the first source and the first drain, and a second nano-wire channel disposed at a predetermined distance from the first nano-wire channel in a direction perpendicular to the substrate or a direction parallel to the substrate.Type: GrantFiled: March 18, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jie Ai Yu, Duck Hwan Kim, In Sang Song, Jing Cui
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Patent number: 8900935Abstract: In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire.Type: GrantFiled: January 25, 2011Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang, Yu Zhu
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Patent number: 8901533Abstract: Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.Type: GrantFiled: March 8, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-moon Lee, Young-jin Cho
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Patent number: 8890117Abstract: A nanowire circuit architecture is presented. The technology comprises of nanowire transistors (8,9), and optionally nanowire capacitors (12) and nanowire resistors (11), that are integrated using two levels of interconnects only (1,2). Implementations of ring-oscillators, sample-and-hold circuits, and comparators may be realized in this nanowire circuit architecture. Circuit input and circuit output as well as the transistor connections within each circuit are provided in the two levels of interconnects (1,2).Type: GrantFiled: March 28, 2008Date of Patent: November 18, 2014Assignee: Qunano ABInventor: Lars-Erik Wernersson
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Patent number: 8890119Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.Type: GrantFiled: December 18, 2012Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Brian S. Doyle, Roza Kotlyar, Uday Shah, Charles C. Kuo
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Patent number: 8890118Abstract: The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor.Type: GrantFiled: December 17, 2010Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Benjamin Chu-Kung, Gilbert Dewey, Marko Radosavljevic, Niloy Mukherjee
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Patent number: 8884345Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.Type: GrantFiled: September 24, 2013Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
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Patent number: 8884266Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.Type: GrantFiled: June 13, 2012Date of Patent: November 11, 2014Assignees: Samsung Display Co., Ltd., SNU R&DB FoundationInventors: Sang Ho Park, Young Ki Shin, Yoon Ho Khang, Joo Hyung Lee, Hyung Woo Lee, Seung Hun Hong
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Publication number: 20140326953Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.Type: ApplicationFiled: July 17, 2014Publication date: November 6, 2014Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
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Publication number: 20140326952Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.Type: ApplicationFiled: May 9, 2014Publication date: November 6, 2014Inventors: Kelin J. KUHN, Seiyon KIM, Rafael RIOS, Stephen M. Cea, Martin D. GILES, Annalisa CAPPELLANI, Titash RAKSHIT, Peter CHANG, Willy RACHMADY
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Patent number: 8878244Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.Type: GrantFiled: January 3, 2008Date of Patent: November 4, 2014Assignee: Renesas Electronics CorporationInventors: Yasuichi Kondo, Wataru Hirasawa, Nobuyuki Sugii
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Patent number: 8878152Abstract: A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.Type: GrantFiled: February 29, 2012Date of Patent: November 4, 2014Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLCInventors: Yun Wang, Tony P. Chiang, Imran Hashim, Dipankar Pramanik
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Publication number: 20140319459Abstract: Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.Type: ApplicationFiled: July 11, 2014Publication date: October 30, 2014Inventors: Andrew P. HOMYK, Michael D. HENRY, Axel SCHERER, Sameer WALAVALKAR
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Publication number: 20140319466Abstract: An electrochemically-gated field-effect transistor includes a source electrode, a drain electrode, a gate electrode, a transistor channel and an electrolyte. The transistor channel is located between the source electrode and the drain electrode. The electrolyte completely covers the transistor channel and has a one-dimensional nanostructure and a solid polymer-based electrolyte that is employed as the electrolyte.Type: ApplicationFiled: April 24, 2013Publication date: October 30, 2014Applicant: KARLSRUHER INSTITUT FUER TECHNOLOGIEInventor: KARLSRUHER INSTITUT FUER TECHNOLOGIE
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Patent number: 8872160Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.Type: GrantFiled: April 29, 2013Date of Patent: October 28, 2014Assignee: Intel CorporationInventors: Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Niloy Mukherjee
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Patent number: 8872161Abstract: The present disclosure provides an integrated circuit (IC). The IC includes a substrate having a metal-oxide-semiconductor (MOS) region. The IC further includes first gate, source and drain regions, having a first length, and second gate, source and drain regions, having a second length. A first nanowire set is disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a feature in the first source region and a feature in the first drain region. A second nanowire set is disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a feature in the second source region and a feature in the second drain region. The diameters are such that if the first length is greater than the second length, the first diameter is less than the second diameter, and vice versa.Type: GrantFiled: August 26, 2013Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Jiun-Jia Huang
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Patent number: 8860091Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.Type: GrantFiled: April 16, 2012Date of Patent: October 14, 2014Assignee: HRL Laboratories, LLCInventors: David F. Brown, Miroslav Micovic
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Patent number: 8841650Abstract: An electronic structure modulation transistor having two gates separated from a channel by corresponding dielectric layers, wherein the channel is formed of a material having an electronic structure that is modified by an electric field across the channel.Type: GrantFiled: February 23, 2010Date of Patent: September 23, 2014Assignee: Cornell UniversityInventor: Hassan Raza
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Publication number: 20140264277Abstract: The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled.Type: ApplicationFiled: April 16, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka
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Publication number: 20140264276Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
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Publication number: 20140264278Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: ApplicationFiled: January 16, 2014Publication date: September 18, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Publication number: 20140252315Abstract: A transistor and a fabrication method thereof. A transistor includes a channel region including linkers, formed on a substrate, and metallic nanoparticles grown from metal ions bonded to the linkers, a source region disposed at one end of the channel region, a drain region disposed at the other end of the channel region opposite of the source region, and a gate coupled to the channel region and serving to control migration of charges in the channel region. The metallic nanoparticles have a substantially uniform pattern arrangement in the channel region.Type: ApplicationFiled: March 6, 2014Publication date: September 11, 2014Applicant: SK INNOVATION CO., LTD.Inventors: Jun-Hyung KIM, Young-Keun LEE, Hong YOU, Tae-Hee KIM
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Publication number: 20140252316Abstract: Described are ZnxCd1-xSySe1-y/ZnSzSe1-z core/shell nanocrystals, CdTe/CdS/ZnS core/shell/shell nanocrystals, optionally ally doped Zn(S,Se,Te) nano- and quantum wires, and SnS quantum sheets or ribbons, methods for making the same, and their use in biomedical and photonic applications, such as sensors for analytes in cells and preparation of field effect transistors.Type: ApplicationFiled: October 3, 2012Publication date: September 11, 2014Inventors: Hao Yan, Zhengtao Deng, Yan Liu
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Patent number: 8828783Abstract: A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.Type: GrantFiled: October 15, 2013Date of Patent: September 9, 2014Assignee: Uriel Solar, Inc.Inventor: James David Garnett
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Patent number: 8823089Abstract: A semiconductor power device includes a SiC semiconductor body. At least part of the SiC semiconductor body constitutes a drift zone. A first contact is at a first side of the SiC semiconductor body. A second contact is at a second side of the SiC semiconductor body. The first side is opposite the second side. A current path between the first contact and the second contact includes at least one graphene layer.Type: GrantFiled: April 15, 2011Date of Patent: September 2, 2014Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Roland Rupp
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Publication number: 20140239254Abstract: A system is provided and includes a wafer and a mask. The wafer includes a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer and has a first region with a first SOI thickness and a second region with a second SOI thickness, the first and second SOI thicknesses being different from one another and sufficiently large such that respective pairs of SOI pads connected via respective nanowires with different thicknesses are formable therein. The mask covers one of the first and second regions and prevents a thickness change of the other of the first and second regions from having effect at the one of the first and second regions.Type: ApplicationFiled: April 17, 2013Publication date: August 28, 2014Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy M. Cohen, Amlan Majumdar, Jeffrey W. Sleight
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Publication number: 20140239255Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.Type: ApplicationFiled: January 23, 2014Publication date: August 28, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-Gil KANG, Sung-Bong KIM, Chang-Woo OH, Dong-Won KIM
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Patent number: 8815683Abstract: A nonvolatile memory electronic device including nanowire channel and nanoparticle-floating gate nodes, in which the nonvolatile memory electronic device, which comprises a semiconductor nanowire used as a charge transport channel and nanoparticles used as a charge trapping layer, is configured by allowing the nanoparticles to be adsorbed on a tunneling layer deposited on a surface of the semiconductor nanowire, whereby charge carriers moving through the nanowire are tunneled to the nanoparticles by a voltage applied to a gate, and then, the charge carriers are tunneled from the nanoparticles to the nanowire by the change of the voltage that has been applied to the gate, whereby the nonvolatile memory electronic device can be operated at a low voltage and increase the operation speed thereof.Type: GrantFiled: February 12, 2008Date of Patent: August 26, 2014Assignee: Intellectual Discovery Co., Ltd.Inventors: Sangsig Kim, Chang Jun Yoon, Dong Young Jeong, Dong Hyuk Yeom
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Patent number: 8816326Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.Type: GrantFiled: November 25, 2011Date of Patent: August 26, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huaxiang Yin, Jun Luo, Chao Zhao, Honggang Liu, Dapeng Chen
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Patent number: 8816328Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.Type: GrantFiled: September 14, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
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Patent number: 8816327Abstract: Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.Type: GrantFiled: September 12, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
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Patent number: 8816325Abstract: A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, wherein a first voltage applied across at least one pair of the aligned quantum dot and donor atom controls a donor-quantum dot coupling. A method of performing quantum computing in a scalable architecture quantum computing apparatus includes arranging a pattern of single spin memory donor atoms in a semiconductor layer, forming a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, applying a first voltage across at least one aligned pair of a quantum dot and donor atom to control a donor-quantum dot coupling, and applying a second voltage between one or more quantum dots to control a Heisenberg exchange J coupling between quantum dots and to cause transport of a single spin polarized electron between quantum dots.Type: GrantFiled: October 4, 2012Date of Patent: August 26, 2014Assignee: The Regents of the University of CaliforniaInventors: Thomas Schenkel, Cheuk Chi Lo, Christoph Weis, Stephen Lyon, Alexei Tyryshkin, Jeffrey Bokor
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Patent number: 8809835Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.Type: GrantFiled: August 7, 2012Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Glyn Braithwaite, Richard Hammond, Matthew T. Currie
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Patent number: 8809836Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.Type: GrantFiled: February 4, 2013Date of Patent: August 19, 2014Assignee: Intel CorporationInventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
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Patent number: 8809837Abstract: A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet.Type: GrantFiled: August 20, 2013Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Damon B. Farmer, Aaron D. Franklin, Sataoshi Oida, Joshua T. Smith