Abstract: Disclosed herein is a nano device, including: a carbon layer including one-layered graphene having a honeycombed planar structure in which carbon atoms are connected with each other and two or more-layered monocrystalline graphite; and one or more vertically-grown nanostructures formed on the carbon layer. This nano device can be used to manufacture an integrated circuit in which various devices including a graphene electronic device and a photonic device are connected with each other, and is a high-purity and high-quality nano device having a small amount of impurities because a metal catalyst is not used.

Abstract: A memory device can include an active layer that has a selectable lateral conductivity. The layer can include a plurality of nanoparticles.

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract: A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer.

Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.

Abstract: Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications.

Abstract: Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX. Nanowire cores and pads are etched in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial shells are formed surrounding each of the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores/epitaxial shells, wherein the portions of the nanowire cores/epitaxial shells surrounded by the gate stack serve as channels of the device, and wherein the pads and portions of the nanowire cores/epitaxial shells that extend out from the gate stack serve as source and drain regions of the device.

Abstract: A nanowire sensor having a nanowire in a network structure includes: source and drain electrodes formed over a substrate; a nanowire formed between the source and drain electrodes and having a network structure in which patterns of intersections are repeated; and a detection material fixed to the nanowire and selectively reacting with a target material introduced from outside.

Abstract: A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.

Abstract: A nano resonator includes a substrate, a first insulating layer disposed on the substrate, a first source disposed on the first insulating layer at a first position, a first drain disposed on the first insulating layer at a second position spaced apart from the first position so that the first drain faces the first source, a first nano-wire channel having a first end connected to the first source and a second end connected to the first drain, and having a doping type and a doping concentration that are identical to a doping type and a doping concentration of the first source and the first drain, and a second nano-wire channel disposed at a predetermined distance from the first nano-wire channel in a direction perpendicular to the substrate or a direction parallel to the substrate.

Abstract: An electronic device includes a carbon layer including graphene or graphite and a thin film formed on the carbon layer. The electronic device may further include a drain electrode, a source electrode and/or a gate electrode formed on the thin film. A method of manufacturing an electronic device includes preparing a carbon layer including graphene or graphite, forming a nanostructure on the carbon layer, and forming a thin film to cover the nanostructure.

Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include a modulation doped heterostructure, wherein the modulation doped heterostructure may comprise an active portion having a first bandgap and a delta doped portion having a second bandgap.

Abstract: Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: A semiconductor device includes a substrate, a channel layer that is formed above the substrate, where the channel layer is made of a first nitride series compound semiconductor, a barrier layer that is formed on the channel layer, a first electrode that is formed on the barrier layer, and a second electrode that is formed above the channel layer. Here, the barrier layer includes a block layers and a quantum level layer. The block layer is formed on the channel layer and made of a second nitride series compound semiconductor having a larger band gap energy than the first nitride series compound semiconductor, and the quantum level layer is made of a third nitride series compound semiconductor having a smaller band gap energy than the second nitride series compound semiconductor, and has a quantum level formed therein.

Abstract: This application relates to graphene based heterostructures and transistor devices comprising graphene. The hetero-structures comprise i) a first graphene layer; ii) a spacer layer and iii) a third graphene. The transistors comprise (i) an electrode, the electrode comprising a graphene layer, and (ii) an insulating barrier layer.

Abstract: A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

Abstract: An electronic device includes a substrate supporting mobile charge carriers, insulative features formed on the substrate surface to define first and second substrate areas on either side of the insulative features, the first and second substrate areas being connected by an elongate channel defined by the insulative features, the channel providing a charge carrier flow path in the substrate from the first area to the second area, the conductivity between the first and second substrate areas being dependent upon the potential difference between the areas. The mobile charge carriers can be within at least two modes in each of the three dimensions within the substrate. The substrate can be an organic material. The mobile charge carriers can have a mobility within the range 0.01 cm2/Vs to 100 cm2/Vs, and the electronic device may be an RF device. Methods for forming such devices are also described.

Abstract: A field effect transistor device includes: a reservoir bifurcated by a membrane of three layers: two electrically insulating layers; and an electrically conductive gate between the two insulating layers. The gate has a surface charge polarity different from at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes: an ionic solution filling the reservoir and the nanochannel; a drain electrode; a source electrode; and voltages applied to the electrodes (a voltage between the source and drain electrodes and a voltage on the gate) for turning on an ionic current through the ionic channel wherein the voltage on the gate gates the transportation of ions through the ionic channel.

Abstract: Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.

Abstract: The present invention is directed to a multiwire nanowire field effect transistor (nwFET) device for the measurement. The device includes a sensing nanowire having a first end and a second end and a nanowire FET having a first end and a second end, wherein the first end of the sensing nanowire is connected to the nanowire FET to form a node. Additionally, the first end of the nanowire FET is connected to a source electrode, the second end of the nanowire FET is connected to a drain electrode, and the second end of the sensing nanowire is connected to a base electrode. The sensing nanowire is derivatized with a plurality of immobilized capture probes that are specific for a target(s) of interest. The device is used to detect biomolecules or to detect the change in the ionic environment of a sample. In a further embodiment, the sensing nanowire is derivatized with amino, carboxyl or hydroxyl groups.

Abstract: Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.

Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2 DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Abstract: A method for manufacturing a plurality of holders each being for an LED package structure includes steps: providing a base, pluralities of through holes being defined in the base to divide the base into a plurality of basic units; etching the base to form a dam at an upper surface of each of the basic units of the base; forming a first electrical portion and a second electrical portion on each basic unit of the base, the first electrical portion and the second electrical portion being separated and insulated from each other by the dam; providing a plurality of reflective cups each on a corresponding basic unit of the base, each of the reflective cups surrounding the corresponding dam; and cutting the base into the plurality of basic units along the through holes to form the plurality of holders.

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract: Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract: A semiconductor device comprises an active layer above a first confinement layer. The active layer comprises a layer of ?-Sn less than 20 nm thick. The first confinement layer is formed of material with a wider band gap than ?-Sn, wherein the band gap offset between ?-Sn and this material allows confinement of charge carriers in the active layer so that the active layer acts as a quantum well. A similar second confinement layer may be formed over the active layer. This semiconductor device may be a p-FET. A method of fabricating such a semiconductor device is described.

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.

Abstract: The present invention relates to a semiconductor device (1) comprising: at least a nanowire (2) configured to comprise: at least a source region (3) comprising a corresponding source semiconductor material, at least a drain region (4) comprising a corresponding drain semiconductor material and at least a channel region (5) comprising a corresponding channel semiconductor material, the channel region (5) being arranged between the source region (3) and the drain region (4), at least a gate electrode (6) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of the channel region (5), and at least a strain gate (7) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of a segment of the nanowire (2), the strain gate (7) being configured to apply a strain to the nanowire segment (8), thereby to facilitate at least an alteration of the energy bands corresponding to the source region (3) relative to the energy bands corresponding to the ch

Abstract: Graphene semiconductor device, a method of manufacturing a graphene semiconductor device, an organic light emitting display and a memory, include forming a multilayered member including a sacrificial substrate, a sacrificial layer, and a semiconductor layer deposited in sequence, forming a transfer substrate on the semiconductor layer, forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sacrificial substrate from the semiconductor layer, forming a second laminate by forming a graphene layer on a base substrate, combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer, and removing the transfer substrate.

Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.

Abstract: A thin film transistor includes nanowires. More specifically, the thin film transistor includes nanowires aligned between and extending to opposite facing lateral surfaces of source/drain electrodes on a substrate. The nanowires extend in a direction parallel to a major surface defining the substrate to form a semiconductor channel layer. Also disclosed herein is a method for fabricating the thin film transistor.

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both side portions, the source electrode and the drain electrode electrically connected to the silicon nanowire, respectively.

Abstract: A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.

Abstract: A gallium nitride-based HEMT device, comprising a channel layer formed of an InGaN alloy. Such device may comprise an AlGaN/InGaN heterostructure, e.g., in a structure including a GaN layer, an InGaN layer over the GaN layer, and a (doped or undoped) AlGaN layer over the InGaN layer. Alternatively, the HEMT device of the invention may be fabricated as a device which does not comprise any aluminum-containing layer, e.g., a GaN/InGaN HEMT device or an InGaN/InGaN HEMT device.