Abstract: A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.

Abstract: Various embodiments of the present invention are directed to optical devices comprising planar lenses. In one aspect, an optical device includes two or more planar lenses (208,209), and one or more dielectric layers (210-212). Each planar lens includes a non-periodic, sub-wavelength grating layer (1110), and each dielectric layer is disposed adjacent to at least one planar lens to form a solid structure. The two or more planar lenses are substantially parallel and arranged to have a common optical axis (214) so that light transmitted through the optical device substantially parallel to the optical axis is refracted by the two or more planar lenses.

Abstract: A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.

Abstract: Disclosed herein is a solid-state imaging device including a photoelectric conversion element operable to generate electric charge according to the amount of incident light and to accumulate the electric charge in the inside thereof, an electric-charge holding region in which the electric charge generated through photoelectric conversion by the photoelectric conversion element is held until read out, and a transfer gate having a complete transfer path through which the electric charge accumulated in the photoelectric conversion element is completely transferred into the electric-charge holding region, and an intermediate transfer path through which the electric charge generated by the photoelectric conversion element during an exposure period and being in excess of a predetermined charge amount is transferred into the electric-charge holding region. The complete transfer path and the intermediate transfer path are formed in different regions.

Abstract: A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section.

Abstract: A color filter is formed using a simple manufacturing method, and bias application to a pixel separating electrode allows sensitivity in low illumination intensity to be improved. In a solid-state imaging element, in which a plurality of unit pixel sections are disposed two dimensionally on a side closer to a front surface of a semiconductor substrate or a semiconductor layer, each unit pixel section having a light receiving section for generating a signal charge by light irradiation, an adjoining unit pixel section is formed in the same color to allow for lesser alignment accuracy of the color filter. A pixel separating electrode is formed in the adjoining unit pixel section, and a signal charge is shared by bias application during low illumination intensity, thereby improving an effective photodiode area.

Abstract: A photoelectric conversion device including a photoelectric conversion element including a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type provided in contact with the first semiconductor region, a third semiconductor region of the first conductivity type provided apart from the second semiconductor region, a fourth semiconductor region of a second conductivity type provided between the second and the third semiconductor region, and a fifth semiconductor region of the first conductivity type provided apart from the third semiconductor region, wherein an impurity concentration of the third semiconductor region is lower than that of the fifth semiconductor region, and a depth of a lower-edge of the third semiconductor region from a surface of the semiconductor substrate is larger than that of a lower-edge of the fifth semiconductor region.

Abstract: A photoelectric conversion device, comprising a photoelectric conversion portion, provided in a semiconductor substrate, including a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type provided adjacent to the first semiconductor region, a third semiconductor region of the first conductivity type provided at a position away from the second semiconductor region, and a gate electrode provided between the second semiconductor region and the third semiconductor region, wherein the second semiconductor region is provided at a position away from the gate electrode, and the semiconductor substrate includes a region of a second conductivity type within a region extending from an edge of the second semiconductor region to below the gate electrode.

Abstract: Certain embodiments provide a solid-state imaging device including: a semiconductor substrate of a first conductivity type having a first face and a second face that is the opposite side from the first face; a plurality of pixels provided on the first face of the semiconductor substrate, each of the pixels including a semiconductor region of a second conductivity type that converts incident light into signal charges, and stores the signal charges; a readout circuit provided on the second face of the semiconductor substrate to read the signal charges stored in the pixels; an ultrafine metal structure placed at intervals on a face on a side of the semiconductor region, the light being incident on the face; and an insulating layer provided between the ultrafine metal structure and the semiconductor region.

Abstract: Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the present disclosure are directed towards passivation techniques and configurations for a flexible display. In one embodiment, a flexible display includes a flexible substrate, an array of display elements configured to emit or modulate light disposed on the flexible substrate, and a passivation layer including molecules of silicon (Si) bonded with oxygen (O) or nitrogen (N), the passivation layer being disposed on the array of display elements to protect the array of display elements from environmental hazards.

Abstract: A solid-state imaging device includes: a pixel region in which a plurality of pixels composed of a photoelectric conversion section and a pixel transistor is arranged; an on-chip color filter; an on-chip microlens; and a multilayer interconnection layer in which a plurality of layers of interconnections is formed through an interlayer insulating film. The solid-state imaging device further includes a light-shielding film formed through an insulating layer in a pixel boundary of a light receiving surface in which the photoelectric conversion section is arranged.

Abstract: An input/output device includes a display circuit which changes its display state in accordance with a display data signal; a plurality of photodetector circuits which generate optical data in accordance with illuminance of light entering the photodetector circuits; wherein the photodetector circuits each include X (a natural number of 2 or more) photoelectric conversion elements; X charge accumulation control transistors in which one of a source and a drain is electrically connected to a second current terminal of one photoelectric conversion element of the X photoelectric conversion elements, and one charge accumulation control signal of X charge accumulation control signals from the photodetector circuit control section is input to the gate; and an amplifying transistor in which a gate is electrically connected to one of the source and the drain of each of the X charge accumulation control transistors.

Abstract: A method comprises preparing a semiconductor substrate having a first portion, and a second portion including a first region and a second region; forming an active region in the first portion, and an isolating portion of an insulator defining the active region in the second portion; forming a first semiconductor region of a first conductivity type configuring a first photoelectric conversion element, a second semiconductor region of first conductivity type configuring a second photoelectric conversion element, a third semiconductor region of first conductivity type, a fourth semiconductor region of the conductivity type, a first gate electrode configuring a first transfer transistor, and a second gate electrode configuring a second transfer; exposing the first region of the semiconductor substrate, and performing ion implantation masked by a first photoresist pattern covering the second region of the semiconductor substrate, thus forming a fifth semiconductor region of a second conductivity type.

Abstract: An electroluminescent display panel and method of fabricating the same are provided. The electroluminescent display panel includes a first multiple-layered structural layer, a second multiple-layered structural layer, a passivation layer and a third patterned conductive layer. The first multiple-layered structural layer includes a first patterned conductive layer, a first patterned insulation layer and an oxide semiconductor layer, and the first patterned conductive layer, the first patterned insulation layer and the oxide semiconductor layer have substantially the same shape. The second multiple-layered structural layer includes a second patterned conductive layer. The passivation layer has a plurality of through holes. A portion of the through holes expose the top surface and the lateral surface of the oxide semiconductor layer and the lateral surface of the first patterned conductive layer.

Abstract: An image sensor including a pixel unit, the pixel unit including a photodiode, a first color filter and a second color filter each disposed in a different position on a plane above the photodiode, and a first on-chip lens disposed over the first color filter and a second on-chip lens disposed over the second color filter.

Abstract: Disclosed is a thin film transistor substrate which facilitates to improve output and transfer characteristics of thin film transistor, wherein the thin film transistor substrate comprises a thin film transistor comprising a lower gate electrode on a substrate, an active layer on the lower gate electrode, source and drain electrodes on the active layer, and an upper gate electrode on the source electrode, drain electrode and active layer, the upper gate electrode for covering a channel region defined by the source and drain electrodes; and a contact portion for electrically connecting the lower gate electrode with the upper gate electrode.

Abstract: A solid-state imaging device includes: a substrate which is formed of a semiconductor and includes a first surface and a second surface which face opposite sides; a gate insulation film which is formed on a trench formed in the substrate to penetrate the first surface and the second surface; and a gate electrode which is embedded in the trench through the gate insulation film to be exposed to a second surface side of the substrate. A step difference is formed from the second surface of the substrate to a tip end surface of the gate electrode on the second surface side.

Abstract: According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.

Abstract: The present invention provides a thin-film transistor manufactured on a transparent substrate having a structure of a top gate type crystalline silicon thin-film transistor in which a light blocking film, a base layer, a crystalline silicon film, a gate insulating film, and a gate electrode film arranged not to overlap at least a channel region are sequentially formed on the transparent substrate; wherein the channel region having channel length L, LDD regions having LDD length d on both sides of the channel region, a source region, and a drain region are formed in the crystalline silicon film; the light blocking film is divided across the channel region; and interval x between the divided light blocking films is equal to or larger than channel length L and equal to or smaller than a sum of channel length L and a double of LDD length d (L+2d). Thereby, the cost for manufacturing the thin-film transistor is low, and the photo leak current of the thin-film transistor is suppressed.

Abstract: An image pickup apparatus includes pixels each including a photoelectric conversion unit, an amplifying element, a first signal holding unit and a second signal holding unit both disposed in an electric path between the photoelectric conversion unit and an input node of the amplifying element, a first charge transfer unit configured to transfer electrons from the photoelectric conversion unit to the first signal holding unit, and a second charge transfer unit configured to transfer electrons from the first signal holding unit to the second signal holding unit. Voltage are set such that a voltage supplied to the first control electrode when the electrons are transferred from the photoelectric conversion unit to the first signal holding unit is lower than a voltage supplied to the second control electrode when the electrons held by the first signal holding unit are transferred to the second signal holding unit.

Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein a first dielectric layer formed over the first side of the semiconductor substrate and an interconnect layer formed over the first dielectric layer. The image sensor structure further comprises a backside illumination film formed over a second side of the semiconductor substrate and a first silicon halogen compound layer formed between the second side of the semiconductor substrate and the backside illumination film.

Abstract: In a linear image sensor 1 according to an embodiment of the present invention, a plurality of embedded photodiodes PD(n) of an elongated shape are arrayed. Each of the embedded photodiodes PD(n) comprises a first semiconductor region 10 of a first conductivity type; a second semiconductor region 20 formed on the first semiconductor region 10, having a low concentration of an impurity of a second conductivity type, and having an elongated shape; a third semiconductor region 30 of the first conductivity type formed on the second semiconductor region 20 so as to cover a surface of the second semiconductor region 20; and a fourth semiconductor region 40 of the second conductivity type for extraction of charge from the second semiconductor region 20; the fourth semiconductor region 40 comprises a plurality of fourth semiconductor regions arranged as separated in a longitudinal direction of the second semiconductor region on the second semiconductor region 20.

Abstract: In an image sensor 1 according to an embodiment of the present invention, a plurality of embedded photodiodes PD(m,n) are arrayed. Each of the embedded photodiodes PD(m,n) comprises a first semiconductor region 10 of a first conductivity type; a second semiconductor region 20 formed on the first semiconductor region 10 and having a low concentration of an impurity of a second conductivity type; a third semiconductor region 30 of the first conductivity type formed on the second semiconductor region 20 so as to cover a surface of the second semiconductor region 20; and a fourth semiconductor region 40 of the second conductivity type for extraction of charge from the second semiconductor region 20; the fourth semiconductor region 40 comprises a plurality of fourth semiconductor regions 40 arranged as separated, on the second semiconductor region 20.

Abstract: A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate.

Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.

Abstract: A CMOS detector with pairs of interdigitated elongated finger-like collection gates includes p+ implanted regions that create charge barrier regions that can intentionally be overcome. These regions steer charge to a desired collection gate pair for collection. The p+ implanted regions may be formed before and/or after formation of the collection gates. These regions form charge barrier regions when an associated collection gate is biased low. The barriers are overcome when an associated collection gate is high. These barrier regions steer substantially all charge to collection gates that are biased high, enhancing modulation contrast. Advantageously, the resultant structure has reduced power requirements in that inter-gate capacitance is reduced in that inter-gate spacing can be increased over prior art gate spacing and lower swing voltages may be used. Also higher modulation contrast is achieved in that the charge collection area of the low gate(s) is significantly reduced.

Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.

Abstract: An image pickup device, wherein a part of the carriers overflowing from the photoelectric conversion unit for a period of photoelectrically generating and accumulating the carriers may be flowed into the floating diffusion region, and a pixel signal generating unit generating a pixel signal according to the carriers stored in the photoelectric conversion unit and the carriers having overflowed into the floating diffusion region, is provided. The expansion of a dynamic range and the improvement of an image quality can be provided by controlling a ratio of the carriers flowing into the floating diffusion region to the carriers overflowing from such a photoelectric conversion unit at high accuracy.

Abstract: A solid-state image pickup unit includes: a p-type compound semiconductor layer of a chalcopyrite structure; an electrode formed on the p-type compound semiconductor layer; and an n-type layer formed separately for each pixel, on a surface opposite to a light incident side of the p-type compound semiconductor layer.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.

Abstract: According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.

Abstract: An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even in a case that the insulating film provided between adjacent pixels is formed by a coating method, there is a problem that thin portions are partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.

Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.

Abstract: A purpose of the present invention is to provide a preferable separation structure of wells when a photoelectric conversion unit and a part of a peripheral circuit unit or a pixel circuit are separately formed on separate substrates and electrically connected to each other. To this end, a solid-state imaging device includes a plurality of pixels including a photoelectric conversion unit and a amplification transistor configured to amplify a signal generated by the photoelectric conversion unit; a first substrate on which a plurality of the photoelectric conversion units are disposed; and a second substrate on which a plurality of the amplification transistors are disposed. A well of a first conductivity type provided with a source region and a drain region of the amplification transistor is separated from a well, which is disposed adjacent to the well in at least one direction, of the first conductivity type provided with the source region and the drain region of the amplification transistor.

Abstract: A device includes a device isolation region formed into a semiconductor substrate, the device isolation region having gaps for photo-sensitive devices, a dummy gate structure formed over the substrate, the dummy gate structure comprising at least one structure that partially surrounds a doped pickup region formed into the device isolation region, and a via connected to the doped pickup region.

Abstract: The present invention relates to a display device and a method of manufacturing the display device. The display device includes an insulation substrate, a gate conductor including a gate line and a gate electrode, an organic layer on the insulation substrate and the gate line, and a data conductor including a data line, a drain electrode, and a source electrode. The data line crosses the gate line. The gate electrode, the drain electrode, and the source electrode form a transistor, and a thickness of the gate electrode may be larger than a thickness of the gate line.

Abstract: A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment an isolation region comprising a first concentration of dopants is located between the photosensitive diodes. The photosensitive diodes have a second concentration of dopants that is less than the first concentration of dopants, which helps to prevent diffusion from the photosensitive diodes to form a potential path for undesired cross-talk between the photosensitive diodes.

Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.

Abstract: A solid-state imaging device includes: a first photodiode receiving light of a first color; a second photodiode that is arranged next to the first photodiode in a first direction and receives light of a second color; a third photodiode that is arranged next to the second photodiode in a second direction and receives light of the first color; a fourth photodiode that is arranged next to the third photodiode in the first direction and receives light of a third color; a first reset transistor for discharging a charge generated in the first photodiode and the second photodiode; and a second reset transistor for discharging a charge generated in the third photodiode and the fourth photodiode. The first photodiode and the third photodiode have a small difference in area.

Abstract: A method for manufacturing array substrate with embedded photovoltaic cell includes: providing a substrate; forming a buffer layer on the substrate; forming an amorphous silicon layer on the buffer layer; converting the amorphous silicon layer into a polysilicon layer; forming a pattern on the polysilicon layer; forming a first photoresist pattern on the polysilicon layer and injecting N+ ions; forming a gate insulation layer on the polysilicon layer; forming a second photoresist pattern on the gate insulation layer and injecting N? ions; forming a third photoresist pattern on the gate insulation layer and injecting P+ ions; forming a metal layer on the gate insulation layer so as to form a gate terminal; forming a hydrogenated insulation layer on the metal layer; forming a first ditch in the first insulation layer; and forming a second metal layer on the first insulation layer.

Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.

Abstract: A solid-state imaging device includes a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element, a wiring layer that is formed to be layered on the semiconductor substrate, a support substrate that is formed to be layered on the wiring layer, and a groove that is provided between a blade region in the scribe line region and the solid-state imaging element, in the semiconductor substrate and penetrates through the semiconductor substrate.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.

Abstract: In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region.

Abstract: Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end.

Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.

Abstract: A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.