Abstract: An image capturing apparatus performs a global electronic shutter operation in which a plurality of pixels are exposed during the same exposure period. In a first period, charge is accumulated by a photoelectric conversion unit. In a second period, accumulation units of a plurality of pixels accumulate charge. A ratio of saturation charge quantity of the photoelectric conversion unit to saturation charge quantity of the accumulation unit has a certain relationship with a ratio of a length of the first period to the sum of the length of the first period and the length of the second period.

Abstract: There is provided a solid state imaging device including a plurality of imaging pixels arranged two-dimensionally in a matrix configuration and phase difference detecting pixels arranged scatteredly among the imaging pixels, the solid state imaging device including: a first microlens formed for each of the imaging pixels; a planarization film having a lower refractive index than the first microlens and formed on the first microlens; and a second microlens formed only on the planarization film of the phase difference detecting pixel.

Abstract: A solid-state image sensor includes a plurality of first pixels and a plurality of second pixels. Each of the plurality of first pixels includes a first filter having a visible light transmittance higher than an infrared light transmittance, and a first photoelectric converter configured to receive visible light transmitted through the first filter, and each of the plurality of second pixels includes a second filter having an infrared light transmittance higher than a visible light transmittance, and a second photoelectric converter configured to receive infrared light transmitted through the second filter. The plurality of second pixels are divided into a plurality of groups each includes at least two second pixels. The solid-state image sensor includes a synthesizer configured to synthesize a signal from signals of the at least two second pixels included in each group.

Abstract: An apparatus includes a hardware sensor array including a plurality of pixels arranged along at least a first dimension and a second dimension of the array, each of the pixels capable of generating a sensor reading. A hardware scanning window array includes a plurality of storage elements arranged along at least a first dimension and a second dimension of the hardware scanning window array, each of the storage elements capable of storing a pixel value based on one or more sensor readings. Peripheral circuitry for systematically transfers pixel values, based on sensor readings, into the hardware scanning window array, to cause different windows of pixel values to be stored in the hardware scanning window array at different times. Control logic coupled to the hardware sensor array, the hardware scanning window array, and the peripheral circuitry, provides control signals to the peripheral circuitry to control the transfer of pixel values.

Abstract: A first voltage line supplies a constant first voltage in column circuits of an imaging device. A second voltage line supplies a second voltage that is lower than the first voltage and is constant. A third voltage line supplies a constant third voltage. A fourth voltage line supplies a fourth voltage that is lower than the third voltage and is constant. The first voltage line is electrically connected to a drain of an NMOS transistor, and the third voltage line is electrically connected to a gate of the NMOS transistor. The second voltage line is electrically connected to a drain of a PMOS transistor, and the fourth voltage line is electrically connected to a gate of the PMOS transistor.

Abstract: A pixel is formed by two or more photodiodes and at least one transfer gate. The transfer gate is configured to transfer charge from each of the photodiodes to a common sense node, such that charge from the photodiodes is combined at the common sense node.

Abstract: A pixel array has a plurality of output units arranged in matrix form and a plurality of A/D conversion units corresponds to the output units. Each of the output units outputs an electric signal based on incident electromagnetic waves. Each of the A/D conversion units converts the electric signal input from the corresponding output unit to a digital signal. A plurality of storage units corresponds to columns of the output units. Each of the storage units holds the corresponding digital signal. A first signal line is configured to supply a driving bias to at least one of the output units and the A/D conversion units. A second signal line is configured to transmit the digital signal from the A/D conversion units to the storage units. The output units are provided between the first signal line and the second signal line.

Abstract: An organic light emitting diode display including: a substrate including a pixel part for displaying an image and a peripheral part enclosing the pixel part; a plurality of scan lines formed on the substrate, each for transferring a scan signal; a plurality of data lines for transferring a data voltage, and a plurality of driving voltage lines intersecting the plurality of scan lines for transferring a driving voltage, respectively; a plurality of pixels connected to the plurality of scan lines and the plurality of data lines, respectively and formed in the pixel part; and at least one dummy pixel connected to the plurality of scan lines and the plurality of data lines and formed in the peripheral part.

Abstract: A circuit of light-emitting elements connected between two power terminals is disclosed in the present disclosure. The circuit of light-emitting elements includes a smooth conducting line, multiple light-emitting elements, and a zigzag conducting line. The smooth conducting line is connected to one of the power terminals. One terminal of each light-emitting element is electrically connected at a different position of the smooth conducting line. The zigzag conducting line is connected to the other of the power terminals, and the other terminal of each light-emitting element is electrically connected at a different position of the zigzag conducting line. Each shortest path, starting from one of the power terminals, passing through any the light-emitting element along the smooth conducting line, and ending at the other of the power terminals along the zigzag conducting line, has substantially a same resistance value.

Abstract: An organic electroluminescence display device includes a substrate; a thin film transistor that is formed on the substrate; a light emitting region that has a lower electrode, a light emitting layer, and an upper electrode formed for each of a plurality of pixels arranged in a matrix shape on the thin film transistor; and a contact hole that is formed on the outside of the light emitting region in one corner portion of the pixel and connects the thin film transistor and the lower electrode for each pixel in a plan view. Only one pair of pixels of four pixels that share an intersection point of boundaries of the pixels arranged in the matrix shape, which are arranged in a diagonal manner have the contact holes at the corner portions having the intersection point.

Abstract: In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor is prevented.

Abstract: A solid-state image sensor includes a plurality of first pixels and a plurality of second pixels. Each of the plurality of first pixels includes a first filter having a visible light transmittance higher than an infrared light transmittance, and a first photoelectric converter configured to receive visible light transmitted through the first filter, and each of the plurality of second pixels includes a second filter having an infrared light transmittance higher than a visible light transmittance, and a second photoelectric converter configured to receive infrared light transmitted through the second filter. The plurality of second pixels are divided into a plurality of groups each includes at least two second pixels. The solid-state image sensor includes a synthesizer configured to synthesize a signal from signals of the at least two second pixels included in each group.

Abstract: An apparatus includes a hardware sensor array including a plurality of pixels arranged along at least a first dimension and a second dimension of the array, each of the pixels capable of generating a sensor reading. A hardware scanning window array includes a plurality of storage elements arranged along at least a first dimension and a second dimension of the hardware scanning window array, each of the storage elements capable of storing a pixel value based on one or more sensor readings. Peripheral circuitry for systematically transfers pixel values, based on sensor readings, into the hardware scanning window array, to cause different windows of pixel values to be stored in the hardware scanning window array at different times. Control logic coupled to the hardware sensor array, the hardware scanning window array, and the peripheral circuitry, provides control signals to the peripheral circuitry to control the transfer of pixel values.

Abstract: Provided is a semiconductor device including: a multilayer substrate including an optical element; a light-transmitting plate provided on the substrate to cover the optical element; and a lens of an inorganic material provided between the substrate and the light-transmitting plate. A structure having a same strength as a strength per unit area of the lens is provided at a portion outside an effective photosensitive region where the optical element is formed, when the substrate is viewed in plan.

Abstract: An image sensor and a method for forming an image sensor are provided. The image sensor includes a substrate, and the substrate includes a pixel region, a peripheral region and a boundary region, and the boundary region is formed between the pixel region and the peripheral region. The image sensor also includes a first gate stack structure formed in the pixel region and a second gate stack structure formed in the peripheral region. The second gate stack structure includes a high-k dielectric layer and a first metal layer.

Abstract: A CMOS time-of-flight image sensor must be robust to interface traps and fixed charges which may be present due to fabrication and which may cause an undesired induced electric field in the silicon substrate. This undesired induced electrical field is reduced by introducing a hydrogen-enriched dielectric material. Further remedial techniques can include applying ultraviolet light and/or performing a plasma treatment. Another possible approach adds a passivation doping layer at a top of the detector as a shield against the undesired induced electric field. One or more of the above techniques can be used to prevent any unstable behavior of the time-of-flight sensor.

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.

Abstract: A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment, the method includes arranging an optoelectronic semiconductor chip and a reflector on a top side of a carrier film, arranging a potting material in a region between the optoelectronic semiconductor chip and the reflector and forming a molded body, wherein the optoelectronic semiconductor chip, the reflector and the potting material are embedded into the molded body.

Abstract: A solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a light sensing feature, a negative oxide layer, a gate dielectric layer and a transfer gate. The light sensing feature is configured in the substrate to detect an incoming radiation. The negative oxide layer is over the light sensing feature. The gate dielectric layer is over the negative oxide layer. The transfer gate is over the gate dielectric layer.

Abstract: The present invention introduces a separation type unit pixel of an image sensor having a three-dimensional (3D) structure, which is capable of maximizing transmission efficient of a charge generated through a photodiode to a floating diffusion area. The separation type unit pixel may include a first wafer on which a photodiode and a transmission transistor are formed and a second wafer on which a reset transistor and a source follower transistor are formed. In particular, the photodiode has a positive region to which an N_ground voltage is applied, the N_ground voltage having a lower voltage level than a ground voltage used in the second wafer.

Abstract: Pixels of image sensors are provided. The pixels may include a photo diode configured to accumulate photocharges generated therein corresponding to incident light during a first period, a storage diode configured to store photocharges accumulated in the photo diode and a storage gate configured to control transfer of the photocharges accumulated in the photo diode to the storage diode. The storage gate may include a vertical gate structure extending toward the photo diode.

Abstract: A circuit of light-emitting elements connected between two power terminals is disclosed in the present disclosure. The circuit of light-emitting elements includes a smooth conducting line, multiple light-emitting elements, and a zigzag conducting line. The smooth conducting line is connected to one of the power terminals. One terminal of each light-emitting element is electrically connected at a different position of the smooth conducting line. The zigzag conducting line is connected to the other of the power terminals, and the other terminal of each light-emitting element is electrically connected at a different position of the zigzag conducting line. Each shortest path, starting from one of the power terminals, passing through any the light-emitting element along the smooth conducting line, and ending at the other of the power terminals along the zigzag conducting line, has substantially a same resistance value.

Abstract: An imaging device includes a unit pixel cell including: a semiconductor substrate including a first region exposed to a surface of the semiconductor substrate in a first area, and a second region directly adjacent to the first region and exposed to the surface in a second area; a photoelectric converter; a contact plug connected to the second region; a first transistor including the second region as one of a source and a drain, a first electrode covering a first portion of the first area, and a first insulation layer between the first electrode and the semiconductor substrate; a second electrode covering a second portion of the first area; and a second insulation layer between the second electrode and the semiconductor substrate. When seen in a direction perpendicular to the surface, a contact between the second region and the contact plug is located between the first electrode and the second electrode.

Abstract: A solid state imaging apparatus includes an insulation structure formed of an insulation substance penetrating through at least a silicon layer at a light receiving surface side, the insulation structure having a forward tapered shape where a top diameter at an upper portion of the light receiving surface side of the silicon layer is greater than a bottom diameter at a bottom portion of the silicon layer. Also, there are provided a method of producing the solid state imaging apparatus and an electronic device including the solid state imaging apparatus.

Abstract: A complementary metal oxide semiconductor (CMOS) device includes a p-channel metal oxide semiconductor (PMOS) transistor unit and an n-channel metal oxide semiconductor (NMOS) transistor unit. A semiconductor layer of the PMOS transistor unit between source and drain electrodes thereof is divided into a first tapered region having an ion concentration of CP/e and a first flat region having an ion concentration of CP/f. A semiconductor layer of the NMOS transistor unit between source and drain electrodes thereof is divided into a second tapered region having an ion concentration of CN/e, a second flat region having an ion concentration of CN/f?2 and a third flat region located between the second tapered region and second flat region and having an ion concentration of CN/f?1, wherein the ion concentrations have a relationship of CP/e<CP/f<CN/f?2<CN/e<CN/f?1.

Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.

Abstract: The invention relates to a semiconductor structure intended to receive an electromagnetic wave. The semiconductor structure comprises at least one first semiconductor resonant optical cavity conformed to absorb at least partially the electromagnetic wave and to provide an electrical signal proportional to the part of the electromagnetic wave absorbed. The semiconductor structure further includes a second dielectric resonant optical cavity of which a resonance wavelength is comprised in the predetermined range of wavelengths and is preferentially equal to the wavelength ?0, the second resonant optical cavity being laid out to intercept at least part of the electromagnetic wave and being optically coupled to the first resonant optical cavity. The second resonant optical cavity is transparent to the predetermined range of wavelengths. The invention further relates to a semiconductor component comprising such a semiconductor structure and a method of manufacturing such a semiconductor structure.

Abstract: A light-emitting device and a lighting device each of which includes a plurality of light-emitting elements exhibiting light with different wavelengths are provided. The light-emitting device and the lighting device each have an element structure in which each of the light-emitting elements emits only light with a desired wavelength, and thus the light-emitting elements have favorable color purity. In the light-emitting element emitting light (?R) with the longest wavelength of the light with different wavelengths, the optical path length from a reflective electrode to a light-emitting layer (a light-emitting region) included in an EL layer is set to ?R/4 and the optical path length from the reflective electrode to a semi-transmissive and semi-reflective electrode is set to ?R/2.

Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.

Abstract: In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor is prevented.

Abstract: An image sensor including a first semiconductor region of a first conductivity type that is arranged in a substrate, a second semiconductor region of a second conductivity type that is arranged in the first semiconductor region to form a charge accumulation region. The second semiconductor region includes a plurality of portions arranged in a direction along a surface of the substrate. A potential barrier is formed between the plurality of portions. The second semiconductor region is wholly depleted by expansion of a depletion region from the first semiconductor region to the second semiconductor region. A finally-depleted portion to be finally depleted, of the second semiconductor region, is depleted by the expansion of the depletion region from a portion of the first semiconductor region, located in a lateral direction of the finally-depleted portion.

Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.

Abstract: A frontside illuminated (FSI) image sensor with a reflector is provided. A photodetector is buried in a sensor substrate. A support substrate is arranged under and bonded to the sensor substrate. The reflector is arranged under the photodetector, between the sensor and support substrates, and is configured to reflect incident radiation towards the photodetector. A method for manufacturing the FSI image sensor and the reflector is also provided.

Abstract: A pixel array including an SixGey layer disposed on a first semiconductor layer. A plurality of pixels is disposed in the first semiconductor layer. The plurality of pixels includes: (1) a first portion of pixels separated from the SixGey layer by a spacer region and (2) a second portion of pixels including a first doped region in contact with the SixGey layer. The pixel array also includes pinning wells disposed between individual pixels in the plurality of pixels. A first portion of the pinning wells extend through the first semiconductor layer. A second portion of the pinning wells extend through the first semiconductor layer and the SixGey layer.

Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of isolation structures are each disposed between two respective radiation-sensing regions. The isolation structures protrude out of the second side of the substrate.

Abstract: A photoelectric conversion device includes a substrate having a first surface and a second surface that is an opposite side of the first surface, wherein one of the first and second surfaces is a light incidence surface, a photodiode (PD) formed in the first surface of the substrate, a reflective layer formed on one of the first and second surfaces of the substrate, which is the opposite side of the light incidence surface, and a microlens formed on the light incidence surface of the substrate.

Abstract: An image sensor may include a substrate having a photoelectric conversion element and a grid pattern formed over the substrate and having a flat upper surface, a first side surface, and a second side surface, wherein the first side surface and the second side are located opposite to each other. A first internal angle is formed between the flat upper surface and the first side surface, a second internal angle is formed between the flat upper surface and the second side surface, and the first internal angle may be smaller than the second internal angle.

Abstract: Visual and near infrared pixels may have deep photodiodes to ensure sufficient capture of light. The pixels may have a silicon layer that is etched to form a microlens for the pixel. The pixels may include an inversion layer formed over the silicon layer to prevent dark current. Additionally, the pixels may include a conductive layer formed over the inversion layer that further prevents dark current. The conductive layer may be coupled to a bias voltage supply line. The conductive layer may be biased during image acquisition to prevent dark current. During readout, the bias voltage may be pulsed at a lower voltage to ensure all of the collected charge is transferred out of the photodiode during charge transfer.

Abstract: An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed.

Abstract: There is configured a solid-state image pickup unit including a photoelectric conversion section formed on a light incident side of a substrate; a first charge accumulation section accumulating a signal charge generated by the photoelectric conversion section; a second charge accumulation section formed in a region other than a light-condensing region where incident light is condensed in the substrate on a side opposite to a light incident side and formed to be laminated together with the first charge accumulation section in a depth direction of the substrate; and a floating diffusion section formed in a region other than the light-condensing region in the substrate on the side opposite to the light incident side and converting the signal charge into a voltage.

Abstract: An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed.

Abstract: An imaging device which is capable of taking images with high quality and can be manufactured at low cost is provided. A first circuit includes a first transistor and a second transistor and a second circuit includes a third transistor and a photodiode. The first transistor and the third transistor are each an n-channel transistor including an oxide semiconductor layer as an active layer, and the second transistor is a p-channel transistor including an active region in a silicon substrate. The photodiode is provided in the silicon substrate. A region in which the first transistor and the second transistor overlap each other with an insulating layer positioned therebetween is provided. A region in which the third transistor and the photodiode overlap each other with the insulating layer positioned therebetween is provided.

Abstract: An imaging system may include an image sensor package with through-oxide via connections between the image sensor die and the digital signal processing die in the image sensor package. The image sensor die and the digital signal processing die may be attached to each other. The through-oxide via may connect a bond pad on the image sensor die with metal routing paths in the image sensor and digital signal processing dies. The through-oxide via may simultaneously couple the image sensor die to the digital signal processing die. The through-oxide via may be formed through a shallow trench isolation structure in the image sensor die. The through-oxide via may be formed through selective etching of the image sensor and digital signal processing dies.

Abstract: An oxide semiconductor film and an oxide conductive film are stacked to form a semiconductor layer. The oxide conductive film is made of a material by which the oxide conductive film is etched at a higher speed than the oxide semiconductor film for example with a PAN chemical containing phosphoric acid, nitric acid, and acetic acid. A source electrode and a drain electrode are electrically connected to the oxide semiconductor film through the oxide conductive film at least at an end portion of the source electrode and an end portion of the drain electrode facing each other. A channel region made of the oxide semiconductor film is formed between the source electrode and the drain electrode. The oxide semiconductor film has a substantially tapered shape in cross section at an end face thereof.

Abstract: A solid-state imaging device includes: a light-receiving pixel part configured to be formed on a semiconductor substrate; a black-level reference pixel part configured to be formed on the semiconductor substrate; and a multilayer interconnect part configured to be provided over the semiconductor substrate. The multilayer interconnect part includes an insulating layer formed over the semiconductor substrate and metal interconnect layers formed as a plurality of layers in the insulating layer. The multilayer interconnect part has a first light-blocking film formed above an area between first metal interconnects of a first metal interconnect layer as one of the metal interconnect layers above the black-level reference pixel part, and a second light-blocking film that is connected to the first light-blocking film and is formed of a second metal interconnect layer over the first metal interconnect layer.

Abstract: A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a source/drain layer on the counter-doped layer, forming one or more vertical fins on the source/drain layer, removing a portion of the source/drain layer to form one or more bottom source/drains below each of the one or more vertical fins, reacting an exposed portion of each of the one or more bottom source/drains with a reactant to form a disposable layer on opposite sides of each bottom source/drain and a condensation layer between the two adjacent disposable layers, and removing the disposable layers.

Abstract: A first waveguide member is formed, as viewed from above, in an image pickup region and a peripheral region of a semiconductor substrate. A part of the first waveguide member, which part is disposed in the peripheral region, is removed. A flattening step is then performed to flatten a surface of the first waveguide member on the side opposite to the semiconductor substrate.

Abstract: A system for digital imaging in a light deficient environment includes an emitter for providing illumination with electromagnetic pulses. The system includes an image sensor that creates image data from the electromagnetic pulses. The image sensor has a plurality of subsets of differing pixels, where each of the pixels comprises a transfer gate transistor. Each transfer gate transistor in one subset of pixels is electrically connected by a TX signal. The TX signal provides global operation of transfer gate transistor (TX) per subset of pixels. The system includes a memory comprising instructions for controlling the emitter so as to pulse for a plurality of exposures that correspond to the subsets of differing pixels and instructions that coordinate the electromagnetic pulses being emitted during a blanking portion of the image sensor frame period. The system includes a processor that combines a plurality of exposures to expand dynamic range.

Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.