Abstract: In a semiconductor memory including a dynamic random access memory, a memory cell of the dynamic random access memory includes: a semiconductor pillar (a silicon pillar); a capacitor in which one side of the silicon pillar is used as a charge accumulation electrode; and a longitudinal insulated gate static induction transistor in which the other side of the silicon pillar is used as an active region (a source region, a channel formation region and a drain region), and a bit line is connected to the silicon pillar.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: In a peripheral circuit region of a DRAM, two connection holes 17a, 17b for connecting a first layer line 14 and a second layer line 26 electrically are opened separately in two processes. After forming the connection holes 17a and 17b, plugs 18a and 215a are formed in the connection holes 17a and 17b, respectively.

Abstract: A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Abstract: There is proposed a vertical cell transfer transistor comprising a channel region constituted by a monocrystalline silicon layer which is formed by way of epitaxial growth, source-drain regions constituted by n-type diffusion regions which are formed over and below the monocrystalline silicon layer, and an embedded type gate electrode constituted by a word line. In this case, the surface of the insulating film is made flush with the top surface of the n-type diffusion region, i.e. substantially flat and hence free from a stepped portion.

Abstract: A method for forming a contact capable of tolerating an O2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxygen sink spacers and layers. These oxygen sink spacers and layers are oxidized before the metal layer at the bottom of the plug is oxidized. Accordingly, the conductive connection between the polysilicon and any device built on top of the barrier layer is preserved.

Abstract: A three-dimensional semiconductor device includes a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits to control a portion of the circuit blocks.

Abstract: An active matrix organic electroluminescence display device and a method of fabricating the same are disclosed in the present invention. The device includes gate and data lines defining a pixel region on a substrate, a switching thin film transistor connected to the gate and data lines, a driving thin film transistor connected to the switching thin film transistor, a power line connected to the driving thin film transistor, a transparent first capacitor electrode connected to and overlapping the power line, a second capacitor electrode connected to the driving thin film transistor, and a pixel electrode formed at the pixel region and connected to the driving thin film transistor.

Abstract: An etch stopper member is formed under a cell plate electrode so as to surround an active region along a periphery of the cell plate electrode. The etch stopper member is formed from a material that is resistant to an etchant of a first interlayer insulating film. For example, a dummy gate line and a cylindrical wall formed thereon are provided as the etch stopper member. Either the dummy gate line or the cylindrical wall may be provided as the etch stopper member. The etch stopper member prevents the interlayer insulating film from being laterally etched at the boundary between a DRAM memory section and a logic section. This eliminates the need to provide an etching margin, allowing for reduction in the area of the DRAM memory section.

Abstract: A non-volatile semiconductor memory device has, at a main surface of a semiconductor substrate, an uneven shape with recesses and protrusions repeated continuously and alternately and further includes a source diffusion layer region having a source region formed from an upper surface of each protrusion to the depth direction of the semiconductor substrate and a source diffusion layer interconnection formed from a bottom surface of the recess to the depth direction of the semiconductor substrate when the semiconductor substrate is viewed two-dimensionally. The depth of the bottom surface of the source region from the upper surface of the protrusion is made equal to or larger than the depth of the bottom surface of the recess from the upper surface of the protrusion. Thus, a non-volatile semiconductor memory device is provided which is suitable for miniaturization and in which resistance of the source diffusion layer region can easily be lowered.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: A nonvolatile semiconductor storage device has a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate, and a first diffusion layer and a second diffusion layer formed in the surface of the semiconductor substrate on opposite sides of the gate electrode, a channel region being formed between the first and second diffusion layers. A first insulating layer, isolated pieces of material and a second insulating layer are formed in order in a multilayer structure on the surface of the semiconductor substrate on the channel region.

Abstract: To simplify a method for manufacturing a memory device having a multiplicity of MRAM cells in a crossing area of conductor elements, a method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a plurality of memory cells includes the step of structuring each of the memory elements simultaneously with the structuring of the first and second conductor elements.

Abstract: The invention relates to a phase-change memory device. The device includes a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode. Additionally, other isolated lower electrodes may be formed along a symmetry line that is orthogonal to the first two isolated lower electrodes. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation structure s around a memory cell structure diode stack.

Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: A p type well region, a field insulation film, a gate insulation film, and a gate-use poly-Si layer are formed on the surface of a silicon substrate, after which a laminate of a silicon nitride layer and a resist layer is used as a mask in ion implantation, which forms a low-concentration source region, Source contact region, drain region, and drain contact region. Side spacers are formed on both side walls of the gate-use poly-Si layer, after which the laminate of the gate-use poly-Si layer, the side spacers, and the gate insulation film is used along with the field insulation film as a mask to perform ion implantation via the silicon nitride layer, which forms a high-concentration source region and drain region. After a silicide conversion treatment, the unreacted metal is removed, which forms a silicide layer.

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A lateral MOS transistor including a gate and drain and source regions of a first conductivity type formed in a substrate of a second conductivity type connected to a first power supply, wherein a doped buried layer of the first conductivity type extends under said drain region and under a portion of the gate, the buried layer being connected to the gate via a one-way connection.

Abstract: The invention reduces capacitor coupling between data read bit lines and data write bit lines to thereby prevent error detection of data. A first pair of bit lines BM and {overscore (BM)} that read data from a specified one of memory cells in a memory cell column and a second pair of bit lines BS and {overscore (BS)} that write data in another specified one of the memory cells in the memory cell column are formed in different layers through an interlayer dielectric film. As viewed in a plan view, the space between the first pair of bit lines BM and {overscore (BM)} is wider than the second pair of bit lines BS and {overscore (BS)}, and the second pair of bit lines BS and {overscore (BS)} are disposed between the first pair of bit lines BM and {overscore (BM)}. A first wiring layer that is set a ground potential is disposed in the same layer as the first pair of bit lines BM and {overscore (BM)} and between the first pair of bit lines BM and {overscore (BM)}.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: A semiconductor device and method for manufacturing the same in which the semiconductor device includes a substrate; an MOS transistor formed on the substrate; an interlayer dielectric provided on at least a portion of the MOS transistor; a hydrogen occluding material which is an interstitial hydrogen occluding compound, which is provided on the interlayer dielectric, and which is employed as a wire by being disposed in the vicinity of the top of the MOS transistor; and a ferroelectric capacitor which has a height which is greater than that of the MOS transistor, wherein the hydrogen occluding material is placed between the MOS transistor and the ferroelectric capacitor.

Abstract: An electrically writeable, optically readable, ferroelectric memory cell for nonvolatilely storing a single bit. The memory cell has an optically polarizeable translucent ferroelectric layer located between first and second translucent metal layers. The metal layers are used to electrically write an optical polarization state into the translucent ferroelectric layer. A translucent insulator layer, wire grid polarizer, a second translucent insulator layer and light sensing diode region are, in turn, attached to the second translucent metal layer. A polarized light beam, from a light source, is shone onto the first translucent metal layer, in order to optically read out the optical polarization state of the translucent ferroelectric layer of the memory cell. Alternately, two such memory cells can be used together in order to store a single bit.

Abstract: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. An adhesion layer is formed over at least a portion of the surface. The adhesion layer is formed of RuSixOy, where x and y are in the range of about 0.01 to about 10. The adhesion layer may be formed by depositing RuSixOy by chemical vapor deposition, atomic layer deposition, or physical vapor deposition or the adhesion layer may be formed by forming a layer of ruthenium or ruthenium oxide over a silicon-containing region and performing an anneal to form RuSixOy from the layer of ruthenium and silicon from the adjacent silicon-containing region. Capacitor electrodes, interconnects or other structures may be formed with such an adhesion layer. Semiconductor structures and devices can be formed to include adhesion layers formed of RuSixOy.

Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fi

Abstract: A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

Abstract: A semiconductor memory device includes: a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode; a selection transistor formed at the substrate; an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; and a diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor. The diffusion barrier film is a TaxSi1−xNy film or a HfxSi1−xNy film (where 0.2<x<1 and 0<y<1). The lower electrode includes an Ir film and an IrO2 film which are sequentially formed.

Abstract: A MOS capacitor used in an active matrix liquid crystal display is manufactured by a process comprising the steps of forming capacitor electrodes with a dielectric layer between them in a semiconductor layer, forming a p+ diffused region and an n+ diffused region adjacent to the capacitor electrodes in the semiconductor layer, and making a complementary connection between the regions.

Abstract: Methods of forming integrated circuit capacitors having dielectric layers therein that comprise ferroelectric materials, include the use of protective layers to block the infiltration of hydrogen into the ferroelectric material. By blocking the infiltration of hydrogen, the hysteresis characteristics of the ferroelectric materials can be preserved. A preferred integrated circuit capacitor comprises a semiconductor substrate and a lower capacitor electrode on the semiconductor substrate. A capacitor dielectric layer that comprises a ferroelectric material, is provided on the lower capacitor electrode. An upper capacitor electrode is also provided on the capacitor dielectric layer. In order to inhibit degradation of the ferroelectric characteristics of the capacitor dielectric layer, a protective layer is utilized to cover the capacitor dielectric layer. In particular, the protective layer is formed to encapsulate the upper capacitor electrode and the capacitor dielectric layer.

Abstract: A semiconductor device suppressing increase of the number of types of exposure mask for implantations, preventing complication of manufacturing steps and suppressing the manufacturing cost and manufacturing steps therefor are provided. An impurity implantation region (R81) is formed by first implantation with an exposure mask for implantation having an opening at the lower right and this exposure mask for implantation is turned over for forming another impurity implantation region (R82) by second implantation, thereby forming three types of impurity implantation regions including the impurity implantation region (R81) formed through the first implantation, the impurity implantation region (R82) formed through the second implantation and still another impurity implantation region (R83) formed through the first implantation and the second implantation. Four types of regions inclusive of a region (R84) not subjected to impurity implantation can be formed with a single type of exposure mask for implantation.

Abstract: A read gate of a DRAM core cell includes first and second N channel MOS transistors having gates connected to a pair of bit lines through first and second nodes, respectively, and third and fourth MOS transistors having gates both of which receive a column selecting signal, with gate oxide films of the third and the fourth N channel MOS transistors being formed to be thinner than gate oxide films of the first and the second N channel MOS transistors. It is accordingly possible to lower an amplitude voltage of the column selecting signal, thereby enabling reduction of electric current consumption and speed-up of an operating rate of the DRAM core cell.

Abstract: The present invention provides a semiconductor memory device in which a first insulation film and a second insulation film are laminated on a source and a drain of an access transistor to form a laminated insulation film, wherein the first insulation film is the same as an insulation film used as a sidewall for a logic transistor, and the second insulation film is the same as an encircling insulation film encircling the sidewall. Furthermore, the top surface of the laminated insulation film is positioned at substantially the same height as that of a silicide film on a gate electrode of the access transistor. On the other hand, a method for fabricating a semiconductor memory device according to the present invention polishes a logic region and a memory cell region together so as to expose gate electrodes of a logic transistor and an access transistor, and further polishes a laminated insulation film on a source and a drain of the access transistor.

Abstract: Improved pixel circuits are disclosed for high fill-factor large area imager systems using continuous (e.g., amorphous silicon) sensor layers. A first approach prevents crosstalk by ensuring that each pixel is not able to go into saturation. A second approach employs a cascode transistor to maintain the bias of the sensor contact at a constant potential regardless of illumination condition. These two approaches may be combined. A resistive film connecting the pixel contacts may be used in conjunction with the second approach to prevent aliasing of signal and noise.

Abstract: Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive layer of a semiconductor structure. A layer of an inhibiting substance may be used to inhibit a net flow of atoms so as to maintain conductivity between the metallization layer and the conductive layer of the semiconductor structure. Such layer of inhibiting substance acts even with the presence of point defects for a given temperature.

Abstract: Briefly, in accordance with one embodiment of the invention, a memory device package includes an integrated circuit die having a memory array and at least one passive component mounted to the integrated circuit component.

Abstract: A ferroelectric memory includes first and second plugs respectively connected to one and the other of source/drain regions of the transistor formed on a semiconductor wafer. A first capacitor electrode is connected to the first plug and located at a position above the transistor. The first capacitor electrode includes first and second capacitor faces on the second plug side and a side reverse thereto, respectively. A ferroelectric film is disposed on the first capacitor face. A second capacitor electrode is connected to the second plug and located at a position above the transistor. The second capacitor electrode is disposed on the first capacitor face through the ferroelectric film.

Abstract: Integrated memory circuits, key components in thousands of electronic and computer products, have recently been made using ferroelectric memory transistors, which offer faster write cycles and lower power requirements than over conventional floating-gate transistors. One problem that hinders the continued down-scaling of conventional ferroelectric memory transistors is the vulnerability of their gate insulations to failure at thinner dimensions. Accordingly, the inventors devised unique ferroelectric gate structures, one of which includes a high-integrity silicon-oxide insulative layer, a doped titanium-oxide layer, a weak-ferroelectric layer, and a control gate. The doped titanium-oxide layer replaces a metal layer in the conventional ferroelectric gate structure, and the weak-ferroelectric layer replaces a conventional ferroelectric layer.

Abstract: A method for forming a contact capable of tolerating an O2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxygen sink spacers and layers. These oxygen sink spacers and layers are oxidized before the metal layer at the bottom of the plug is oxidized. Accordingly, the conductive connection between the polysilicon and any device built on top of the barrier layer is preserved.

Abstract: A method for producing a laminate having resin layers and thin metal layers by repeating a process unit comprising a step of laminating a resin layer by applying a resin material, a step of depositing a patterning material on the resin layer and a step of laminating a thin metal layer, predetermined times on a turning support (511), wherein the patterning material is stuck on the surface of the resin layer in a noncontact way. A laminate comprising a large number of laminate units each comprising a resin layer and a thin metal layer divided at an electric insulation stripe part can be produced stably. The laminate is applicable to production of a high performance small capacitor at low cost.

Abstract: By depositing a diffusion prevention film 7 constructed of an oxide of aluminum containing barium and heat-treating the diffusion prevention film 7 in the atmosphere of a mixed gas of oxygen and carbon dioxide, carbon dioxide is made to adsorb to the barium contained in the diffusion prevention film 7. The diffusion prevention film can effectively restrain the permeation of hydrogen and has an excellent hydrogen barrier property. By using the diffusion prevention film for a capacitor, a high-yield semiconductor storage device having the capacitor of a stable ferroelectric characteristic or high dielectric characteristic can be obtained.

Abstract: A data input/output line structure having reduced resistance for a semiconductor memory device includes a first signal line formed from a first metal layer, the first signal line being connected to a bit line of a memory cell; a second signal line formed from a second metal layer, the second signal line being arranged parallel to the first signal line; and a plurality of strapping connectors for connecting the first signal line and the second signal line. The first and the second signal lines having first and second resistances, respectively, wherein the second resistance is lower than the first resistance.

Abstract: A word line and a cell plate electrode line are formed at a common interconnection layer. A redundant replacement unit for a faulty row is set corresponding to the cell plate electrode line. For each redundant replacement unit, a program element is arranged for stopping supply of a cell plate voltage from the cell plate voltage line to the cell plate electrode line. The program element corresponding to the cell plate electrode line short-circuited to the word line nonvolatilely changes from the on state to the off state in response to an externally supplied input instruction.

Abstract: A semiconductor device of the present invention includes capacitors made up of a lower electrode, a capacitive insulation film made from metal oxide material, provided on one surface of a semiconductor substrate. An ozone TEOS film is provided on these capacitors, and a protective film for covering the upper surfaces of the capacitors is then provided on this ozone TEOS film. An interlay insulation film that is thicker than the ozone TEOS film is provided on the protective film for covering the upper surfaces of the capacitors. In this way, the present invention prevents degradation in film quality of the capacitive insulation film due to mutual reaction etc. As a result, it becomes possible to provide a capacitor using an insulating film made of a metal oxide as a capacitive insulation film, having a protective film for sufficiently preventing diffusion of H2, a semiconductor device having high reliability, and a method of manufacturing such a semiconductor device, are provided.

Abstract: A liquid crystal device, which is an example of an electro-optical device, includes a TFT, a data line, a scanning line, a second capacitor electrode, and a pixel electrode, all formed on a TFT array substrate. The pixel electrode and the TFT are electrically connected to each other via a conductive layer and via two contact holes. A second storage capacitor is formed between the second capacitor electrode and a part of the conductive layer, wherein a part of a second insulating thin film is disposed between the second capacitor electrode and the part of the conductive layer. The second insulating thin film is formed of an oxide film obtained by oxidizing the scanning line and the second capacitor electrode.

Abstract: A method for forming a capacitor by stacking impurity-doped polysilicon layers having different concentrations to form a bottom electrode, treating surfaces of the bottom electrode to prevent a low dielectric constant material from being generated on the surface of the bottom electrode, and forming a dielectric layer and a top electrode on the bottom electrode.

Abstract: A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends laterally beyond the edges of the hydrogen barrier layer. The sacrificial segment absorbs hydrogen so that it cannot diffuse laterally into the protected segment of the ferroelectric thin film. After it absorbs hydrogen, the sacrificial segment is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate compound helps to reduce hydrogen degradation of the ferroelectric properties.

Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising (A) a bit line, (B) a transistor for selection, (C) memory units in the number of N, each memory unit including memory cells in the number of M wherein N≧2 and M≧2, and (D) plate lines in the number of M×N, in which the memory units in the number of N are stacked through an insulating interlayer, each memory cell includes a first electrode, a ferroelectric layer and a second electrode, the first electrodes are in common in each memory unit, and the common first electrode is connected to the bit line through the transistor for selection, and the second electrode of the m-th memory cell in the n-th memory unit is connected to the [(n−1)M+m]-th plate line wherein m=1, 2 . . . M and n=1, 2 . . . N.

Abstract: A semiconductor device includes a contact plug formed in a first interlayer insulating film on a semiconductor substrate, a second interlayer insulating film formed on the first interlayer insulating film and having an opening formed therein to reach the first interlayer insulating film, a liner film formed on the bottom and side surfaces of the opening, a capacitor lower electrode of a stacked capacitor formed to be at least partly filled in the opening, the capacitor lower electrode being formed in contact with the first and second interlayer insulating films with the liner film disposed therebetween, a capacitor insulating film formed on the capacitor lower electrode, and a capacitor upper electrode formed on the capacitor insulating film. The capacitor lower electrode is formed of a platinum group material and the capacitor insulating film is formed of a high-dielectric-constant material.

Abstract: A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit lines. Each of the memory cells includes a pillar of semiconductor material which extends outward from the substrate. A storage node plug extends from a storage node through the pillar to a storage node contact and one of a drain and a source of a MOS transistor. A bit line plug extends from the bit line inwardly to the outer surface of the pillar to form a bit line contact and the other of the drain and the source of the MOS transistor. A word line plug extends from the word line through the pillar and a portion of the word line plug forms a gate of the MOS transistor. The storage node plug, bit line plug, and word line plug can be formed asymmetrically as substantially solid, unitary structures having a desired thickness for ease in manufacturing.