Abstract: The non-volatile semiconductor memory device has a booster including a capacitor, and a storage circuit including a storage element. The capacitor has a lower electrode, a capacitor capacitance insulating film and an upper electrode. The lower electrode of the capacitor is shaped to have an increased surface area.

Abstract: A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a substrate having a trench therein, a buried bit-line in the substrate crossing the trench, a word-line covering at least the trench and crossing over the buried bit-line, and a charge trapping layer between the substrate and the word-line.

Abstract: In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.

Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.

Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors.

Abstract: A memory cell array of the non-volatile semiconductor memory device includes a plurality of gate electrodes provided in the row direction, bit lines D1, D2, D3, D4 and source lines S1, S2, S3, S4 provided in the column direction, and memory cells each having a floating gate. The source lines are separately provided in at least two wiring layers. The source line S2 provided in the first layer overlaps the source line S1 provided in the second layer when viewed two-dimensionally. This array structure reduces the dimension of the memory cell array in the row direction, thereby enabling significant reduction in area.

Abstract: A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

Abstract: A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.

Abstract: A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.

Abstract: A memory device including at least one pair of spaced apart conductors and a ferroelectric material between the pair of conductors. The pair of conductors is spaced apart a distance sufficient to permit a tunneling current therebetween.

Abstract: A semiconductor power module capable of efficiently utilizing the performance of the module and facilitating management of the module in custody. The semiconductor power module having one or more semiconductor power switching elements and a drive unit is provided with a non-volatile memory for storing use history of the module and a drive unit. The use history contains information of one of the number of switching times of the semiconductor power switching element, the number of over-current detections of the semiconductor power switching element and a temperature rise of the semiconductor power module.

Abstract: The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.

Abstract: A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.

Abstract: A method of forming resistance changing elements with improved operational characteristics for use in memory devices and the resulting structures are disclosed. A chalcogenide glass having the formula (Gex1Se1−x1)1−y1Agy1, wherein 18≦x1≦28, or the formula (Gex2SE1−x2)1−y2Agy2, wherein 39≦x2≦42, and wherein in both the silver is in a concentration which maintains the germanium selenide glass in the glass forming region is used in a memory cell. The glass may also have a glass transition temperature (Tg) near or higher than typical temperatures used for fabricating and packaging memory devices containing the memory cell.

Abstract: A semiconductor integrated circuit device has a first LT fuse group for storing replacement information used in a memory array; a second LT fuse group for storing confirmation information to confirm whether the first LT fuse group has accurately stored the replacement information; and an input/output port for outputting information PI actually stored in the first LT fuse group and information CI actually stored in the second LT fuse group to an external memory tester. The first and second LT fuse groups are fabricated according to the same conditions, and the laser input to the respective group is set to be under the same conditions.

Abstract: A semiconductor memory device of the present invention includes: a semiconductor substrate; a memory cell capacitor for storing data, including a first electrode provided above the semiconductor substrate, a capacitance insulating film formed on the first electrode, and a second electrode provided on the capacitance insulating film; a step reducing film covering an upper surface and a side surface of the memory cell capacitor; and an overlying hydrogen barrier film covering the step reducing film.

Abstract: An active anti-ESD pod for transporting photomask (reticle) comprises six body portions delimiting the container, an electrically conducting plate on the top portion, and an electrically conducting handle connected to the plate. An active charge sinker combined with a tag identifying the container or placed onto the photomask itself is provided to absorb the static electricity and to thus prevent charge accumulation that may otherwise cause ESD damage to the photomask.

Abstract: An improved buried strap method in the fabrication of a DRAM integrated circuit device where the active area is self-aligned to the deep trench in the length direction only is described. An etch stop layer is provided on a substrate. A deep trench is etched into the substrate not covered by the etch stop layer and filled with a silicon layer to form a deep trench capacitor. A polysilicon layer is deposited over the capacitor to form a buried strap. A liner layer is deposited over the etch stop layer and the buried strap having the same material as the etch stop layer. A hard mask material is deposited over the liner layer and etched where it is not covered by a mask wherein etching stops at the liner layer. The liner layer and the etch stop layer are etched away where they are not covered by the hard mask layer to form an etch stop frame. The substrate and the deep trench are etched into where they are exposed by the hard mask and the etch stop frame to form isolation trenches.

Abstract: To provide an IC chip for contactless IC card that ensures reliabilities such as data retention of nonvolatile memory and reduces power consumption. Power supply voltages VDD and VSS, which are output from a rectifier circuit, are used as a power supply for driving an analog circuit, digital circuit, and memory control circuit to cause them to operate at low voltages. A booster circuit is provided for generating a power supply voltage VDDM, which is a boost voltage, to drive a memory circuit. Because the memory circuit can be operated at the same, high voltage and the other circuits can be operated at lower voltages than voltages that would be used in a case where the analog circuit, digital circuit, memory control circuit and memory circuit are driven by a common power supply, power consumption can be reduced.

Abstract: A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.

Abstract: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

Abstract: The present invention provides a programmable element that can be programmed using relatively low-voltages (less than about 5 V) for use in one time programmable non-volatile memory storage or other high-density application. The low-voltage programmable element is a field effect transistor (FET) device that includes source and drain elements, which are separated by a channel region, and a gate region, present atop a portion of the channel region. The source and drain elements are not located beneath the gate region and the FET includes no extension implant regions present therein.

Abstract: Metal nitride compound powder substrate for capacitor anodic oxide film and the substrate interface therebetween, characterized, relative to un-nitrided analogs, by reduced temperature bias and frequency dependencies of capacitance, the substrate-anodic oxide interface being substantially insensitive to heating compared to the un-nitrided analog.

Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gage dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.

Abstract: A non-volatile semiconductor memory device has, at a main surface of a semiconductor substrate, an uneven shape with recesses and protrusions repeated continuously and alternately and further includes a source diffusion layer region having a source region formed from an upper surface of each protrusion to the depth direction of the semiconductor substrate and a source diffusion layer interconnection formed from a bottom surface of the recess to the depth direction of the semiconductor substrate when the semiconductor substrate is viewed two-dimensionally. The depth of the bottom surface of the source region from the upper surface of the protrusion is made equal to or larger than the depth of the bottom surface of the recess from the upper surface of the protrusion. Thus, a non-volatile semiconductor memory device is provided which is suitable for miniaturization and in which resistance of the source diffusion layer region can easily be lowered.

Abstract: In a non-volatile semiconductor memory device, three-layered structure of the first, second and third floating gate electrodes is implemented, and stepped portions are provided on the first interlayer insulating film surrounding the first floating gate electrode. The position of the bottom surface of the second floating gate electrode can be disposed higher than that of the upper surface of the first floating gate electrode. Consequently, compared with overlapping area of the floating gate electrode with a control gate electrode in a conventional non-volatile semiconductor device, it can be increased by the length of stepped portions on the first interlayer insulating film. Film thickness as floating gate electrode will not be as thick as conventional structures. Overlapping area of the floating gate electrode with the control gate electrode can be sufficiently secured without a portion with the maximum film thickness of floating gate electrode being larger.

Abstract: In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

Abstract: A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

Abstract: A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hole. This invention prevents contact resistance of a bottom electrode and a plug from increasing as well as implementing high-speed operation and improving the reliability of the semiconductor device.

Abstract: Lead interconnection layers and are electrically connected to the respective source and drain regions of a pair of a monitor transistor MT. Lead interconnection layers and are both formed on same insulating layer and on same insulating layer as is a bit line conductive layer of a memory cell area. Furthermore, lead interconnection layers and have respective contact sections each with a large width and to each of which a needle of a probe can be connected externally. With such a structure adopted, there can be obtained a semiconductor device capable of monitoring a transistor characteristic correctly and easily by reducing parasitic resistance, further, at an early stage in a wafer process; and a fabrication process therefor.

Abstract: A semiconductor device with a transistor having a first impurity region, a second impurity region, and a gate electrode formed on a semiconductor substrate. The semiconductor device also includes a first insulating film covering the transistor, and a capacitor formed on the first insulating film. The capacitor includes a dielectric film formed of either ferroelectric material or high dielectric material, and an upper electrode and a lower electrode positioned to put the dielectric film therebetween. A second insulating film is formed on the capacitor, and a wiring layer is formed on the second insulating film. A nitride film covers the wiring layer and a first silicon oxide film formed on the nitride film includes nitrogen at least at the surface thereof.

Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Abstract: A memory cell includes a MOS transistor having a source region, a drain region and a gate electrode, a ferroelectric film formed on the source region of the MOS transistor via an insulating film and an electrode formed on the ferroelectric film. The memory cell can be composed of a smaller number of elements while preventing data corruption and disturbance at the time of readout.

Abstract: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract: A conductive plug is formed in an interlayer insulation film and on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects a pair of active regions of the semiconductor elements formed on the different sides of the isolating layer. Alternatively, a conductive plug is formed in an interlayer insulation film and on a conducive line formed on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects the conductive line and an active region of the semiconductor element.

Abstract: A semiconductor device and a method of producing the semiconductor device, fabricated by forming a memory device and a logic device on a single semiconductor substrate, are provided. A side wall (9) and a silicide protection film (10) of a gate electrode (7e) are used instead of forming a silicide protection film in a logic device region (101), whereby the number of steps in forming a logic process consolidating device can be reduced. Further, high concentration impurity regions are formed using the silicide protection film (10) as a mask, whereby a degree of freedom of a condition of implanting ions becomes high.

Abstract: A magnetic random access memory with write and read circuits using magnetic tunnel junction (MTJ) devices wherein MTJs are arranged at cross points of word lines and read bit lines to form memory cells. After write bit lines and read bit lines are arranged parallel to each other, current bypass paths are formed allowing current to bypass the side and bottom of the MTJ. Thus, an electric field having intensity enough to change the magnetization direction of the MTJ, is applied only to each selected cell. In a write operation, the magnetization direction of a free layer in the MTJ is formed to be parallel or antiparallel to the magnetization direction of a pinned ferromagnetic layer by the current passing through the word line and the current bypass path.

Abstract: A memory device and method in which the capacitor lower electrode within the memory cell array and a first interconnection layer within the peripheral circuitry are provided simultaneously from the same conductive material. The capacitor upper electrode and a second interconnection layer within the peripheral circuitry are also provided simultaneously from the same conductive material.

Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalLine material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.

Abstract: A semiconductor integrated circuit comprises a non-volatile semiconductor memory and a capacitor formed respectively on a first region and a second region of a substrate, wherein an insulation film of the non-volatile semiconductor memory has a thickness different from a capacitor insulation film of the capacitor.

Abstract: A memory cell has a cylindrical electrode having a porous cylindrical portion, and insulating layers for making less steep the height of cylindrical electrode are provided in the peripheral circuit region. Thus a semiconductor memory device and manufacturing method thereof can be provided in which the step between the memory cell array region and the peripheral circuit region can be made less steep by a smaller number of manufacturing steps.

Abstract: A semiconductor memory device and a fabricating method thereof are provided. In the course of forming a buried contact hole after forming a bit line pattern, the buried contact hole is formed by a self aligned contact process using capping layers included in the bit line pattern, thereby securing an overlap margin. Formation of a deep inner cylinder type capacitor unit prevents a bridge defect between lower electrodes of the capacitor and suppresses the occurrence of particles while simplifying the fabrication process. Furthermore, a mechanism for forming a second metal contact hole can simplifies the problems related to etching and filling of the second metal contact hole.

Abstract: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

Abstract: A non-volatile semiconductor memory device includes a plurality of trenches for element-isolation formed on the main surface of a semiconductor substrate, a nitrided silicon layer formed along the wall surface of the trench, a silicon oxide film for element-isolation formed in the trench, a thermal oxide film extending from the aforementioned main surface located at the periphery of the nitrided silicon layer onto the nitrided silicon layer, the thickness of a portion located on the nitrided silicon layer of which is not less than the thickness of a portion located at the periphery of nitrided silicon layer, a floating gate electrode formed on the thermal oxide film, an insulating film, and a control gate electrode.

Abstract: A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar.

Abstract: A non-volatile memory cell and a manufacturing process therefor are discussed. The cell is integrated in a semiconductor substrate and includes a floating gate transistor having a first source region, first drain region, and gate region projecting over the substrate between the first source and drain regions. The cell also includes a selection transistor having a second source region, second drain region, and respective gate region, projecting over the substrate between the second source and drain regions. The first and second regions are lightly doped and the cell comprises mask elements.

Abstract: A semiconductor device has a diffusion layer formed on a silicon substrate, an interlayer insulator which covers a surface of the silicon substrate and whose surface is planarized, and a dielectric capacitor composed of a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which is formed of a barrier metal layer composed of a contact plug, a low resistance layer and tantalum silicon nitride, and a dielectric film formed on the lower electrode, and an upper electrode. The lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the. upper dielectric film. Thus, a high-integration semiconductor device which allows the lower electrode to be micro-fabricated and enables lower-voltage operation and higher reliability can be obtained.

Abstract: A magnetic memory device of the present invention includes a first wiring conductor having a first ability to flow a current therethrough, a second wiring conductor having a second ability larger than the first ability to flow a current therethrough, a magnetic memory cell having a pinned magnetic layer coupled to the second wiring conductor, a free magnetic layer coupled to the first wiring conductor and anon-magnetic layer sandwiched between the first and second magnetic layers. The first wiring conductor is made by aluminum and the second wiring conductor is made by copper.