Abstract: Disclosed herein is a 4T (four transistor) SRAM cells. Stability, fabrication and integration density advantages as well as a high degree of soft error immunity with small and potentially tailorable write delay penalty may potentially be available in a memory cell by providing a source of pull down current through leakage of stabilizing capacitors, pass gate transistor leakage/off current, or a combination thereof. The source of pull down current allows omission of active pull down devices in a four transistor memory cell circuit to substantially reduce memory cell size or footprint while providing levels of soft error immunity comparable to or exceeding that of known 6T memory cell designs fabricated at comparable minimum feature size regimes and avoiding the expected increase of soft error rates as minimum feature size and/or number of circuit elements is reduced.

Abstract: There is provided a nonvolatile memory including memory cells each of which includes a storage element including a bistable molecular layer, wherein the bistable molecular layer contains a bistable molecule which brings about isomerization from a first isomer into a second isomer by injecting a hole and an electron into the bistable molecular layer, and brings about isomerization from the second isomer into the first isomer by irradiating the bistable molecular layer with erase light, and the memory is configured to irradiate the bistable molecular layers of all the memory cells with the erase light while applying an electric field to the bistable molecular layer of only a part of the memory cells that stores information to be held when erasing information stored in the rest of the memory cells.

Abstract: A method of forming an MIM capacitor with low leakage and high capacitance is disclosed. A layer of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) material is formed as a lower electrode over an optional capacitance layer of hemispherical grained polysilicon (HSG). Prior to the dielectric formation, the first layer may be optionally subjected to a nitridization or oxidation process. A dielectric layer of, for example, aluminum oxide (Al2O3) formed by atomic layer deposition (ALD) is fabricated over the first layer and after the optional nitridization or oxidation process. An upper electrode of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) is formed over the dielectric layer.

Abstract: Certain embodiments of the present invention relate to a semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate. The semiconductor device includes an interlayer dielectric layer, an embedded connection layer and a connection layer, wherein the interlayer dielectric layer is located between the semiconductor substrate and the capacitor element. The connection layer and the embedded connection layer are used to electrically connect a lower electrode of the capacitor element to another semiconductor element. The connection layer is located in a common layer of a bit line that is a component of the DRAM. The embedded connection layer is located in a connection hole formed in the interlayer dielectric layer.

Abstract: Memory cells, word lines and bit lines are formed on the substrate. Each word line is connected to some memory cells. The bit line is disposed in a wiring layer above the word lines, the bit line being connected to some memory cells and applied with a signal read from the memory cell selected by the word lines. Signal wiring lines are disposed in a wiring layer above the bit lines and partially superposed upon the bit lines. A shield layer is disposed in a wiring layer between the bit lines and signal wiring lines. As viewed along a direction vertical to the surface of the semiconductor substrate, the shield layer includes the bit lines in an area including an area where the bit lines and signal wiring lines are superposed upon each other, openings being formed through the shield layer in areas where the bit lines are not disposed.

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract: A method of patterning a metal surface by electro-mechanical polishing is disclosed. A metal surface is placed in fluid communication with an abrasive surface of a pad. The two surfaces are moved relative to each other, in acidic fluid which contains abrasive particles. An electrical circuit is formed between the metal surface and abrasive pad and a current is supplied to the circuit. The patterned surface then is processed into a useful feature such as a bottom electrode for a DRAM capacitor.

Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: On a silicon substrate 201, there are formed a silicon oxide 202, an adhesion layer 203 consisting of TiO2, a lower electrode 204 consisting of Pt, a ferroelectric thin film 205, and an upper electrode 206 consisting of Pt. A portion of the ferroelectric thin film adjacent to the upper electrode 206 is formed from a compound with a composition formula of SrBi2 (TaxNb1-x)2O9 where x=0.7. A compound with a value x in the composition formula being greater than 0.7 is used for the portion of the ferroelectric thin film adjacent to the upper electrode 206, so as to generate an appropriate number of grain boundaries on the surface of the ferroelectric film 205, the grain boundaries enabling implementation of anchoring effect between the ferroelectric film 205 and the upper electrode 206, thereby achieving prevention of exfoliation of the upper electrode 206 from the ferroelectric film 205.

Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAW using such elements is disclosed Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

Abstract: A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Abstract: Phase changeable memory devices include an integrated circuit substrate and first and second storage active regions on the integrated circuit substrate. The first and second storage active regions have a first width and a second width, respectively. A transistor active region on the integrated circuit substrate is between the first and second active regions, the first and seconds widths being less than a width of the transistor active region.

Abstract: A semiconductor device comprises a semiconductor substrate having first conductivity type, a trench capacitor, provided in the substrate, having a charge accumulation region, a gate electrode provided on the substrate via a gate insulating film, a gate side wall insulating film provided on a side surface of the gate electrode, drain and source regions, provided in the substrate, having a second conductivity type, an isolation insulating film provided adjacent to the trench capacitor in the substrate to cover an upper surface of the charge accumulation region, a buried strap region having the second conductivity type, the buried strap region being provided to electrically connect an upper portion of the charge accumulation region to the source region in the substrate, and a pocket implantation region having the first conductivity type, the pocket implantation region being provided below the drain and source regions and being spaced apart from the strap region.

Abstract: A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.

Abstract: A magnetic element which can switch states using a relatively lower magnetic field. The magnetic element comprises first and second magnetic layers separated by an intermediate layer. The magnetization of the first magnetic layer is fixed in a first direction parallel to the easy axis. The second magnetic layer comprises first and second magnetization vectors which are in opposite directions to create a magnetic boundary therein. The magnetic boundary can be driven out of the second magnetic layer by shifting the boundary along a first or second direction along the easy axis.

Abstract: A semiconductor integrated circuit apparatus having a planar capacitor can use a plurality of source voltages therein. According to the semiconductor integrated circuit apparatus, it is possible to not only control thresholds of individual MOS transistors but also reduce the threshold voltage of the planar capacitor without any additional fabrication process. The semiconductor integrated circuit apparatus includes a p-channel memory transistor and a capacitor in a first n-type element region, an n-channel low-voltage MOS transistor in a second p-type element region, and an n-channel high-voltage MOS transistor in a third p-type element region. A channel region of the second MOS transistor is doped under a high density profile by using a p-type impurity element. At the same time, the p-type impurity element is imported in a capacitor region of the first element region under the substantially same profile.

Abstract: A non-volatile memory (1) which comprises an insulating substrate (11) having a plurality of first electrodes (15) extending therethrough from a front surface of the substrate to a rear surface thereof, a second electrode (12) formed on one surface side of the substrate (11), and a recording layer (14) held between the first electrodes (15) and the second electrode (12) and variable in resistance value by electric pulses applied across the first electrodes (15) and the second electrode (12), the plurality of first electrodes (15) being electrically connected to the recording layer (14) in a region constituting a single memory cell (MC). The non-volatile memory (1) can be reduced in power consumption and has great freedom of design and high reliability.

Abstract: The invention achieves the fine processing of an information writing device, which includes a multilayered element obtained by stacking ferromagnetic/semiconductor/ferromagnetic layers, without increasing the resistivity and power consumption of the device and lowering the reliability thereof. The invention provides an information storage apparatus (1) having write word lines (11), bit lines (21) formed in such a way as to intersect with the write word lines (11) at predetermined intervals, and information storage devices (31) each comprising a multilayered film including a magnetic layer provided in an intersection region, in which each of the write word lines (11) intersects with an associated one of the bit lines (21), between the write word lines (11) and the bit lines (21).

Abstract: A nonvolatile semiconductor memory device that can be miniaturized is provided. A method of manufacturing the nonvolatile semiconductor memory device includes the steps of: forming an interlayer insulating film covering a stacked structure and a sidewall insulating film and having a top surface approximately parallel to a main surface; forming a resist pattern as a mask layer on the top surface of the interlayer insulating film; forming a groove as an opening in the interlayer insulating film to be positioned between the sidewall insulating films formed at the adjacent stacked structures; and forming a source region extending along a plurality of floating gate electrodes by implanting impurity ions from the groove to the main surface.

Abstract: A magnetic memory cell that uses a curved magnetic region to create magnetic anisotropy is provided by the present invention. The magnetic memory cell is created from a free magnetic layer, a barrier layer and a reference magnetic layer. The magnetic layers are constructed such that they have portions that are curved with respect to a first axis and straight with respect to a second perpendicular axis. These curved portions result in a magnetic memory cell that has an easy axis that is parallel to the first axis and a hard axis that is perpendicular to the easy axis. In addition, the resulting magnetic memory cell's coercivity is independent of it's thickness. Thus, the magnetic memory cell is well adapted to being scaled down without increasing the likelihood of thermally induced errors.

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A magnetoresistive effect element (1) has an arrangement in which a pair of ferromagnetic material layers (magnetization fixed layer (5) and magnetization free layer (7)) is opposed to each other through an intermediate layer (6) to obtain a magnetoresistive change by causing a current to flow in the direction perpendicular to the layer surface, the magnetization free layer (7) is made of a ferromagnetic material containing FeCoB or FeCoNiB and the magnetization free layer (7) has a film thickness ranging from 2 nm to 8 nm. A magnetic memory device comprises this magnetoresistive effect element (1) and bit lines and word lines sandwiching the magnetoresistive effect element (1) in the thickness direction. There are provided the magnetoresistive effect element having satisfactory magnetic characteristics and the magnetic memory device including this magnetoresistive effect element and which can obtain excellent write/read characteristics.

Abstract: A nonvolatile memory device including one transistor and one resistant material and a method of manufacturing the nonvolatile memory device are provided. The nonvolatile memory device includes a substrate, a transistor formed on the substrate, and a data storage unit connected to a drain of the transistor. The data storage unit includes a data storage material layer having different resistance characteristics in different voltage ranges.

Abstract: A ferroelectric memory device along with a method of forming the same are provided. A first interlayer insulating layer is formed on a semiconductor substrate. A buried contact structure is formed on the first interlayer insulating layer. The buried contact structure is electrically connected to the substrate through a first contact hole extending through the first interlayer insulating layer. A blocking layer covers or encapsulates the buried contact structure and the first interlayer insulating layer. A second interlayer insulating layer is formed on the blocking layer. A ferroelectric capacitor formed on the second interlayer insulating layer and is electrically connected to the buried contact structure through a second contact hole that penetrates the second interlayer insulating layer and the blocking layer.

Abstract: A metallized film capacitor made by winding or laminating a both-side metallized polypropylene (PP) film and a non-metallized PP film. Limiting the heat shrinkage factor and the thickness of the PP films, the position of deposited electrodes, and the rate of the peeled area of the deposited electrodes to a curtain range provides a metallized film capacitor having improved dielectric strength, tan &dgr;, and charge-discharge characteristics.

Abstract: The present invention is characterized by including an electrode formed on surface of a semiconductor substrate, wherein said electrode includes a barrier layer consisting of amorphous or microcrystal expressed by the following expression: M1xM21-x (0<X<1; M1: Au, Pt, Ir, Pd, Os, Re, Rh, Ru, Cu, Co, Fe, Ni, V, Cr; M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb).

Abstract: An active pixel array has the signal output of each pixel connected to a first column conductor, and a reset switch connected to a second column conductor. The first and second column conductors are connected to a read-reset amplifier. The read-reset amplifier operates in a first mode in which a reset voltage is applied to the second column line, and in a second mode in which pixel output signals are buffered from the first column line. The read-reset amplifier can also operate as a comparator forming part of an ADC circuit.

Abstract: A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114), wherein either the cap layer (140) or hard mask layer (142) comprise WN. A seed layer (136) disposed beneath the magnetic stacks (114) may also be comprised of WN, The use of the material WN improves etch process selectivity during the manufacturing process.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: A magnetic memory element has reduced Néel coupling between a pinned layer and a free layer. The magnetic memory element includes a first pinned ferromagnet and a free ferromagnet which are separated by a barrier layer. The magnetic field direction of the pinned layer is fixed, for example, by an antiferromagnetic exchange layer. An additional ferromagnetic layer, provided in coupling relationship with the first pinned ferromagnet, offsets Néel coupling between the free ferromagnetic layer and the first pinned ferromagnet.

Abstract: This invention proposes to make memory using organic materials. The basic structure of the memory cell is a field effect organic transistor using a ferroelectric thin film polymer as gate dielectric. By controlling the gate voltage to polarize the thin film ferroelectric polymer polarized in either an “up” or “down” state, the source-drain current can be controlled between two different values under the same source-drain voltage. The source-drain current thus can be used to represent either a “0” or “1” state. The organic thin film transistor can be made from poly(phenylenes), thiophene oligomers, pentacene, polythiophene, perfluoro copper phthalocyanine or other organic thin films. The ferroelectric thin film can be poly(vinylidene fluoride) (PVDF), poly(vinyldiene-trifluoroethylene) (P(VDF-TrFE)) copolymers, odd-numbered nylons, cyanopolymers, polyureas, or other ferroelectric thin films.

Abstract: A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.

Abstract: A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.

Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.

Abstract: A memory cell array of the non-volatile semiconductor memory device includes a plurality of gate electrodes provided in the row direction, bit lines D1, D2, D3, D4 and source lines S1, S2, S3, S4 provided in the column direction, and memory cells each having a floating gate. The source lines are separately provided in at least two wiring layers. The source line S2 provided in the first layer overlaps the source line S1 provided in the second layer when viewed two-dimensionally. This array structure reduces the dimension of the memory cell array in the row direction, thereby enabling significant reduction in area.

Abstract: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

Abstract: A semiconductor device capable of preventing a ring defect and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate having a junction region, a planarization layer having a first contact hole portion through which the junction region is exposed, an interlayer dielectric layer formed on the planarization layer and having a second contact hole portion extended from the first contact hole portion, and contact spacers formed at the sidewalls of the first and second contact hole portions. Here, the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate.

Abstract: The capacitor comprises an lower electrode 22, a dielectric film 30 formed on the lower electrode 22, a floating electrode 20 formed on the dielectric film 30, a dielectric film 50 formed on the floating electrode 40 and having a film orientation different from that of the dielectric film 30, and an upper electrode 80 formed on the dielectric film 50, whereby various characteristics depending on film orientations of the dielectric films can be simultaneously improved.

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF-overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control-electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: A magnetic memory device capable of achieving high reliability and superior operation characteristics of tunneling magneto-resistive (TMR) elements is provided. This magnetic memory device includes a semiconductor substrate, a transistor which is formed above the semiconductor substrate, and a TMR element which is formed on or above an interlayer dielectric film that covers the transistor of the substrate. The device also includes a first wiring line which is buried in the interlayer dielectric film and connected to a source/drain diffusion layer of the transistor, a second wiring line which is buried under the TMR element while overlying the first wiring line within the interlayer dielectric film and which is used to apply a current-created magnetic field to the TMR element during writing, and a third wiring line connected to an upper surface of the TMR element and provided to cross the second wiring line.

Abstract: A DRAM device having improved charge storage capabilities and methods for providing the same. The device includes an array portion having a plurality of memory cells extending from a semiconductor substrate. Each cell includes a storage element for storing a quantity of charge indicative of the state of the memory cell and a valve element that inhibits the quantity of charge from changing during quiescent periods. The storage elements are disposed adjacent a plurality of storage regions of the substrate and the valve elements are disposed adjacent a plurality of valve regions of the substrate. A plurality of dopant atoms are selectively implanted into the array portion so as to increase a threshold voltage which is required to develop a conducting channel through the valve region. The dopant atoms are disposed mainly throughout the valve regions of the substrate and are substantially absent from the storage regions.

Abstract: In accordance with the present invention, a memory cell includes a non-volatile device and a DRAM cell. The DRAM cell further includes an MOS transistor and a capacitor. The non-volatile device include a control gate region and a guiding gate region that may partially overlap. The non-volatile device is erased prior to being programmed. Programming of the non-volatile device may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM is loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile device is restored in the DRAM cell.

Abstract: A semiconductor integrated circuit comprises a non-volatile semiconductor memory and a capacitor formed respectively on a first region and a second region of a substrate, wherein an insulation film of the non-volatile semiconductor memory has a thickness different from a capacitor insulation film of the capacitor.

Abstract: A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated using sidewall spacers within the trench. A doped region is buried at the bottom of the trench. The structure can be fabricated such that the buried doped region provides a connecting layer in a multi-bit flash memory cell. Alternatively, the buried doped region may be used as a buried bitline in a single bit flash memory cell.

Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.

Abstract: A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via different contacts, respectively. The protective metal line has a resistance higher than that of the word-line.

Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: Structures and methods involving at least a pair of gate oxides having different thicknesses, one suitable for use in a logic device and one suitable for use in a memory device, have been shown. The method provided by the present invention affords a technique for ultra thin dual gate oxides having different thicknesses using a low temperature process in which no etching steps are required. The method includes forming a pair of gate oxides to a first thickness, which in one embodiment, includes a thickness of less than 5 nanometers. In one embodiment, forming the pair of gate oxides includes using a low-temperature oxidation method. A thin dielectric layer is then formed on one of the pair of gate oxides which is to remain as a thin gate oxide region for a transistor for use in a logic device. The thin dielectric layer exhibits a high resistance to oxidation at high temperatures.