Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies, and capacitor structures.

Abstract: A structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Abstract: A high capacity silicon capacitor formed on an integrated circuit substrate includes a metal portion on the substrate; a silicon nitride (SiN) portion sputtered on the metal; a silicon (Si) portion sputtered on the silicon nitride portion, another SiN layer and finally a metal layer. The SiN layers are for increased isolation and are optional.

Abstract: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

Abstract: Magnetic random access memory cells having split sub-digit lines include a pair of sub-digit lines disposed over a semiconductor substrate. The pair of sub-digit lines are spaced apart from each other when viewed from a top plan view. A magnetic resistor is disposed over the pair of sub-digit lines. The magnetic resistor is disposed to overlap with the pair of sub-digit lines. The magnetic resistor is electrically connected to a predetermined region of the semiconductor substrate through a magnetic resistor contact hole that penetrates a gap region between the pair of sub-digit lines.

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A device (2) with a switchable capacitance comprises a first and a second electrode (12, 20) facing each other, a dielectric layer (14) between a first and a second capacitor electrode (12, 20), and a switching member (18) between the second electrode (20) and the dielectric layer (14), the switching member (18) comprising a switching material reversibly switchable between a lower conductivity state and a higher conductivity state, each of the lower conductivity state and the higher conductivity state being persistent, wherein the capacitance of the device (2) depends on the conductivity state of the switching material.

Abstract: An electro-optical device having six image signal lines that are third layer leads comprising the same layer as data lines. A lead which is branched from one image signal line and crosses the other image signal lines is a parallel connection of a first layer lead and a second layer lead. The first layer lead comprises the same layer as the scanning lines in a display region and the second layer lead comprises the same layer as a barrier film of a thin film transistor (TFT) in the display region. Although the first and second layer leads have high resistance alone, the parallel connection can reduce resistance. In other portions, the second layer lead is used alone to improve the design versatility. Thus, the design versatility of peripheral circuits such as a sampling circuit in an electro-optical device is improved and the lead resistance in the peripheral circuit is reduced.

Abstract: A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.

Abstract: A memory cell having improved interconnect. Specifically, a dynamic random access memory (DRAM) based content addressable (CAM) memory cell is provided. The lower cell plate of the storage capacitor is implemented to provide an interconnect for the access transistor and the CAM portion of the memory cell. Conductive plugs are coupled to each of the transistors and coupled directly to the lower cell plate of the capacitor.

Abstract: A plurality of first wiring structures of a first width are arranged periodically at first intervals. A second wiring structure is formed next to one of the first wiring structures. The lower part of the second wiring structure has a second width substantially equal to the sum of n times the first width of the first wiring structure (n is a positive integer equal to two or more) and (n?1) times the first interval.

Abstract: A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32.

Abstract: A capacitor includes an array of first conductive units and an array of second conductive units. Each of the first conductive units includes a hollow first conductive post that has lateral sides. The first conductive posts of the first conductive units are interconnected to form a grid that defines a plurality of lattices. Each of the second conductive units includes a second conductive post that is disposed in a respective one of the lattices and that has lateral sides that are surrounded by the lateral sides of the first conductive post of a respective one of the first conductive units. The first conductive post of each of the first conductive units and the second conductive post of the respective one of the second conductive units cooperatively define a charge space. A dielectric material fills the charge space.

Abstract: Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.

Abstract: A first insulating hydrogen barrier film is filled between lower electrodes of some ferroelectric capacitors arranged along one direction out of a word line direction and a bit line direction among a plurality of ferroelectric capacitors included in a ferroelectric memory of this invention. A common capacitor dielectric film commonly used by the some ferroelectric capacitors arranged along the one direction is formed on the lower electrodes of the some ferroelectric capacitors arranged along the one direction and on the first insulating hydrogen barrier film. A common upper electrode commonly used by the some ferroelectric capacitors arranged along the one direction is formed on the common capacitor dielectric film. A second insulating hydrogen barrier film is formed so as to cover the common upper electrode.

Abstract: Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

Abstract: The invention relates to a magnetoresistive semiconductor element, including a first contact and a second contact, and also a layer of a nonmagnetic semiconductor arranged between the first contact and the second contact. The first contact is composed of a semi-magnetic material. The semi-magnetic material is a strongly paramagnetic material whose electron spins have no preferential direction without an action of an external magnetic field. Under the action of an external magnetic field, the electrons are spin-polarized in the first contact. When a voltage is applied this results in the injection of spin-polarized electrons into the nonmagnetic semiconductor. As a result, in the nonmagnetic semiconductor, only one of the spin channels can be used for transporting the charge carriers, so that a positive magnetoresistive effect is obtained.

Abstract: A nonvolatile semiconductor memory apparatus capable of attaining a low voltage when writing data, wherein charge injection into an unnecessary portion is not performed when reading, and capable of unifying a threshold voltage level when erasing, comprising a first conductive type semiconductor region, two source/drain regions made by a second conductive type semiconductor, a plurality of dielectric films stacked on a first conductive type semiconductor region between the two source/drain regions, and a gate electrode; wherein the first conductive type semiconductor region between the two source/drain regions includes a first region wherein a channel is formed by an inversion layer of a minority carrier and a second region formed between the first region and a source/drain region on one side of the first region and having higher concentration than that of the first region.

Abstract: The MRAM has a transistor for selection, a lower insulating interlayer, a first connecting hole, a first wiring formed on the lower insulating interlayer, a tunnel magnetoresistance device formed on the first wiring through an insulating film, an upper insulating interlayer, and a second wiring, in which a lower surface of the tunnel magnetoresistance device is electrically connected to the first connecting hole through a second connecting hole, and the tunnel magnetoresistance device, the insulating film and the first wiring have nearly the same widths along the second direction.

Abstract: A high capacity, fast access dynamic random access memory is provided. Furthermore, a pipelined write method can be realized at each array block by affixing a latch between the sense amplifier and write data line for each column. In this manner, a data write phase can occur simultaneously with the pre-read phase of the following address. Using this method, the effective access speed to the array block can be increased, yielding a fast access cache memory.

Abstract: A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 ? thickness or less, as commonly available from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

Abstract: Various embodiments of a magnetic memory element, including a storage layer and a reference layer, are disclosed. The storage layer includes two conjugate magnetic domain segments having opposing helicities. The reference layer is permanently magnetized. A non-magnetic layer is interposed between the two magnetic layers. The boundaries of the two conjugate magnetic domain segments of the storage layer define domain walls along the radial direction thereof. The magnetic moment direction of one domain wall points inward and the magnetic moment direction of the other domain wall points outward. The two domain walls always attract each other, leaving one segment significantly larger than the other. These two different conditions (each longer the other) define two binary data states. By sending a vertical current through the magnetic memory element, transitions between the memory states can be achieved. Also disclosed are a memory cell, a memory device, and a computing device.

Abstract: A ferroelectric memory device includes a lower interlayer dielectric on a semiconductor substrate, a plurality of ferroelectric capacitors, and a plate line. The ferroelectric capacitors are on the lower interlayer dielectric. The plate line extends across and electrically connects to surfaces of at least two adjacent ones of the plurality of ferroelectric capacitors.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: A magnetic random access memory (MRAM) device including a magnetic tunneling junction (MTJ) stack separated from one or more proximate conductive layers and/or one or more proximate MTJ stacks by a low-k dielectric material.

Abstract: The present invention provides a resistance random access memory structure, including a plurality of word lines in a substrate, a plurality of reset lines coupled to the word lines, a dielectric layer on the substrate, a plurality of memory units in the dielectric layer. Each of the memory units includes a bottom electrode, a top electrode and a resistive thin film between the top electrode and the bottom electrode. The top electrodes of the memory units in a same column e coupled to one of the reset lines and a plurality of the bit lines on the memory units. The bottom electrodes of the memory units in a same row are coupled to one of the bit lines. Because the present invention provides reset lines for Type 1R1D RRAM, it can overcome the non-erasable of the conventional Type 1R1D RRAM.

Abstract: A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body. The ferroelectric body can be formed by chemical-mechanical polishing of a ferroelectric film. In a memory device, the capacitor is coupled to a transistor. The dielectric lining protects the ferroelectric body from etching damage during the fabrication process, obviating the need for repeated annealing to repair such damage, thereby avoiding the alteration of transistor characteristics that would be caused by such annealing.

Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line.

Abstract: A nonvolatile ferroelectric memory device and a method for fabricating the same are provided that increase a process margin and simplify process steps. In addition, a number of masks is reduced to save the cost and at the same time minimize or reduce a layout area. The nonvolatile ferroelectric memory device can include first and second split wordlines formed along a first direction on a substrate at prescribed intervals, a first electrode of a first ferroelectric capacitor on the second split wordline and a first electrode of a second ferroelectric capacitor on the first split wordline, first and second ferroelectric layers respectively on surfaces of the first electrodes of the first and second ferroelectric capacitors, and second electrodes of the first and second ferroelectric capacitors, respectively, on surfaces of the first and second ferroelectric layers.

Abstract: Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also provided, including measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.

Abstract: A nonvolatile semiconductor memory device improved with integration degree, in which the gate of the selection transistors is separated on each of active regions, first and second selection transistors are arranged in two stages in the direction of the global bit line, the gates for the selection transistors in each stage are disposed on every other active regions, contact holes are formed in mirror asymmetry with respect to line B—B in the connection portion for the active regions, the gate is connected through the contact hole to the wiring, the adjacent active regions are connected entirely in one selection transistor portion and connected in an H-shape for adjacent two active regions in another selection transistor portion, and the contact hole is formed in the connection portion and connected when the global bit line, whereby the pitch for the selection transistor portion can be decreased in the direction of the global bit line.

Abstract: The present invention provides a ferroelectric memory device and a manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. The ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, includes a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; and a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode.

Abstract: A magnetic memory device capable of achieving high reliability and superior operation characteristics of tunneling magneto-resistive (TMR) elements is provided. This magnetic memory device includes a semiconductor substrate, a transistor which is formed above the semiconductor substrate, and a TMR element which is formed on or above an interlayer dielectric film that covers the transistor of the substrate. The device also includes a first wiring line which is buried in the interlayer dielectric film and connected to a source/drain diffusion layer of the transistor, a second wiring line which is buried under the TMR element while overlying the first wiring line within the interlayer dielectric film and which is used to apply a current-created magnetic field to the TMR element during writing, and a third wiring line connected to an upper surface of the TMR element and provided to cross the second wiring line.

Abstract: A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.

Abstract: A semiconductor element in which the hydrogen-induced degradation of ferroelectric characteristics can be controlled includes a hydrogen penetration prevention film 400 for preventing hydrogen from penetrating into a ferroelectric film is formed above top electrodes 28. The width of the hydrogen penetration prevention film 400 in the direction orthogonal to a specific direction in which the top electrodes 28 are arranged in a parallel manner is set to be equal to or greater than the maximum width of the top electrodes 28 in the orthogonal direction. The hydrogen penetration prevention film 400 is used as a main WL that connects sub-WL drivers 60a and a main WL driver 60b extended in the same direction as the specific direction in the which the top electrodes 28 are aligned parallel to each other in a peripheral circuit 60.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: An exemplary thermally-assisted magnetic memory structure comprises a first conductor substantially surrounded by a cladding, a memory cell being thermally isolated from the first conductor by a thermally resistive region, and a second conductor electrically contacting the memory cell.

Abstract: A semiconductor component having a material-reinforced contact area formed of a metal layer is disclosed. The contact area is jointly formed by a second metal area of a first metal layer and a fourth metal area of a second metal layer which is to be contacted. A thickness of the contact area material is at least twice that of a single metal layer and thereby prevents penetrative etching when a hole is created for contacting the metal layer.

Abstract: In one aspect, a semiconductor device includes an array of memory cells. Individual memory cell of the array include a capacitor having first and second electrode, a dielectric layer disposed between the first and second electrodes. Select individual capacitors are energized so as to blow the dielectric layer to establish a connection between the first and second electrodes such that, after blowing the dielectric layer, the second electrode is coupled to a cell plate generator establish a bias connection therebetween. Cell plate bias connection methods are also described.

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract: A semiconductor device embodiment may include a plurality of cells each including a transistor therein, the cells also each including a first capacitor electrode therein, the first capacitor electrodes being positioned on an insulating layer, the first capacitor electrodes in adjacent cells being separated from each other. The device may also include partitioning members on the insulation layer, wherein the partitioning members are positioned to separate the cells from one another, and the partitioning members include an upper surface thereon. The device also may include an organic layer on the first capacitor electrodes between the partitioning members, wherein the organic layer is not positioned in contact with the upper surface of the partitioning members. The device may also include a continuous second capacitor electrode on the organic layer, the second capacitor electrode layer formed to be a common electrode for cells.

Abstract: A magnetoresistive memory apparatus with a semiconductor substrate having a plurality of intersecting, non-contacting word lines and bit lines constituting a matrix, and a plurality of ferromagnetic tunnel junction devices located adjacent each intersection of the plurality of lines, each junction device having, disposed one upon another via insulating layers, free layers having variable magnetization directions and fixed magnetization layers having fixed magnetization directions, with magnetized information being written to the memory device at an intersection selected by magnetization electric currents supplied to the lines, the magnetized information read out by detecting the resistance variance of electric currents flowing through the memory device due to the tunnel effect.

Abstract: Ultra-high-density data-storage media employing indium chalcogenide, gallium chalcogenide, and indium-gallium chalcogenide films to form bit-storage regions that act as photoconductive, photovoltaic, or photoluminescent semiconductor devices that produce electrical signals when exposed to electromagnetic radiation, or to form bit-storage regions that act as cathodoconductive, cathodovoltaic, or cathodoluminescent semiconductor devices that produce electrical signals when exposed to electron beams. Two values of a bit are represented by two solid phases of the data-storage medium, a crystalline phase and an amorphous phase, with transition between the two phases effected by heating the bit storage region.

Abstract: Ferroelectric memory includes a hollow formed in a first insulation film. A lower electrode is formed in this hollow by sol-gel method including an application process due to a spin coat method. In this application process, a precursor solution is dripped on a surface of the first insulation film and splashed away due to centrifugal force. Due to this, a first conductive film to being formed has an increased film thickness at portion of the hollow where the precursor solution is ready to correct, or portion to be formed into a lower electrode, and a decreased film thickness at portion other than the hollow. Accordingly, it is satisfactory to etch only the hollow portion when forming a lower electrode by dry-etching the first conductive film.

Abstract: A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first and second doped regions. The second MOS has a second gate structure, a second spacer and third and fourth doped regions. Anisotropic etching is performed to remove part of the organic layer until the oxide layer on the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate. The oxide layer on the first and the second gate structures is removed. The remaining organic layer is removed. The oxide layer on the first, second, and third doped regions is removed. Thus, a silicide layer cannot form on the fourth doped region.

Abstract: Described in this disclosure is a non-volatile memory cell. The non-volatile memory cell generally includes a short-range atomic order substrate, a dielectric positioned adjacent to the substrate, and a non-floating gate positioned adjacent to the dielectric.

Abstract: A first impurity diffusion area is formed in the semiconductor substrate at a bottom of the first trench formed in a surface of the semiconductor substrate. A second impurity diffusion area is formed in the surface of the semiconductor substrate, each have one end contacting a first side wall of the first trench, and each have the same conductive type as the first impurity diffusion area. A first gate electrode is provided on the first side wall between the first and second impurity diffusion areas with a gate insulating film interposed therebetween. A first ferroelectric film is provided on a first lower electrode, which is provided on the second impurity area. A first upper electrode is provided on the first ferroelectric film. A first interconnection layer is provided above the first upper electrode. A first contact plug electrically connects the first interconnection layer and first impurity diffusion area.

Abstract: A semiconductor power module capable of efficiently utilizing the performance of the module and facilitating management of the module in custody. The semiconductor power module having one or more semiconductor power switching elements and a drive unit is provided with a non-volatile memory for storing use history of the module and a drive unit. The use history contains information of one of the number of switching times of the semiconductor power switching element, the number of over-current detections of the semiconductor power switching element and a temperature rise of the semiconductor power module.

Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.

Abstract: The present invention discloses a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure. The capacitor lower electrode has a cylindrical shape and a certain height. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The capacitor upper electrode has a spacer shape and is formed around the sidewall of the ferroelectric layer that surrounds the lower electrode. In the method of forming the ferroelectric memory device, a semiconductor substrate having an interlayer dielectric layer and a lower electrode contact formed through the interlayer dielectric layer is prepared. A cylindrical capacitor lower electrode is formed on the interlayer dielectric layer to cover the contact.