Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.

Abstract: A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption.

Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.

Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.

Abstract: The present disclosure provides a semiconductor structure, comprising a substrate, dielectric layers and conductive layers. A first dielectric layer is disposed on a bottom surface and sidewall surfaces of a filled trench of the substrate. A first conductive layer is disposed on the first dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A second dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the second dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A third dielectric layer is disposed on the second conductive layer. A third conductive layer is disposed in the filled trench and on the third dielectric layer. A top surface of the third conductive layer is lower than the second surface of the second conductive layer.

Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Abstract: Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.

Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

Abstract: One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example.

Abstract: A memory cell with a composite top electrode is provided. A bottom electrode is disposed over a substrate. A switching dielectric having a variable resistance is disposed over the bottom electrode. A capping layer is disposed over the switching dielectric. A composite top electrode is disposed over and abutting the capping layer. The composite top electrode comprises a tantalum nitride (TaN) layer and a titanium nitride (TiN) film disposed directly on the tantalum nitride layer. By having the disclosed composite top electrode, an interfacial oxidized layer is eliminated or less formed when exposing the composite top electrode for top electrode via formation, thereby improving RC properties between the top electrode and the top electrode via. A method for manufacturing the memory cell is also provided.

Abstract: A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract: A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

Abstract: Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A contact trench is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate to a buried oxide layer of the SOI substrate. An isolation trench is formed that extends through the device layer to the buried oxide layer. An electrical insulator is deposited that fills the contact trench and the first isolation trench. The electrical insulator is removed from the contact trench. After the electrical insulator is removed from the contact trench, an electrical conductor is formed in the contact trench. The electrical contact may be coupled with a doped region in a handle wafer of the SOI substrate.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes forming an opening in the dielectric layer. A dielectric constant of a first portion of the dielectric layer is less than that of a second portion of the dielectric layer surrounding the opening. The method further includes forming a conductive feature in the opening. The second portion is between the first portion and the conductive feature. In addition, the method includes modifying an upper portion of the first portion to increase the dielectric constant of the upper portion of the first portion. The method also includes removing the upper portion of the first portion and the second portion.

Abstract: There is provided a method of forming a nitride film, including: repeating a cycle including an adsorption process of adsorbing a film forming precursor gas onto a substrate having a surface in which a fine recess is formed, the film forming precursor gas containing an element and chlorine constituting a nitride film to be formed; and a nitriding process of nitriding the adsorbed film forming precursor gas with nitriding active species, to form the nitride film in the fine recess. The nitriding process includes: generating NH* active species and N* active species as a nitriding active species; and controlling concentrations of the NH* active species and the N* active species to vary an area where the film forming precursor gas is adsorbed in the fine recess.

Abstract: A capacitor that includes a conductive porous base material; a dielectric layer; and an electrode. The conductive porous base material, the dielectric layer, and the upper electrode are laminated together to constitute an effective part that accumulates charges in the dielectric layer when a voltage is applied between the conductive porous base material and the electrode. The conductive porous base material includes at least one groove having a width of 10 ?m or more at ½ of a depth of the at least one groove.

Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes determining a guard ring width within an integrated circuit design layout, where a guard ring with the guard ring width surrounds an active area in the integrated circuit design layout. A deep trench location is calculated for replacing the guard ring, where the deep trench location depends on the guard ring width. The guard ring in the integrated circuit design layout is replaced with a deep trench having the deep trench location. The deep trench is formed within a substrate at the deep trench location, where the deep trench surrounds the active area.

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

Abstract: A method of centering a contact on a layer of a magnetic memory device. In one embodiment, a spacers is formed in an opening surrounding the upper layer and the contact is formed within the spacer. The spacer is formed from an anisotropically etched conformal layer deposited on an upper surface and into the opening.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a deep trench capacitor, integrated structures and methods of manufacture. The structure includes: a conductive material formed on an underside of an insulator layer and which acts as a back plate of a deep trench capacitor; an inner conductive layer extending through the insulator layer and an overlying substrate; and a dielectric liner between the inner conductive material and the conductive material, and formed on a sidewall of an opening within the insulator layer and the overlying substrate.

Abstract: A sensor device includes a high voltage component, a sensor component and a charge storage component. The sensor component utilizes a low voltage supply. The high voltage component is configured to generate the low voltage supply from a high voltage supply. The charge storage component is configured to provide charge for the low voltage supply during a power break. The charge storage component has a vertical capacitor.

Abstract: A semiconductor structure includes a replacement strap for a finFET fin that provides communication between a storage capacitor and the fin. The storage capacitor is located in a deep trench formed in a substrate and the fin is formed on a surface of the substrate. The replacement strap allows for electrical connection of the fin to the storage capacitor and is in direct physical communication with the fin and the storage capacitor. The replacement strap may be formed by removing a sacrificial strap and merging epitaxially grown material from the fin and epitaxially grown material from the capacitor. The epitaxially grown material grown from the fin grows at a slower rate relative to the epitaxially grown material grown from the capacitor. By removing the sacrificial strap prior to forming the replacement strap, epitaxial overgrowth that may cause shorts between adjacent capacitors is limited.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The structure includes: a transistor formed over a semiconductor material and an underlying substrate; and multiple isolated contact regions under a body or channel of the transistor, structured to provide a local potential to the body of the transistor at different locations.

Abstract: Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together.

Abstract: A semiconductor device includes a substrate having a field region disposed therein that defines an active region of the substrate, the active region comprising a pillar-shaped bit line contact region having an upper surface disposed at a higher level than an upper surface of the field region. An interlayer insulating layer is disposed on the substrate and covers the field region. A bit line is disposed in a trench in the interlayer insulating layer above the pillar-shaped bit line contact region and electrically connected thereto.

Abstract: Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed.

Abstract: A capacitor structure includes a deep trench, a contact plug, a spacer and a metal-insulator-metal film. The deep trench extends into a crown oxide substrate, and the contact plug is disposed entirely below the crown oxide substrate. The spacer lines the deep trench, and the metal-insulator-metal film is disposed in the deep trench.

Abstract: A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.

Abstract: A memory structure includes a 3D array of memory cells, a plurality of first conductive lines disposed on the 3D array, a plurality of second conductive lines disposed on the first conductive lines, a top metal plate disposed on the second conductive lines, and at least one strapping structure. The second conductive lines and the first conductive lines extend on different directions. The at least one strapping structure is configured for the first conductive lines and correspondingly disposed on at least one dummy region of the 3D array. Each strapping structure includes a connecting structure and a jumping line. The jumping line is disposed on and coupled to the connecting structure, and coupled to the top metal plate. The jumping line and the second conductive lines extend on the same direction.

Abstract: A method includes forming a trench in a Silicon substrate; depositing metal on sidewalls and a bottom of the trench; annealing to react the metal with underlying Si and form metal silicide adjacent to sidewalls and bottom of the trench; removing unreacted metal and depositing a dielectric layer on the metal silicide, a metal layer over the dielectric layer and polysilicon to fill a remainder of the trench thereby forming top plate electrode of a MIM capacitor. The method further forms a transistor adjacent to a top of the trench, where the transistor is connected to the top plate electrode of the MIM capacitor via a strap interface that comprises a portion of the metal silicide layer at the top of the trench. The portion of the metal silicide layer can be disposed in an SOI layer, and silicide in the Si substrate forms a bottom plate of the capacitor.

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor.

Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

Abstract: An electronic device includes a wiring board having one or more layers, an integrated circuit arranged on the wiring board, an antenna, and a signal path. The integrated circuit generates a high frequency signal and feeds it to the signal path. The signal path conveys the high frequency signal to the antenna. The antenna emits the high frequency signal into an environment of the electronic device. Alternatively or in addition, the antenna receives the high frequency signal from the environment and feeds it to the signal path. The signal path conveys the high frequency signal to the integrated circuit. The integrated circuit processes the high frequency signal. The signal path includes a wave guide that traverses one or more of the layers of the wiring board.

Abstract: In accordance with the present disclosure, one embodiment of a fractal variable capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure, wherein the capacitor body has an upper first metal plate with a fractal shape separated by a vertical distance from a lower first metal plate with a complementary fractal shape; and a substrate above which the capacitor body is suspended.

Abstract: Capacitor strap connections for a memory cell and device structures for making such capacitor strap connections. A deep trench capacitor is formed in a substrate. A collar comprised of an electrical insulator is formed at least partially inside an upper section of a deep trench in which the deep trench capacitor is formed. A portion of the collar is removed to define a notch extending through the collar, and a connection strap is formed in the notch. A fin is formed from a portion of the substrate, and is coupled by the connection strap with an electrode of the deep trench capacitor that is located inside the deep trench.

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor.

Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

Abstract: A method of filling a depression of a workpiece is provided. The method includes forming a first thin film made of a semiconductor material substantially not containing an impurity along a wall surface which defines the depression, forming an epitaxial region conforming to crystals of the semiconductor substrate from the semiconductor material of the first thin film moved toward a bottom of the depression by annealing, etching the first thin film remaining on the wall surface, performing gas phase doping upon the epitaxial region, forming a second thin film made of a semiconductor material substantially not containing an impurity along the wall surface, further forming an epitaxial region from the semiconductor material of the second thin film moved toward the bottom of the depression by annealing, and performing gas phase doping upon the second thin film remaining on the wall surface and the epitaxial region.