Stacked Capacitor Patents (Class 257/303)
  • Patent number: 11158591
    Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern including a single via. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first via surrounding a second via. The first and second vias are concentric with one another about a central point of the second via layer.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chan Chen, Yueh-Chuan Lee
  • Patent number: 11127790
    Abstract: Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 10991662
    Abstract: A semiconductor device includes a transistor implemented over an oxide layer, one or more electrical connections to the transistor, one or more dielectric layers formed over at least a portion of the electrical connections, an electrical element disposed over the one or more dielectric layers, the electrical element being in electrical communication with the transistor via the one or more electrical connections, a patterned form of sacrificial material covering at least a portion of the electrical element, and an interface layer covering at least a portion of the one or more dielectric layers and the sacrificial material.
    Type: Grant
    Filed: February 1, 2020
    Date of Patent: April 27, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: David T. Petzold, David Scott Whitefield
  • Patent number: 10956646
    Abstract: In some embodiments, a method includes selecting, a first circuit layout, where the first circuit layout includes a circuit element representation, a design rule, and a target circuit element value. The method further includes receiving a plurality of circuit element values of circuit elements fabricated in each of multiple fabrication facilities using the design rule. The method also includes selecting a fabrication facility and a circuit element value of circuit elements fabricated in the selected fabrication facility using the design rule. Further the method includes determining a circuit element value calculation based on the selected circuit element values, and determining an adjustment value. This adjustment value is further used to customize the design rule. The method then includes generating a second circuit layout comprising the customized design rule, causing the fabrication facility to fabricate a circuit using the second circuit layout.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: March 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tae S. Kim, Gregory B. Shinn
  • Patent number: 10957576
    Abstract: A dynamic random access memory (DRAM) and a method of fabricating the same are provided. The DRAM includes a substrate, a plurality of first isolation structures, a plurality of word line structures, a plurality of second isolation structures, and a plurality of third isolation structures. The plurality of first isolation structures are located in the substrate to define a plurality of active areas arranged along a first direction, wherein the plurality of active areas and the plurality of first isolation structures are alternately arranged along the first direction. The plurality of word line structures pass through the plurality of active areas and the plurality of first isolation structures. The plurality of word line structures are arranged along a second direction and extended along a third direction.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Feng-Jung Chang
  • Patent number: 10957374
    Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 10916621
    Abstract: A capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer disposed between the first and second electrodes and being in contact with each of the first and second electrodes. The dielectric layer contains at least one element selected from the group consisting of nitrogen and silicon.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 9, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Koyanagi, Yuuko Tomekawa
  • Patent number: 10825823
    Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a substrate, a main device, a one-time-programmable (OTP) device and a decoupling capacitor array. The substrate includes a first region and a second region. The main device is in the first region, the OTP device and the decoupling capacitor array are in the second region, and the decoupling capacitor array overlies the OTP device.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shian-Jyh Lin
  • Patent number: 10818592
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of one-time-programmable (OTP) cells, a bottom cell plate, a top cell plate and a decoupling capacitor array. The substrate includes a plurality of active areas and at least one isolation structure provided between the active areas to isolate the active areas from one another. The plurality of OTP cells are disposed in the active areas, the bottom cell plate is disposed on the OTP cells, and the top cell plate is disposed over the bottom cell plate. The decoupling capacitor array is disposed between the bottom cell plate and the top cell plate, and overlies the OTP cells.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 27, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shian-Jyh Lin
  • Patent number: 10748846
    Abstract: A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer. The circuit may be disposed in the insulating layer. The circuit may be positioned below the pad. The first wiring may be disposed between the pad and the circuit. The second wiring may be disposed between the pad and the first wiring. The third wiring may be disposed between the pad and the second wiring. The pad contact may be configured to directly connect the pad to the circuit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Il Oh, Jung-Ha Oh, Hyuck-Joon Kwon, Jong-Hyuk Kim, Jong-Moon Yoon
  • Patent number: 10665594
    Abstract: A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure. The semiconductor substrate includes a memory cell region and a peripheral region. The gate structure is disposed on the semiconductor substrate and disposed on the peripheral region. The gate structure includes a first conductive layer and a gate capping layer. The gate capping layer is disposed on the first conductive layer. The first spacer structure is disposed on a sidewall of the first conductive layer and a sidewall of the gate capping layer. The gate connection structure includes a first part and a second part. The first part penetrates the gate capping layer and is electrically connected with the first conductive layer. The second part is connected with the first part, and the second part is disposed on and contacts a top surface of the gate capping layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 26, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Shih-Fang Tzou
  • Patent number: 10622992
    Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 14, 2020
    Assignee: pSemi Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 10596910
    Abstract: Provided are a power receiving unit suppressing temperature rise of at least one of a coil and a capacitor, and a power supply system having the power receiving unit. The power receiving unit includes a coil and a capacitor body used for noncontactly receiving the power transmitted from the power supply device, and a receiving side case including therewithin a space housing the coil and the capacitor body. A pace K inside the receiving side case is wholly filled with heat conduction member.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: March 24, 2020
    Assignee: Yazaki Corporation
    Inventors: Takahiro Nakahara, Ryohei Nishizaki, You Yanagida
  • Patent number: 10541279
    Abstract: A display device includes a display panel, and a touch sensing unit on the display panel, the touch sensing unit including a first conductive pattern on the display panel, an insulating layer covering the first conductive pattern, and a second conductive pattern on the insulating layer, partially crossing the first conductive pattern, and having a thickness that is greater than a thickness of the first conductive pattern.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chiwook An, Doyeon Kim, Sunghyun Park, Jaehyun Lee, Sung-woong Cho
  • Patent number: 10522465
    Abstract: A semiconductor device may include: a semiconductor substrate; an interlayer insulating film; a contact plug penetrating the interlayer insulating film; a first metal layer covering a surface of the interlayer insulating film; a protective insulating film covering a part of of the first metal layer; and a second metal layer covering the surface of the first metal layer. A peripheral region may be a region in which the protective insulating film is located; an active region may be a region in which a plurality of first parts of the contact plug is located; and an intermediate region may be a region which is located between the peripheral region and the active region and in which a second part of the contact plug is located. The first parts may extend toward an edge portion of the protective insulating film, and the second part may extend along the edge portion.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: December 31, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Jun Okawara
  • Patent number: 10522468
    Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Te Ho, Ming-Chung Liang, Chien-Chih Chiu, Chien-Han Chen
  • Patent number: 10510785
    Abstract: The present disclosure provides a method for manufacturing a TFT substrate and a method for manufacturing a TFT display apparatus, including the steps of: providing a base substrate; forming a source/drain metal layer on the base substrate; depositing a photoresist layer on the source/drain metal layer and patterning the photoresist layer to form a desired pattern of the photoresist layer; using a BCl3 gas to remove metal oxides generated on surface of the source/drain metal layer with air; and using a mixing gas including a Cl2 gas and the BCl3 gas to etch the source/drain metal layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: December 17, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Songshan Li
  • Patent number: 10504959
    Abstract: A lower dielectric layer is disposed on a semiconductor substrate. A plurality of peripheral lower wirings are disposed on a peripheral region of the semiconductor substrate and in the lower dielectric layer. An upper dielectric layer is disposed on the lower dielectric layer and covers the plurality of peripheral lower wirings. A mold layer is disposed on the upper dielectric layer and includes an etching stopper layer. A peripheral upper wiring penetrates the mold layer and the upper dielectric layer to be connected to at least one of the plurality of peripheral lower wirings. The peripheral upper wiring includes a wiring portion, a first via portion extending downwardly from a bottom surface of the wiring portion, and a second via portion extending downwardly from the bottom surface of the wiring portion.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghoon Bak, Kwangil Shin
  • Patent number: 10446325
    Abstract: A capacitor structure is disclosed. The capacitor structure includes a substrate, and a first electrode disposed on the substrate, the first electrode including a conductive layer, a first conductive post electrically connected to the conductive layer and a second conductive post electrically connected to the conductive layer. The capacitor structure further includes a planarization layer disposed on and covering the first electrode, the planarization layer disposed in a space between the first conductive post and the second conductive post, a first dielectric layer disposed on the planarization layer and in the space between the first conductive post and the second conductive post, and a second electrode disposed on the first dielectric layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Chi-Chang Lee
  • Patent number: 10438886
    Abstract: A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least-one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer. The circuit may be disposed in the insulating layer. The circuit may be positioned below the pad. The first wiring may be disposed between the pad and the circuit. The second wiring may be disposed between the pad and the first wiring. The third wiring may be disposed between the pad and the second wiring. The pad contact may be configured to directly connect the pad to the circuit.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Il Oh, Jung-Ha Oh, Hyuck-Joon Kwon, Jong-Hyuk Kim, Jong-Moon Yoon
  • Patent number: 10374010
    Abstract: Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 10283597
    Abstract: A semiconductor device structure including a scandium (Sc)- or yttrium (Y)-containing material layer situated between a substrate and one or more overlying layers. The Sc- or Y-containing material layer serves as an etch-stop during fabrication of one or more devices from overlying layers situated above the Sc- or Y-containing material layer. The Sc- or Y-containing material layer can be grown within an epitaxial group III-nitride device structure for applications such as electronics, optoelectronics, and acoustoelectronics, and can improve the etch-depth accuracy, reproducibility and uniformity.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 7, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew T. Hardy, Brian P. Downey, David J. Meyer
  • Patent number: 10249704
    Abstract: A capacitor that includes a conductive porous base material with a porous part; an upper electrode opposite the porous part, the upper electrode having, as its main constituent, a material selected from one of ruthenium, platinum, and an alloy of ruthenium and platinum; and a dielectric layer between the upper electrode and the conductive porous base material.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: April 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiromasa Saeki, Naoki Iwaji, Hiroshi Nakagawa, Junichi Yoshida
  • Patent number: 10194529
    Abstract: A partial metal fill is provided within the footprint of an ultra-thick-metal (UTM) conductor on a dielectric layer to strengthen the dielectric layer to inhibit delamination of the UTM conductor without inducing significant electrical coupling between the UTM conductor and the partial metal fill.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Guoqing Chen
  • Patent number: 10181472
    Abstract: The present disclosure provides a memory cell. The memory cell includes a substrate, a deep trench capacitor formed in the substrate, and a vertical transistor formed on the substrate and electrically connected to the deep trench capacitor. The vertical transistor includes a source region and a drain region stacked on the substrate, a channel region vertically sandwiched between the source region and the drain region, and a gate structure annularly wrapping around the channel region.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: January 15, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ching-Chia Huang
  • Patent number: 10170541
    Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-young Yi, Youn-seok Choi, Young-min Ko, Mun-jun Kim, Hong-gun Kim, Seung-heon Lee
  • Patent number: 10141048
    Abstract: A memory device including a plurality of memory cells arranged in a crossbar configuration for a neural network is provided. Each of the memory cells includes a readout transistor, a charging transistor, a discharging transistor, and a stack capacitor array connected to one of source/drain regions of each of the charging transistor and the discharging transistor and a functional gate of the readout transistor for storing analog information.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10131534
    Abstract: This disclosure provides systems, methods and apparatus for a via structure. In one aspect, an apparatus includes a substrate and a first electromechanical systems device on a surface of the substrate. The first electromechanical systems device includes a first metal layer and a second metal layer. A first via structure can be included on the surface of the substrate. The first via structure includes the first metal layer, the second metal layer, and a third metal layer. The first metal layer of the first electromechanical systems device may be the same metal layer as the first metal layer of the first via structure.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: November 20, 2018
    Assignee: SnapTrack, Inc.
    Inventors: Yaoling Pan, Lixia Zhou
  • Patent number: 10096665
    Abstract: A second data transfer line that is coupled to a gate layer of a drive transistor is formed in a layer higher than the gate layer, and a transfer capacitor is formed in a layer higher than a layer having the second data transfer line. A first data transfer line to which a data signal is supplied is formed in a layer higher than a layer having the transfer capacitor.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: October 9, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hitoshi Ota, Ryoichi Nozawa
  • Patent number: 10090410
    Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng Chi, Tenko Yamashita, Chen Zhang
  • Patent number: 10083958
    Abstract: Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. The metal-insulator-metal capacitor includes a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sukeshwar Kannan, Somnath Ghosh, Daniel Smith, Luke England
  • Patent number: 10020051
    Abstract: A memory device including a plurality of memory cells arranged in a crossbar configuration for a neural network is provided. Each of the memory cells includes a readout transistor, a charging transistor, a discharging transistor, and a stack capacitor array connected to one of source/drain regions of each of the charging transistor and the discharging transistor and a functional gate of the readout transistor for storing analog information.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10020232
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 10, 2018
    Assignee: Intel Corporation
    Inventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
  • Patent number: 10014252
    Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu
  • Patent number: 9960168
    Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Benjamin Ryan Cipriany, Ramachandra Divakaruni, Brian J. Greene, Ali Khakifirooz, Byeong Yeol Kim, William Larsen Nicoll
  • Patent number: 9960079
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Todd B. Myers, Nicholas R. Watts, Eric C. Palmer, Jui Min Lim
  • Patent number: 9941484
    Abstract: An organic light emitting display (OLED) device includes a substrate, a plurality of first electrodes, a plurality of light emitting layers, a second electrode, a power supply line, a third electrode, and an encapsulation member. The third electrode that is formed on the power supply line and the second electrode that is formed on the light emitting layers extend to a contact region that is in a peripheral region of the substrate. The third electrode and the second electrodes have an uneven pattern in the contact region.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 10, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yong-Jin Kim
  • Patent number: 9935007
    Abstract: A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: April 3, 2018
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Moon
  • Patent number: 9917092
    Abstract: A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 13, 2018
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Youichi Okita, Hideki Ito, Wensheng Wang
  • Patent number: 9899409
    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Eun Lee, Sunghoon Kim
  • Patent number: 9893212
    Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhihong Chen, Shu-Jen Han, Siyuranga O. Koswatta, Alberto Valdes Garcia
  • Patent number: 9866212
    Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 9, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9812455
    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: November 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
  • Patent number: 9728337
    Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: August 8, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SA
    Inventors: Yann Lamy, Olivier Guiller, Sylvain Joblot
  • Patent number: 9721960
    Abstract: Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. Each of the 7 different pillars is immediately adjacent to six neighboring pillars. A distance to two of the six neighboring pillars is a short distance, ds; and a distance to four of the six neighboring pillars is a long distance, dl. Some embodiments include an apparatus having semiconductor pillars in a packing arrangement. The packing arrangement comprises alternating first and second rows, with pillars in the first rows being laterally offset relative to pillars in the second rows. A distance between neighboring pillars in a common row as one another is a short distance, ds, and a distance between neighboring pillars that are not in common rows as one another is a long distance, dl.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 1, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9711449
    Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 18, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Gerrit J. Leusink, Cory Wajda, Tadahiro Ishizaka, Takahiro Hakamata
  • Patent number: 9691841
    Abstract: A semiconductor device includes an insulating layer formed on a substrate, and a capacitor including first and second electrodes formed in the insulating layer, wherein a lower surface of the first electrode is formed to have a greater depth than a lower surface of the second electrode in the insulating layer.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: June 27, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung Lae Oh, Chang Man Son, Sang Hyun Sung, Dae Hun Kwak
  • Patent number: 9595956
    Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: March 14, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9558994
    Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wookyung You, Sanghoon Ahn, Sangho Rha, Jongmin Baek, Nae-In Lee
  • Patent number: RE47311
    Abstract: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: March 19, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Erh-Kun Lai