Abstract: A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

Abstract: In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

Abstract: A cell structure of a semiconductor device includes an active region, having a concave portion, and an inactive region that defines the active region. A gate pattern in the active region is arranged perpendicular to the active region. A landing pad on the active region and the inactive region contacts the active region. A bit line pattern on the inactive region intersects the gate pattern perpendicularly, the bit line pattern being electrically connected to the landing pad and having a first protrusion corresponding to the concave portion of the active region.

Abstract: Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

Abstract: In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate.

Abstract: Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.

Abstract: A semiconductor memory device includes a titanium layer and a titanium nitride layer formed on a substrate, a thin layer formed on the titanium nitride layer, and a metal layer formed on the thin layer, wherein the thin layer increases a grain size of the metal layer.

Abstract: The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.

Abstract: A method of realizing a flash floating poly gate using an MPS process can include forming a tunnel oxide layer on an active region of a semiconductor substrate; and then forming a first floating gate on and contacting the tunnel oxide layer; and then forming second and third floating gates on and contacting the first floating gate, wherein the second and third floating gates extend perpendicular to the first floating gate; and then forming a poly meta-stable polysilicon layer on the first, second and third floating gates; and then forming a control gate on the semiconductor substrate including the poly meta-stable polysilicon layer. Therefore, it is possible to increase the surface area of the capacitor by a limited area in comparison with a flat floating gate. As a result, it is possible to improve the coupling ratio essential to the flash memory device and to improve the yield and reliability of the semiconductor device.

Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.

Abstract: In an eDRAM-type semiconductor device, a dynamic random access memory (DRAM) section and a logic circuit section are formed on a semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. A first capacitor is formed in the insulating layer at the DRAM section, the first capacitor defining a part of memory cell of the DRAM section. A second capacitor is formed in the insulating layer at the logic circuit section. The first capacitor comprises a lower electrode layer formed on an inner wall face of a hole formed in the insulating layer, and the second capacitor comprises a first lower electrode layer portion formed on an inner wall face of a groove formed in the insulating layer, and a second lower electrode layer portion formed on a surface of the insulating layer so as to be integrated with the first lower electrode portion.

Abstract: A semiconductor memory device in which a plurality of capacitors each including a columnar lower electrode, a capacitor insulation film and an upper electrode are stacked with interlayer films therebetween, a contact plug connects an upper face of each lower electrode of a lower layer with a bottom face of each lower electrode of an upper layer, and another contact plug connects upper electrodes of the capacitors in respective layers with each other.

Abstract: The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes within a capacitor array area over a substrate. The capacitor electrodes comprise outer lateral sidewalls. The plurality of capacitor electrodes is supported at least in part with a retaining structure which engages the outer lateral sidewalls. The retaining structure is formed at least in part by etching a layer of material which is not masked anywhere within the capacitor array area to form said retaining structure. The plurality of capacitor electrodes is incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: A method that includes forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a dielectric material, forming a cavity by removing the sacrificial material from under the dielectric material, and forming a gate in the cavity. System and devices are also provided.

Abstract: An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.

Abstract: In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.

Abstract: A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that it includes the source and drain regions of the plurality of first transistors and that the depth of the impurity region is greater than the depth of the source and drain regions. The impurity region sets the threshold voltage of the first transistors.

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.

Abstract: A capacitance cell 21 is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T1 and T2 orthogonally to opposed lateral end faces out of lateral end faces X1, X2, Y1, and Y2 that section the cell in a plane direction. Contact surfaces of electrode surfaces T1 and T2 with the lateral end faces are second connection terminals T12 and T22. For longitudinal pathways, first and second via contact layers V1 and V2are connected. The first via contact layer V1 interconnects the wiring layers Ma and Mb. The second via contact layer V2 is connected to a wiring layer located outside beyond an upper or lower end face Z2, Z1. The second via contact layer V2 is connected to a first connection terminal T11, T21 located on the upper or lower end faces Z2, Z1. The capacitance cells 21 are linked via the first and second connection terminals so that a capacitance element having a free shape is formed.

Abstract: A liquid crystal display array board includes a plurality of gate wiring lines formed on a substrate and a plurality of data wiring lines crossing the plurality of gate wiring lines, a plurality of thin film transistors formed in areas defined by crossings of the gate wiring lines and the data wiring lines, a plurality of storage capacitor first electrodes that run parallel to the gate wiring lines and patterned to have concavo-convex patterns, a plurality of storage capacitor second electrodes integrated with the drain electrodes of the thin film transistors and formed on the storage capacitor first electrodes, and a plurality of pixel electrodes electrically connected to the drain electrodes.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.

Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

Abstract: A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes.

Abstract: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

Abstract: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and the upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

Abstract: A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a re-distribution layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the re-distribution layer.

Abstract: A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.

Abstract: A partition-wall structure having a concave portion corresponding to a pattern formed by a functional liquid, including: a first concave portion provided corresponding to a first pattern; a second concave portion provided corresponding to a second pattern that is coupled to the first pattern and whose width is smaller than a width of the first pattern; and a convex portion provided in the first pattern.

Abstract: In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature a within the reaction chamber at from about 0° C. to less than 300° C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.

Abstract: In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface of the dielectric layer along the profile of the lower electrode and a second sub-electrode is continuously formed on the first sub-electrode corresponding to the top surface of the lower electrode, so an opening portion of the lower electrode is covered with the second sub-electrode. The first and second sub-electrodes include first and second metal nitride layers in which first and second stresses are applied, respectively. Directions of the first and second stresses are opposite to each other. Accordingly, cracking is minimized in the upper electrode with the high dielectric constant, thereby reducing current leakage.

Abstract: In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.

Abstract: A high surface area capacitor structure includes a storage electrode with recesses. An upper surface of the storage electrode has a maze-like appearance. Low elevation regions of a hemispherical grain polysilicon layer may remain on the upper surface of the storage electrode. The storage electrode or portions thereof may be lined or coated with dielectric material. The dielectric material may space a cell electrode of the high surface area capacitor structure apart from the storage electrode. One or both of the storage electrode and the cell electrode may be formed from polysilicon. Intermediate structures, which include mask material over contiguous low elevation regions of a layer of hemispherical grain polysilicon, which may have a maze-like appearance, and apertures located laterally between the low elevation regions of the layer of hemispherical grain polysilicon, are also disclosed.

Abstract: A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.

Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.

Abstract: The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.

Abstract: A process for producing structures in a semiconductor zone, has the steps of a) producing a trench (2) in the semiconductor zone (18), b) filling the trench with a photoresist (19), and c) exposing the photoresist (19) using ion beams (20), d) developing the photoresist (19). The energy density and ion dose for the ion beams (20) are selected in such a way that the photoresist (19) is only chemically changed at defined depths, so as to produce two regions, in the first region (21) of which the photoresist has been chemically changed at the defined depths by the ion beams (20), and in the second region of which the photoresist has been left chemically unchanged, so that during the developing step the photoresist is removed in precisely one of the two regions.

Abstract: A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape.

Abstract: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.

Abstract: Method for solving the problem caused when forming a crown-structure capacitor in a trench which is formed in an insulating film, and having difficulty in electrical by connecting a first upper electrode formed on the inside wall of the trench and a second upper electrode which is to be a plate because of the intervention of dielectric between the first and second upper electrodes. The conducting state of the first upper electrode and the plate upper electrode is ensured by utilizing a tantalum oxide film formed on a titanium nitride film, which is brought to a completely conducting state when heat treated. A crown structure is formed without removing the insulating film, in which a trench has been formed, by wet etching, whereby a stacked trench capacitor, which has double the capacity is provided while eliminating the collapse of the lower electrode or pair bit defect.

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.

Abstract: A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.