Abstract: A capacitor for a semiconductor device includes a lower electrode, a dielectric layer formed on a lower electrode, and an upper electrode formed on the dielectric layer. The lower electrode includes a first layer having a cylindrical shape and a mesh second layer formed on inner sidewalls and the bottom surface of the first layer. Beneficially, the first layer is connected to a conductive region of a semiconductor substrate by a contact plug. The lower electrode can be formed by injecting a catalyst into an opening in which the cylindrical first layer is to be formed before forming the cylindrical first layer.

Abstract: A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

Abstract: The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an auxiliary structure is arranged on the substrate adjacent to the useful structure, the auxiliary structure having an auxiliary structure side edge, wherein the useful structure side edge is opposite to the auxiliary structure side edge separated by a distance, and wherein the auxiliary structure useful structure distance is dimensioned such that a form of the useful structure side edge or a form of the substrate next to the useful structure side edge differs from a form in a device where there is no auxiliary structure.

Abstract: A capacitor assembly has a substrate, a first conductive auxiliary layer on the substrate, a capacitor dielectric, a second conductive auxiliary layer and a contact electrode. Thereby the first conductive auxiliary layer is connected to the capacitor dielectric within a first boundary area and the second conductive auxiliary layer is connected to the capacitor dielectric within a second boundary area. Thereby, an effective capacitor area is present where the first boundary area and the second boundary area overlap across the capacitor dielectric. The contact electrode is connected to the first conductive auxiliary layer in a contacting area, wherein the contacting area is disposed on a surface of the first conductive auxiliary layer opposite to the first boundary area and overlaps the effective capacitor area partly or not at all, so that at least part of the first conductive auxiliary layer within the effective capacitor area is adjacent to the substrate or not to the contact electrode.

Abstract: The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electrode, a dielectric layer (10) on the trench wall as capacitor dielectric and a metallic filler material (30?) provided in the trench (2) as second electrode. Above the conducting metallic filling material (30?) a dielectric filling material (35) is provided in the trench (2) with a cavity (40) provided for mechanical tensions. The invention further relates to a corresponding method of production.

Abstract: Memory cell having a trench capacitor that is constructed in a lower region of a substantially perpendicular trench hole, and which comprises an inner and an outer electrode, a dielectric layer being arranged between the inner and the outer electrodes, a vertical selection transistor that has a substantially perpendicular channel region, which is constructed adjacent to an upper region of the trench hole and which connects the inner electrode of the trench capacitor to a bit line, it being possible to construct a conductive channel as a function of the potential of a word line in the channel region, the channel region partially enclosing the trench hole in its upper region, and the associated work line at least partially surrounding the channel region.

Abstract: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.

Abstract: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.

Abstract: The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 40° C. higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.

Abstract: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.

Abstract: In a semiconductor device having a concave-type capacitor, HSG silicon is formed on a side surface of a lower electrode while no HSG silicon is formed on a bottom of the lower electrode.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: A capacitor structure comprises a plurality of cylinders and a supporting ring positioned among the plurality of cylinders and connecting a portion of the sidewall of each cylinder. The cylinders can be hollow circular cylinders, and the supporting ring can be positioned on a top portion of the cylinders. The capacitor structure may comprise a plurality of supporting rings and a hard mask separating these supporting rings from each other. The supporting rings and the hard mask are made of different material; for example, the supporting rings can be made of silicon oxide or aluminum oxide, and the hard mask can be made of silicon oxide or polysilicon. The capacitor structure comprises a first electrode positioned in the hollow circular cylinder, a dielectric layer positioned on the surface of the first electrode and a second electrode positioned on the surface of the dielectric layer.

Abstract: A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.

Abstract: A semiconductor device includes cylindrical capacitors each including corresponding cylindrical electrodes. Each cylindrical electrode includes hemispherical silicon grains. The hemispherical silicon grains protruding from an upper region of the cylindrical electrode have a large size, and the hemispherical silicon grains protruding from a lower region of the cylindrical electrode have a small size or the lower region of the cylindrical electrode has no hemispherical silicon grains.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A three-dimensional capacitor structure has a first conductive layer, a second conductive layer disposed above the first conductive layer, and a plug layer disposed therebetween. The first conductive layer includes a plurality of grid units arranged in a matrix, where in odd rows of the matrix, a first conductive grid is located in each odd column, and a first circular hole is located in each even column. Additionally, a first conductive island is located within each first circular hole. The pattern of the second conductive grids, the second circular holes, and the second conductive island of the second conductive layer is mismatched with that of the first conductive layer. The plug layer has a plurality of plugs disposed in between each first conductive island and each second conductive grid, and in between each first conductive grid and each second conductive island.

Abstract: In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.

Abstract: A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

Abstract: In a capacitor of a semiconductor device, a bottom electrode is formed on a substrate and has an uneven top surface. An interlayer insulation layer is formed on the substrate and has a via hole exposing the top surface of the bottom electrode. A dielectric layer is formed unevenly on the bottom electrode. A top electrode is formed on the dielectric layer while filling the via hole.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract: This integrated circuit comprises a capacitor (23) formed above a substrate (1) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure (7) for connection to the capacitor. The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.

Abstract: A method of processing a for an electronic device, comprising, at least: a nitridation step (a) of supplying nitrogen radicals on the surface of the electronic device substrate, to thereby form a nitride film on the surface thereof; and a hydrogenation step (b) of supplying hydrogen radicals to the surface of the electronic device substrate. By use of this method, it is possible to recover the degradation in the electric property of an insulating film due to a turnaround phenomenon which can occur at the time of nitriding an Si substrate, etc.

Abstract: A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer, a second metal layer having a buried metal layer, and a second metal wiring layer are sequentially connected. Within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.

Abstract: A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film. The dielectric film of the capacitive element is crystallized. The first and second conductive films are made of a polycrystal of an oxide, a nitride or an oxynitride of a noble metal.

Abstract: Apparatus for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce an increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.

Abstract: A method of fabricating an MIM capacitor is provided, by which higher capacitance can be secured per unit volume or area by forming a dual-stack type capacitor to increase an effective area of the capacitor. The method includes patterning a first metal layer, forming a planarized second insulating layer having a trench exposing a portion of the patterned first metal layer, forming a second metal layer within the trench, forming a first dielectric layer on the second metal layer, forming first via holes exposing the patterned first metal layer, forming first plugs filling the trench and first via holes, forming a third metal layer thereover, forming a second dielectric layer on the third metal layer, forming a patterned fourth metal layer on the second dielectric layer, patterning the second dielectric layer and the third metal layer, forming a planarized third insulating layer having second via holes therein, and forming a patterned fifth metal layer on the third insulating layer.

Abstract: A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a layer of doped polysilicon within a container in an insulative layer disposed on a substrate; forming a barrier layer over the polysilicon layer within the container; removing the insulative layer to expose the polysilicon layer outside the container; nitridizing the exposed polysilicon layer at a low temperature, preferably by remote plasma nitridation; removing the barrier layer to expose the inner surface of the polysilicon layer within the container; and forming HSG polysilicon over the inner surface of the polysilicon layer. The capacitor can be completed by forming a dielectric layer over the lower electrode, and an upper electrode over the dielectric layer. The cup-shaped bottom electrode formed within the container defines an interior surface comprising HSG polysilicon, and an exterior surface comprising smooth polysilicon.

Abstract: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.

Abstract: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

Abstract: A method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains (HSG) is disclosed. The method begins by depositing a first amorphous silicon film, then depositing silicon nuclei, which will act as nucleation sites, on the amorphous film. After deposition of silicon nuclei, crystallization, and specifically HSG, is prevented by lowering temperature and/or raising pressure. Next a second amorphous silicon layer is deposited over the first layer and the nuclei. Finally an anneal is performed to induce crystallization from the embedded nuclei. Thus grains are formed from the silicon bulk, rather than from the surface, HSG is avoided, and a smooth polysilicon film with enhanced grain size is produced.

Abstract: A semiconductor device includes: an insulating underlying layer of which surface portion has a concave portion; a lower electrode formed on the underlying layer along the inner face of the concave portion; a capacitor insulating film formed on the lower electrode and made of a high-dielectric or a ferroelectric subjected to thermal treatment for crystallization; and an upper electrode formed on the capacitor insulating film. The lower electrode and the upper electrode are made of a material that generates tensile stress in the thermal treatment for the capacitor insulating film, and the upper end part of the side wall and the corner part at the bottom face of the concave portion of the underlying layer are rounded.

Abstract: A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so as not to expose parts of wafer, the aperture of the wafer becomes nearly cocoon-shaped with a constriction in the middle. Thereby, the peripheral length of the aperture can be increased without changing the occupation rate of the mask patterns in a cell. Further, the shape of the bottom of the aperture also becomes nearly cocoon-shaped with a constriction in the middle, and therefore it is possible to increase the mechanical strength of cylinders.

Abstract: An integrated capacitor on a packaging substrate. The integrated capacitor comprises a conductor plane, a first dielectric layer and a signal transmission layer. The conductor plane has an extrusion layer of a first thickness. The first extrusion layer and the conductor plane are made of the same material. The first dielectric layer is formed on the conductor plane. The signal transmission layer is formed on the first dielectric layer.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: An electronic component and method of production thereof is presented. The electronic component includes a first insulation layer, an upper metal layer on the first insulation layer, an electrically conductive structure integrated into the first insulation layer and formed as a capacitor with a first metal strip sequence, and a second metal strip sequence. Each of the first and second sequences are arranged congruently one above another and are connected to one another by via connections. The second sequence is arranged on both sides of the first sequence at identical lateral distances. The metal strips of the first and second sequences are arranged at the same level and are connected to different electrical potentials. The electrically conductive structure mechanically stabilizes the insulation layer under the action of mechanical force such as bonding of the upper metal layer or mounting of the electronic component.

Abstract: A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

Abstract: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.

Abstract: Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the semiconductor substrate. The dual stacked MIM capacitor includes a lower plate positioned, an upper plate electrically connected to the lower plate and positioned above the lower plate, and an intermediate plate interposed between the lower plate and the upper plate. An upper interconnection line is positioned at the same level as the upper plate. The upper interconnection line is electrically connected to the intermediate plate. As a result, the upper plate may be formed by a damascene process.

Abstract: A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

Abstract: A memory circuit is provided with a spacer formed on a support surface and positioned adjacent to a first electrode surface of a first electrode. The memory circuit further includes a ferroelectric layer formed on the first electrode and the spacer.

Abstract: A ferroelectric capacitor including a bottom electrode which has a projecting portion, a top electrode, a ferroelectric layer and a dielectric layer formed between the bottom electrode and the top electrode. The dielectric layer is formed on a peripheral area of the bottom electrode. The ferroelectric layer is formed on the dielectric layer and on the projecting portion of the bottom electrode. As a result, a damaged layer which is formed during an etching process occurs at the ineffective area of the ferroelectric capacitor.

Abstract: The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.

Abstract: The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors. Individual of the capacitors include a storage node electrode, a capacitor dielectric region, and a cell electrode. The cell electrode is commonly shared among at least some of the plurality of memory cell capacitors within the memory array. The cell electrode within the memory array includes a conductor metal layer including at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride. Polysilicon is received over the conductor metal layer. The conductor metal layer and the polysilicon are received over the storage node electrodes of said at least some of the plurality of memory cell capacitors. Other aspects and implementations are contemplated.