Abstract: A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by the charge storage lamina or conductive layer; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina or conductive layer occupy collectively substantially all of the container region. A bit line terminal is coupled to the charge storage lamina through a switching structure.

Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

Abstract: The present invention includes a method of constructing a novel capacitor and geometry for the capacitor. The method and device include forming a multilayer structure having what generally can be described as a wave shape. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A semiconductor device includes a MOS transistor, interlayer dielectric film, first and second high-dielectric-constant films, and first and second conductive films. The MOS transistor is formed on a semiconductor substrate. The interlayer dielectric film is formed on the semiconductor substrate so as to cover the MOS transistor. The first high-dielectric-constant film is formed on the interlayer dielectric film and has an opening portion that reaches the interlayer dielectric film. The first conductive film contains a metal element and is formed to be partially embedded in the opening portion. The second high-dielectric-constant film is formed on the first conductive film. The second conductive film is formed on the second high-dielectric-constant film.

Abstract: In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.

Abstract: A semiconductor device, in which four pieces of strip-shaped electrodes, whose longitudinal directions are the same, are formed in each layer of a plurality of wiring layers that are provided by a same design rule with each other, simultaneously with regular wirings. In each wiring layer, two pieces each of first electrode and second electrode are formed parallelly with each other, alternately, and remote from each other. Then, the first electrodes formed in each layer are connected to each other by a first via, the second electrodes formed in each layer are connected to each other by a second via, a first structure body formed by connecting the first electrodes and the first via to each other is connected to a ground wiring, and a second structure body formed by connecting the second electrodes and the second via to each other is connected to a power source wiring.

Abstract: Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer is then selectively recessed with a peroxide mixture and subsequently the HSG silicon layer is recessed using tetramethyl ammoniumhydroxide. Thus, the bottom electrode is recessed below the level of particles which may overlie the memory cell capacitors and cause shorts by contacting the bottom electrode.

Abstract: A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film. The dielectric film of the capacitive element is crystallized. The first and second conductive films are made of a polycrystal of an oxide, a nitride or an oxynitride of a noble metal.

Abstract: A method used to form a semiconductor device comprises forming a layer such as a container capacitor layer having a bottom plate layer. The bottom plate layer is formed to define a receptacle, and a rim which defines an opening to an interior of the receptacle. The bottom plate layer is formed to have a smooth texture. Subsequently, an inhibitor layer is formed on the rim of the bottom plate layer while a majority of the receptacle defined by the bottom plate layer remains free from the inhibitor. With the inhibitor layer on the rim of the bottom plate layer, at least a portion of the receptacle is converted to have a rough texture, such as to hemispherical silicon grain (HSG) polysilicon, while subsequent to the conversion the smooth texture of the rim which defines the opening to the interior of the receptacle remains. A resulting structure is also described.

Abstract: A method for forming a trench capacitor. The method includes forming a trench in a semiconductor substrate. A conformal layer of semiconductor material is deposited in the trench. The surface of the conformal layer of semiconductor material is roughened. An insulator layer is formed outwardly from the roughened, conformal layer of semiconductor material. A polycrystalline semiconductor plate is formed outwardly from the insulator layer in the trench.

Abstract: Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.

Abstract: A semiconductor technique is provided which can achieve both of lowered resistance in a logic formation region and reduced leakage current of the capacitor of a memory device. Source/drain regions (4) are formed in the upper surface of a semiconductor substrate (1) in a memory formation region and cobalt silicide films (9) are formed in the upper surfaces of the source/drain regions (4). Source/drain regions (54) are formed in the upper surface of the semiconductor substrate (1) in a logic formation region and cobalt silicide films (59) are formed in the upper surfaces of the source/drain regions (54). The cobalt silicide films (59) in the logic formation region are thicker than the cobalt silicide films (9) in the memory formation region.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: The present invention relates to a gate structure of a flash memory cell and method of forming the same, and method of forming a dielectric film.

Abstract: A capacitor fabrication method may include forming a first capacitor electrode over a substrate and atomic layer depositing an insulative barrier layer to oxygen diffusion over the first electrode. A capacitor dielectric layer may be formed over the first electrode and a second capacitor electrode may be formed over the dielectric layer. The barrier layer may include Al2O3. A capacitor fabrication method may also include forming a first capacitor electrode over a substrate, chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode, and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer. A chemisorption product of the first and second precursors may be comprised by a layer of an insulative barrier material. The first precursor may include H2O and the second precursor may include trimethyl aluminum.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.

Abstract: Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

Abstract: Integrated circuit capacitors are provided having an electrically insulating electrode support layer having an opening therein on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

Abstract: An integrated circuit memory device includes a semiconductor substrate and a first electrically insulating layer that extends on the semiconductor substrate and has a first contact hole extending therethrough. An electrically conductive plug is provided in the first contact hole. A phase-change material layer pattern is provided as a non-volatile storage medium. The phase-change material layer pattern has a bottom surface that is electrically connected to the electrically conductive plug. A second electrically insulating layer is provided on the phase-change material layer pattern. The second electrically insulating layer has a second contact hole therein. This contact hole exposes a portion of an upper surface of the phase-change material layer pattern. To improve data writing efficiency, the area of the exposed portion of the upper surface of the phase-change material layer pattern is less than a maximum cross-sectional area of the electrically conductive plug. A plate electrode is also provided.

Abstract: A semiconductor element includes a semiconductor substrate; a film of electrode material on the substrate at a thickness corresponding to the height of a pair of confronting electrodes standing vertical; a gap in the film of electrode material at a position so that confronting surfaces of the electrodes are formed as having a width corresponding to an interval of the confronting surfaces of the electrodes; and an insulating film in the gap. Then, a pair of confronting electrodes is formed by etching the film of electrode material. An intermediate film is formed on the pair of confronting electrodes; plugs are connected to the pair of confronting electrodes through the intermediate film; and finally wiring is connected to the plugs.

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract: An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies.

Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.

Abstract: A structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a reference plate which splits into at least two prongs. Each of the prongs is surrounded by a lateral periphery. A dielectric material extends around the lateral peripheries of the prongs, and a storage node surrounds an entirety of the lateral peripheries of the prongs. The storage node is separated from the reference plate by at least the dielectric material. Also, the invention includes electronic systems comprising novel capacitor constructions.

Abstract: A FeRAM device in which a bottom electrode of a ferroelectric capacitor is connected to a source/drain region of a transistor and a top electrode is connected to a plate line. The FeRAM device comprises a semiconductor substrate; a gate electrode formed on the semiconductor substrate; an impurity region formed on each side of the gate electrode of the semiconductor substrate; a bottom electrode connected to the impurity region; an oxygen diffusion barrier layer formed on the bottom electrode; a ferroelectric layer formed on the oxygen diffusion barrier layer and the bottom electrode; and a top electrode formed on the ferroelectric layer.

Abstract: A phase changing memory device, and method of making the same, that includes contact holes formed in insulation material that extend down to and exposes source regions for adjacent FET transistors. Spacer material is disposed in the holes with surfaces that define openings each having a width that narrows along a depth of the opening. Lower electrodes are disposed in the holes. A layer of phase change memory material is disposed along the spacer material surfaces and along at least a portion of the lower electrodes. Upper electrodes are formed in the openings and on the phase change memory material layer. For each contact hole, the upper electrode and phase change memory material layer form an electrical current path that narrows in width as the current path approaches the lower electrode, such that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the upper and lower electrodes.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract: An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: Afin-type trench capacitor structure includes a buried plate diffused into a silicon substrate. The buried plate, which surrounds a bottle-shaped lower portion of the trench capacitor structure, is electrically connected to an upwardly extending annular poly electrode, thereby enabling the buried plate and the annular poly electrode to constitute a large-area capacitor electrode of the trench capacitor structure. A capacitor storage node consisting of a surrounding conductive layer, a central conductive layer and a collar conductive layer encompasses the upwardly extending annular poly electrode. A first capacitor dielectric layer isolates the capacitor storage node from the buried plate. A second capacitor dielectric layer and a third capacitor dielectric layer isolate the upwardly extending annular poly electrode from the capacitor storage node.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: A method of forming a device pattern of a semiconductor device. The method includes the steps of carrying out an over-exposure to a resist film using a mask which has transmission regions which are positioned about a circumference of each of intended patterns of a resist film. Then carrying out a development of the resist film to form a resist pattern having the intended patterns. And then forming a device pattern of a semiconductor device by use of the resist pattern.

Abstract: A capacitor includes an array of first conductive units and an array of second conductive units. Each of the first conductive units includes a hollow first conductive post that has lateral sides. The first conductive posts of the first conductive units are interconnected to form a grid that defines a plurality of lattices. Each of the second conductive units includes a second conductive post that is disposed in a respective one of the lattices and that has lateral sides that are surrounded by the lateral sides of the first conductive post of a respective one of the first conductive units. The first conductive post of each of the first conductive units and the second conductive post of the respective one of the second conductive units cooperatively define a charge space. A dielectric material fills the charge space.

Abstract: A method used to manufacture a semiconductor device comprises providing a first conductive container capacitor top plate layer and etching the first conductive container capacitor top plate layer to form a plurality of openings therein. Subsequently, a container capacitor bottom plate layer is formed within the plurality of openings in the top plate layer such that the bottom plate layer defines a plurality of openings. A second conductive container capacitor top plate layer is formed within the plurality of openings in the bottom plate layer. The first conductive container capacitor top plate layer is electrically coupled with the second conductive container capacitor top plate layer. The first and second conductive container capacitor top plate layers and the container capacitor bottom plate layer form a plurality of container capacitors. A structure resulting from the method is also disclosed.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: A capacitor formed in a substrate including a recess dug into a substrate; a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; a second layer of a conductive material covering the first layer; a third layer of a conductive or insulating material filling the recess; trenches crossing the third layer; a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges thereof; a fifth layer of a dielectric material covering the fourth layer; and a sixth layer of a conductive material covering the fifth layer.

Abstract: A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second metal wiring layer are sequentially connected. And within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C. When manufacturing the semiconductor device, the second layer-insulating layer is formed in such a way as to cover the metal wiring layer on the first layer-insulating layer. Removal is performed of at least respective parts, corresponding to a memory cell portion, of the first and the second layer-insulating layers. Thereafter, the capacitive element C is formed in regions corresponding to the removed portions of the first and the second layer-insulating layer.

Abstract: The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

Abstract: A semiconductor device is obtained that can prevent occurrence of a shape defect of a capacitor electrode in the semiconductor device or operation failure of the semiconductor device. A semiconductor device with the capacitor includes a second interlayer insulation film, an SC poly plug, a barrier metal and an SN electrode. The second interlayer insulation film has a through hole. The SC poly plug is formed within the through hole of the second interlayer insulation film. The barrier metal is formed on the SC poly plug. The SN electrode is formed on the barrier metal. The SN electrode is electrically connected to the SC poly plug with the barrier metal interposed therebetween. The barrier metal is a multilayer film including three layers of a tantalum nitride (TaN) film, a titanium nitride (TiN) film and a titanium (Ti) film.

Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

Abstract: A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: Disclosed is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: Corming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into the sidewall using the islands as a mask. The capacitor is completed by forming a node insulator on the pits and the sidewall; and filling said trench with a trench conductor.

Abstract: A honeycomb/webbed, high surface area capacitor formed by etching a storage poly using an etch mask having a plurality of micro vias. The etch mask is preferably formed by applying an HSG polysilicon layer on a surface of the storage poly with a mask layer being deposited over the HSG polysilicon layer. An upper portion of the mask layer is removed to expose the uppermost portions of the HSG polysilicon layer and the exposed HSG polysilicon layer portions are then etched, which translates the pattern of the exposed HSG polysilicon layer portions into the storage poly. The capacitor is completed by depositing a dielectric material layer over the storage poly layer and depositing a cell poly layer over the dielectric material layer.

Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium single crystalline layer or a dual layer in which a silicon-germanium single crystalline layer covers a silicon single crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium single crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a single crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium single crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium single crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.