Abstract: A device may generate a hypergraph for a plurality of cells included in a communications network. The device may identify one or more parameters for allocating operating transmission frequencies to the plurality of cells. The plurality of cells may correspond to vertices of the hypergraph, and one or more cumulative transmission interference regions, associated with the plurality of cells, may correspond to hyperedges of the hypergraph. The device may generate a constraint model based on the hypergraph and the one or more parameters. The device may determine, using a quantum solver, one or more minimum energy states of the constraint model. The one or more minimum energy states may correspond to respective operating transmission frequency allocation configurations for the plurality of cells. The device may assign, based on a minimum energy state of the one or more minimum energy states, operating transmission frequencies to the plurality of cells.

Abstract: A stacked quantum computing device including: a first chip including a superconducting qubit, where the superconducting qubit includes a superconducting quantum interference device (SQUID) region, a control region, and a readout region, and a second chip bonded to the first chip, where the second chip includes a first control element overlapping with the SQUID region, a second control element displaced laterally from the control region and without overlapping the control region, and a readout device overlapping the readout region.

Abstract: A method of forming a superconducting structure is provided that includes forming a superconducting element in a first dielectric layer, forming a protective pad formed from a resistive material over at least a portion of the superconducting element, forming a second dielectric layer overlying the first dielectric layer, and etching an opening through the second dielectric layer to the protective pad, such that no portion of the superconducting element is exposed in the opening. A cleaning process is performed on the superconducting structure, and a contact material fill with a resistive material is performed to fill the opening and form a resistive element in contact with the superconducting element through the protective pad.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.

Abstract: A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

Abstract: In a general aspect, information is encoded in data qubits in a three-dimensional device lattice. The data qubits reside in multiple layers of the three-dimensional device lattice, and each layer includes a respective two-dimensional device lattice. A three-dimensional color code is applied in the three-dimensional device lattice to detect errors in the data qubits residing in the multiple layers. A two-dimensional color code is applied in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubits residing in the respective layer.

Abstract: A quantum interference device includes a superconducting loop interrupted by a normal conductor segment, and an interferometer connected to the normal conductor segment, wherein the superconducting loop includes a plurality of turns. The turns can be a plurality of adjacent lobes. A coil can be located within a lobe of the superconducting loop. Optionally, a bridge layer (e.g., of gold) is formed above the substrate to make an electrical contact between a superconducting layer (e.g., of niobium) formed above the bridge layer and a normal conducting layer (e.g., of titanium) formed above the bridge layer. The bridge layer allows the device to be formed of superconducting and normal conducting material that are otherwise incompatible. A titanium normal conducting layer can be allowed to oxidize over a period of years.

Abstract: A quantum computing device includes: a first array of qubits arranged along a first axis; and a second array of qubits arranged along a second axis different from the first axis so that the qubits of the second array intersect with the qubits of the first array to form a lattice structure, in which each qubit in the first array is offset along the second axis relative to a directly adjacent qubit in the first array, each qubit in the second array is offset along the first axis relative to a directly adjacent qubit in the second array, and each intersection between a qubit from the first array and a qubit from the second array in the lattice structure comprises a coupler arranged to inductively couple the qubit from the first array to the qubit from the second array.

Abstract: Systems and method for applying security measures to data sets requiring external quantum-level processing. Specifically, segmenting a data set into a plurality of data blocks/segments, such that each data block is communicated to different external entities for subsequent quantum-level computing processing of the data blocks. Once the data blocks have been quantum-level processed by the external entities and returned to the data provider/owner, the data blocks are combined to re-form the data set.

Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.

Abstract: A quantum interference device includes a superconducting loop interrupted by a gap, a plurality of normal conductor segments bridging the gap; and an interferometer connected to the normal conductor segments, wherein the normal conductor segments are spaced apart. There may be 2N+1 normal conductor segments, where N is a positive integer, which may be of equal length and evenly spaced. The device produces a larger signal than a conventional quantum interference device.

Abstract: Systems and methods for determining timing paths and reconciling topology in a superconducting circuit design are provided. The design may include a first timing path having a first set of timing pins associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. An example method includes processing the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method further includes inserting a first shadow element representing a first physically connected component on the timing path, where the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method further includes addressing any changes to the first legal start time or the second legal start time caused by an insertion of the first shadow element on the timing path.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.

Abstract: An always-on, exchange-only (AEON) qubit is comprised of three two-level systems (e.g., semiconductor quantum dot or other spin encoded qubit) and can be operated at a “sweet spot” during both single qubit and two-qubit gate operations. The “sweet spot” operation is immune to variations in noise with respect to nontrivial detuning parameters defining the AEON. By operating at the “sweet spot,” both single and two-qubit gate operations can be performed using only exchange pulses (e.g., DC voltage pulses applied to tunneling gates).

Abstract: A magnetometer for measuring a magnetic flux and also the absolute magnetic flux, the magnetometer comprising a plurality of superconducting quantum devices (SQUIDs) connected in series, each SQUID including: a superconducting loop containing two Josephson junctions connected to each other in parallel; and a flux-focussing region, the flux-focussing region configured to generate a screening current in response to the magnetic flux, the screening current modulating the corresponding voltage response for each SQUID which is in-phase with the voltage response of each other SQUID in the array.

Abstract: Among other things, an apparatus comprises quantum units; and couplers among the quantum units. Each coupler is configured to couple a pair of quantum units according to a quantum Hamiltonian characterization of the quantum by the coupler.

Abstract: A flux-biasing device includes a set of magnetic flux generating members. A first magnetic flux generating member is configured to magnetically interact with a first qubit from a set of qubits of a quantum processor such that a first magnetic flux of the first member causes a first change in a first resonance frequency of the first qubit by a first frequency shift value. Each non-corresponding magnetic flux generating member of the set is well separated from qubits corresponding to other magnetic flux generating members of the set such that qubits corresponding to other members exhibit less than a threshold value of resonance frequency shift as a result of a magnetic flux of a non-corresponding member.

Abstract: Methods, systems, and apparatus for parallel optimization of continuously running quantum error correction by closed-loop feedback. In one aspect, a method includes continuously and effectively optimizing qubit performance in-situ whilst an error correction operation on the quantum system is miming. The method directly monitors the output from error detection and provides this information as feedback to calibrate the quantum gates associated with the quantum system. In some implementations, the physical qubits are spatially partitioned into one or more independent hardware patterns, where the errors attributable to each hardware pattern are non-overlapping. The one or more different sets of hardware patterns are then temporarily interleaved such that all physical qubits and operations are optimized. The method allows for the optimization of each section of a hardware pattern to be performed individually and in parallel, and can result is O(1) scaling.

Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.

Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.

Abstract: Examples described in this disclosure relate to a memory cell with Josephson phase-based torque. In one example, a memory cell including a first inductor and a magnetic Josephson junction (MJJ) coupled to the first inductor to form a loop is provided. The MJJ may include a free magnetic layer formed above a non-magnetic layer, and a fixed magnetic layer below the non-magnetic layer. A first state of the memory cell corresponds to a first magnetization of the free magnetic layer that is parallel to a magnetization of the fixed magnetic layer and the second state of the memory cell corresponds to a second magnetization of the free magnetic layer that is anti-parallel to the magnetization of the fixed magnetic layer. The memory cell is configured to switch from the first state to the second state based on whether the MJJ is in a zero-state or a ?-state.

Abstract: A technique relates a structure. An inductive element is on a first surface. A capacitive element is on the first surface and a second surface. An interconnect structure is between the first surface and the second surface.

Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: A method of forming a superconductor device structure is disclosed. The method comprises forming a base electrode in a first dielectric layer, forming a junction material stack over the base electrode, forming a hardmask over the junction material stack, etching away a portion of the junction material stack to form a Josephson junction (JJ) over the base electrode, and depositing a second dielectric layer over the hardmask, the JJ, the base electrode and the first dielectric layer. The method additionally comprises forming a first contact through the second dielectric layer to the base electrode to electrically couple the first contact to a first end of the JJ, and forming a second contact through the second dielectric layer and the hardmask to electrically coupled the second contact to a second end of the JJ.

Abstract: Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.

Abstract: A building block for a quantum information processing system includes a superconducting qubit having a Josephson junction connected between two superconducting electrodes. The two superconducting electrodes are coaxial and coplanar. The building block also includes a control line coupled to the superconducting qubit and arranged to control the state of the superconducting qubit, and/or a readout element coupled to the superconducting qubit and arranged to measure the state of the superconducting qubit. The control line and/or the readout element are arranged out of plane with respect to the two superconducting electrodes.

Abstract: Techniques regarding parallel gradiometric SQUIDs and the manufacturing thereof are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a first pattern of superconducting material located on a substrate. Also, the apparatus can comprise a second pattern of superconducting material that can extend across the first pattern of superconducting material at a position. Further, the apparatus can comprise a Josephson junction located at the position, which can comprise an insulating barrier that can connect the first pattern of superconductor material and the second pattern of superconductor material.

Abstract: Symmetrical qubits with reduced far-field radiation are provided. In one example, a qubit device includes a first group of superconducting capacitor pads positioned about a defined location of the qubit device, wherein the first group of superconducting capacitor pads comprise two or more superconducting capacitor pads having a first polarity, and a second group of superconducting capacitor pads positioned about the defined location of the qubit device in an alternating arrangement with the first group of superconducting capacitor pads, wherein the second group of superconducting capacitor pads comprise two or more superconducting capacitor pads having a second polarity that is opposite the first polarity.

Abstract: Systems and methods for employing macroscopic resonant tunneling operations in quantum processors are described. New modes of use for quantum processor architectures employ probe qubits to determine energy eigenvalues of a problem Hamiltonian through macroscopic resonant tunneling operations. A dedicated probe qubit design that may be added to quantum processor architectures is also described. The dedicated probe qubit enables improved performance of macroscopic resonant tunneling operations and, consequently, improved performance of the new modes of use described.

Abstract: A coil component has a first surface and a second surface facing each other. The coil component has a coil conductor formed into a spiral shape and having a central axis intersecting with the first surface and the second surface, an insulation resin body covering the coil conductor and including an inner diameter hole part corresponding to the central axis of the coil conductor and a magnetic resin body disposed on the first surface side of the insulation resin body without being disposed on the second surface side of the insulation resin body. The magnetic resin body is also disposed inside the inner diameter hole part of the insulation resin body.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.

Abstract: Various embodiments provide a coupling mechanism, method of activation and a square lattice. The coupling mechanism comprises two qubits and a tunable coupling qubit that activates an interaction between the two qubits by modulation of a frequency of the tunable coupling qubit. The tunable coupling qubit capacitively couples the two qubits. The tunable coupling qubit is modulated at a difference frequency of the two qubits. The difference frequency may be significantly larger than an anharmonicity of the two qubits. The tunable coupling qubit may be coupled to the two qubits by two electrodes separated by a superconducting quantum interference device (SQUID) loop having two Josephson junctions or by a single electrode with a SQUID loop coupling to ground. The SQUID loop is controlled by an inductively-coupled flux bias line positioned at the center of the tunable coupling qubit.

Abstract: A method for operating a quantum processing device is provided including at least two quantum circuits coupled to a tunable coupler, wherein the quantum circuits are subject to cross-talk, the method including: applying a primary signal to the quantum circuits so as to drive one or more energy transitions between states spanned by the quantum circuits; and applying a compensation signal to the tunable coupler, the compensation signal designed so as to shift at least one state spanned by the quantum circuits, in energy, to compensate for cross-talk between the quantum circuits. Related quantum processing devices and chips are also provided.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

Abstract: Aspects of the disclosure provide a method for configuring a Quantum Annealing (QA) device. Then QA device has a plurality of qubits and a plurality of couplers at overlapping intersections of the qubits. The method includes mapping a node of a neural network that have a plurality of nodes and connections between the nodes to a qubit in the QA device, and mapping a connection of the neural network to a coupler at an intersection in the QA device where two qubits corresponding to two nodes connected by the connection intersect. The method further includes mapping a node of the neural network to a chain of qubits. In an embodiment, a coupling between qubits in the chain is configured to be a ferromagnetic coupling in order to map the node of the neural network to the chain of qubits.

Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.

Abstract: A building block (1) for a quantum information processing system includes a superconducting qubit (2) having a Josephson junction (5) connected between two superconducting electrodes (3, 4). The two superconducting electrodes (3, 4) are coaxial and coplanar. The building block (1) also includes a control line (6) coupled to the superconducting qubit (2) and arranged to control the state of the superconducting qubit (2), and/or a readout element (8) coupled to the superconducting qubit (2) and arranged to measure the state of the superconducting qubit (2). The control line (6) and/or the readout element (8) are arranged out of plane with respect to the two superconducting electrodes (3, 4).

Abstract: Systems and methods are provided for readout of a qubit. A readout resonator is coupled to a transmission line and a compound Josephson junction coupler couples the qubit to the readout resonator. A coupling controller controls the coupling strength of the compound Josephson junction coupler such that a coupling between the qubit and the readout resonator is a first value when a state of the qubit is being read and a second value during operation of the qubit.

Abstract: A tunable bus-mediated coupling system is provided that includes a first input port coupled to a first end of a variable inductance coupling element through a first resonator and a second input port coupled to a second end of the variable inductance coupling element through a second resonator. The first input port is configured to be coupled to a first qubit, and the second output port is configured to be coupled to a second qubit. A controller is configured to control the inductance of the variable inductance coupling element between a low inductance state to provide strong coupling between the first qubit and the second qubit and a high inductance state to provide isolation between the first qubit and the second qubit.

Abstract: A qubit may be formed by forming a Josephson junction between two capacitive plates. The Josephson junction may be an aluminum/aluminum-oxide/aluminum trilayer Josephson junction on a substrate. The Josephson junction may be annealed with a thermal source. Annealing the Josephson junction may alter the frequency of the qubit.

Abstract: In this disclosure, example networks of coupled superconducting nanowires hosting MZMs are disclosed that can be used to realize a more powerful type of non-Abelian defect: a genon in an Ising×Ising topological state. The braiding of such genons provides the missing topological single-qubit ?/8 phase gate. Combined with joint fermion parity measurements of MZMs, these operations provide a way to realize universal TQC.

Abstract: Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.

Abstract: A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.

Abstract: An apparatus includes a line-termination circuit and a continuous-time linear equalizer circuit. The line-termination circuit may be configured to generate a data signal in response to an input signal. The input signal generally resides in a first voltage domain. The input signal may be single-ended. The data signal may be generated in the first voltage domain. The continuous-time linear equalizer circuit may be configured to generate an intermediate signal by equalizing the data signal relative to a reference voltage. The continuous-time linear equalizer circuit generally operates in a second voltage domain. The first voltage domain may be higher than the second voltage domain.

Abstract: A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.

Abstract: A braiding element and a method for operating the braiding device, a structure of braiding devices as well as an array of braiding devices for controlling parafermions for quantum computing may be provided. The braiding device comprises a first wire layer and a second wire layer, a superconductor layer arranged in vertical sandwich-style between the first and the second wire layer such that a device structure is built and a plurality cascades of gate electrodes such that one of the plurality of cascades of gate electrodes is arranged at the first quantum wire layer and at the second quantum wire layer of each of the three legs.

Abstract: A device may include one more processors to receive designed network information corresponding to a designed network; generate a data graph corresponding to a topology of the designed network based on the designed network information; receive discovered network information corresponding to discovered network devices of a discovered network; generate a query graph corresponding to the discovered network based on the discovered network information; perform a validation analysis of a topology of the discovered network relative to the topology of the designed network based on the data graph and the query graph; and/or perform an action based on a result of the validation analysis.

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.