Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Abstract: A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

Abstract: A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

Abstract: A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The no-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.

Abstract: Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to the active pillar, the charge storage layer being disposed between the active pillar and the gates. Before depositing a gate, a bulk substrate is etched using a dry etching to form a vertical active pillar which is in a single body with a semiconductor substrate.

Abstract: A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2 ) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3 ), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3 ?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: A split gate type nonvolatile semiconductor memory device having a FinFET structure includes a semiconductor substrate, parallel trenches on a surface of the semiconductor substrate, and select and memory gate electrodes perpendicular to the trenches. While either the select or the memory gate electrodes are formed prior to the other gate electrodes, each remaining gate electrode is formed adjacent to a side wall of each of the gate electrodes. The semiconductor memory device includes source/drain regions each formed between each pair of the select gate electrodes and between each pair of the memory gate electrodes in protruding portions between each pair of the trenches. A difference between heights of the select gate electrodes and the memory gate electrodes is equal to or greater than a difference between heights of insulation layers formed on the bottom of each of the trenches and the source/drain regions.

Abstract: A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.

Abstract: A memory cell of a non-volatile memory device, comprises: a select transistor gate of a select transistor on a substrate, the select transistor gate comprising: a gate dielectric pattern; and a select gate on the gate dielectric pattern; first and second memory cell transistor gates of first and second memory cell transistors on the substrate at opposite sides of the select transistor, each of the first and second memory cell transistor gates comprising: a tunnel insulating layer pattern; a charge storage layer pattern on the tunnel insulating layer pattern; a blocking insulating layer pattern on the charge storage layer pattern; and a control gate on the blocking insulating layer pattern; first and second floating junction regions in the substrate between the select transistor gate and the first and second memory cell transistor gates respectively; and first and second drain regions in the substrate at sides of the first and second memory cell transistor gates respectively opposite the first and second float

Abstract: A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention includes a memory cell including, a charge storage layer on a gate insulating film, a multilayer insulator on the charge storage layer, and a control gate electrode on the multilayer insulator, the gate insulating film including a first tunnel film, a first high-dielectric-constant film on the first tunnel film and offering a greater dielectric constant than the first tunnel film, and a second tunnel film on the first high-dielectric-constant film and having the same configuration as that of the first tunnel film, the multilayer insulator including a first insulating film, a second high-dielectric-constant film on the first insulating film and offering a greater dielectric constant than the first insulating film, and a second insulating film on the second high-dielectric-constant film and having the same configuration as that of the first insulating film.

Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

Abstract: The semiconductor device has a stacked structure in which a tunnel oxide layer, a charge trapping layer, a blocking oxide layer, and a gate electrode are sequentially formed on a silicon substrate, wherein the blocking oxide layer includes a crystalline layer disposed adjacent to the charge trapping layer and an amorphous layer disposed adjacent to the gate electrode.

Abstract: A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.

Abstract: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.

Abstract: A method for manufacturing trench MOSFET device with low gate charge includes the steps of providing a substrate of first conductivity type; forming an epitaxial layer of first conductivity type on the substrate; forming a body region of second conductivity type in the epitaxial layer, the body region extends downwards from the surface of the epitaxial layer; forming a plurality of trenches in the epitaxial layer, the body region having the trenches formed therethrough; forming a first insulating layer on the body region and on an inner surface of each trench; forming a ploy-silicon spacer on the first insulating layer on an inner side-wall of each trench; filling a dielectric structure in the lower portion of each trench; and filling a ploy-silicon structure on top of the dielectric structure in each trench. Through the trench MOSFET device, the gate capacitance and resistance thereof are reduced so the performance is increased.

Abstract: In a nonvolatile semiconductor memory device, a tunnel insulating layer, a charge storage layer and a charge block layer are formed on a silicon substrate in this order, and a plurality of control gate electrodes are provided above the charge block layer. Moreover, a cap layer made of silicon nitride is formed between the charge block layer and each of the control gate electrode, the cap layer being divided for each gate control electrode.

Abstract: A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.

Abstract: A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions. The insulating structure wraps around the channel bridge, and the gate wraps around the insulating structure.

Abstract: Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.

Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract: A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the inner side wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate.

Abstract: A semiconductor device suppresses short-circuit failure between a selection gate electrode and a control gate electrode while shortening the distance between the upper portions of the selection gate electrode and the control gate electrode. The device includes an impurity region formed on both sides of a channel region of a semiconductor substrate; a selection gate electrode on the channel region via a gate insulating film; a control gate electrode in the shape of sidewall via a gate isolation insulating film on both side surfaces of the selection gate electrode and on the surface of the channel region; a protective insulating film covering the sidewall of the control gate electrode; and a silicide layer on the selection gate electrode. The protective insulating film is a two-layer structure of a silicon nitride film covering the sidewall of the control gate electrode and a silicon oxide film covering the silicon nitride film.

Abstract: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

Abstract: A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second semiconductor layer provided in contact with the first semiconductor layer. A third lamination part includes: a plurality of first contact layers formed in contact with the respective second lamination part, extending to a first direction perpendicular to the lamination direction, and in line with each other along a second direction perpendicular to the first direction; and a plurality of contact plug layers formed in contact with any one of the first contact layers and extending to the lamination direction. The contact plug layers are arranged at different positions relative to each other in the first direction.

Abstract: A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.

Abstract: Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.

Abstract: A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

Abstract: A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films.

Abstract: To improve characteristics of a semiconductor device having a nonvolatile memory. There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by transferring a charge to/from a charge storage film, wherein the nonvolatile memory cell includes a p well formed in a principal plane of a silicon substrate, and a memory gate electrode formed over the principal plane across the charge storage film, and wherein a memory channel region located beneath the charge storage film of the principal plane of the silicon substrate contains fluorine.

Abstract: Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to the active pillar, the charge storage layer being disposed between the active pillar and the gates. Before depositing a gate, a bulk substrate is etched using a dry etching to form a vertical active pillar which is in a single body with a semiconductor substrate.

Abstract: First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode. The first channel includes a first-conductivity-type region and a second-conductivity-type region which is formed on at least a part of the first-conductivity-type region and whose conductivity type is opposite to the first conductivity type. The third channel includes the first-conductivity-type region and the second-conductivity-type region formed on the first-conductivity-type region. The number of data stored in the first memory cell is smaller than that of data stored in the second memory cell.

Abstract: Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.

Abstract: The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide, a first control gate electrode, and a first source/drain region. The select transistor includes a third insulating film on the semiconductor substrate, a fourth insulating film made of an aluminum oxide containing at least one of a tetravalent cationic element, a pentavalent cationic element, and N (nitrogen), a second control gate electrode, and a second source/drain region.

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

Abstract: A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

Abstract: A non-volatile memory device includes a semiconductor substrate having a first section including a substantially planar first top surface, a second section including a substantially planar second top surface, and a sidewall extending between the first and second top surfaces. The second top surface of the substrate is closer to a bottom surface of the substrate than is the first top surface. A charge storage pattern extends on the first and second top surfaces of the substrate and along the sidewall therebetween. A source region in the first section of the substrate extends from the first top surface into the second section of the substrate and has a stepped portion defined by the sidewall and the second top surface. Related fabrication methods and methods of operation are also discussed.

Abstract: Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Abstract: Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.

Abstract: The present invention provides a flash memory device having a high degree of integration and high performance. The flash memory device has a double/triple gate structure where a channel is formed in a wall-shaped body. The flash memory device has no source/drain regions. In addition, although the flash memory device has the source/drain regions, the source/drain region are formed not to be overlapped with a control electrode. Accordingly, an inversion layer is induced by a fringing field generated from the control electrode, so that cell devices can be electrically connected to each other. The flash memory device includes a charge storage node for storing charges formed under the control electrode, so that miniaturization characteristics of cell device can be improved. According to the present invention, there is proposed a new device capable of improving the miniaturization characteristics of a MOS-based flash memory device and increasing memory capacity.

Abstract: A memory cell of a nonvolatile semiconductor memory device according to an embodiment of the invention has a MONOS structure. The charge storage layer of the memory cell includes insulating material layers. The relationship between the conduction band edge energy and valance band edge energy of the insulating material layers either increases gradually or decreases gradually from the tunnel insulating film toward the block insulating film. Furthermore, when the relative permittivity of the block insulating film is expresses as ?r, an energy barrier between the charge storage layer and the block insulating film is equal to or larger than 4.5 ?r?2/3 (eV) and is equal to or smaller than 3.8 (eV).

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.

Abstract: Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.