With Additional, Non-memory Control Electrode Or Channel Portion (e.g., Accessing Field Effect Transistor Structure) Patents (Class 257/326)
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Patent number: 8643083Abstract: Devices and systems for insulating integrated circuits from ultraviolet (“UV”) light are described. The device includes a conductive feature, a first and second UV blocking layer, a first and second insulating laver, and a conductive structure. The first insulating layer overlays the first UV blocking layer. A via opening extends through the first insulating layer and the first UV blocking layer. The second UV blocking layer overlays the first insulating laver. The second insulating layer overlays the second UV blocking layer. An interconnect trench is defined in the second insulating layer and second UV blocking layer. The conductive structure is electrically connected to the conductive feature and extends into the via opening and along the interconnect trench.Type: GrantFiled: May 7, 2012Date of Patent: February 4, 2014Assignee: Spansion LLCInventors: Bryon K. Hance, Brian D. White, William Brennan, Joseph W. Wiseman, Allen Evans
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Patent number: 8637918Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.Type: GrantFiled: November 10, 2011Date of Patent: January 28, 2014Assignee: Spansion LLCInventors: Shenqing Fang, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong
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Publication number: 20140008716Abstract: When the width of an isolation region is reduced through the scaling of a memory cell to reduce the distance between the memory cell and an adjacent memory cell, the electrons or holes injected into the charge storage film of the memory cell are diffused into the portion of the charge storage film located over the isolation region to interfere with each other and possibly impair the reliability of the memory cell. In a semiconductor device, the charge storage film of the memory cell extends to the isolation region located between the adjacent memory cells. The effective length of the charge storage film in the isolation region is larger than the width of the isolation region. Here, the effective length indicates the length of the region of the charge storage film which is located over the isolation region and in which charges are not stored.Type: ApplicationFiled: June 29, 2013Publication date: January 9, 2014Inventors: Tsuyoshi Arigane, Digh Hisamoto, Yutaka Okuyama, Takashi Hashimoto, Daisuke Okada
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Publication number: 20130341703Abstract: According to one embodiment, the electrode films are provided on the substrate. The first insulating films are provided between the electrode films. The second insulating film is provided on an uppermost electrode film of the electrode films. The select gate is provided on the second insulating film. The channel body extends in a stacking direction in a stacked body. The memory film is provided between the channel body and the electrode films and includes a charge storage film. The memory film includes a block film, the charge storage film, and a tunnel film. The second insulating film includes at least the block film of the memory film.Type: ApplicationFiled: June 18, 2013Publication date: December 26, 2013Inventors: Hiroshi SHINOHARA, Toru Matsuda
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Patent number: 8614477Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.Type: GrantFiled: February 2, 2012Date of Patent: December 24, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Izumida, Nobutoshi Aoki
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Publication number: 20130334594Abstract: Some embodiments include a memory device and a method of forming the memory device. One such memory device includes a string of stacked memory cells. Each of the memory cells in the string includes a charge storage structure and a recessed control gate. The recessed control gate has a substantially smooth surface separated from the charge storage structure by dielectric material. One such method includes etching heavily boron doped polysilicon selective to oxide to form a recessed control gate having a surface with nubs. A smoothing solution is applied to the surface of the recessed control gate to smoothen the nubs. Additional apparatuses and methods are described.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Inventors: Jerome A. Imonigie, Patrick M. Flynn, Sandra L. Tagg, Prashant Raghu
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Patent number: 8610200Abstract: A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.Type: GrantFiled: April 26, 2011Date of Patent: December 17, 2013Assignee: Macronix International Co., Ltd.Inventor: Chien Hung Liu
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Publication number: 20130320426Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.Type: ApplicationFiled: August 8, 2013Publication date: December 5, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Kenichiro Toratani, Masayuki Tanaka, Kazuhiro Matsuo
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Patent number: 8598648Abstract: A semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide-gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long time. Transistors each including an oxide semiconductor in memory cells of the semiconductor device are connected in series; thus, a source electrode of the transistor including an oxide semiconductor in the memory cell and a drain electrode of the transistor including an oxide semiconductor in the adjacent memory cell can be connected to each other. Therefore, the area occupied by the memory cells can be reduced.Type: GrantFiled: March 10, 2011Date of Patent: December 3, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Satohiro Okamoto, Shuhei Nagatsuka
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Publication number: 20130313630Abstract: Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.Type: ApplicationFiled: July 31, 2013Publication date: November 28, 2013Applicant: Renesas Electronics CorporationInventor: Shoji SHUKURI
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Patent number: 8592890Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.Type: GrantFiled: January 11, 2011Date of Patent: November 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Nobutaka Watanabe, Kazuyuki Higashi, Gaku Sudo
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Publication number: 20130307054Abstract: One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.Type: ApplicationFiled: September 7, 2012Publication date: November 21, 2013Inventors: Shinichi YASUDA, Kosuke Tatsumura, Mari Matsumoto, Koichiro Zaitsu, Masato Oda, Atsuhiro Kinoshita, Daisuke Hagishima, Yoshifumi Nishi, Takahiro Kurita, Shinobu Fujita
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Publication number: 20130299894Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.Type: ApplicationFiled: July 12, 2013Publication date: November 14, 2013Inventors: Kiwamu Sakuma, Atsuhiro Kinoshita
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Patent number: 8581326Abstract: A nonvolatile semiconductor memory device including first laminated bodies each having a plurality of first gate electrodes of first memory cells, second laminated bodies each having a plurality of second gate electrodes of second memory cells, gate insulating film portions located on side surfaces of the first and second laminated bodies, first semiconductor layers that are each located between the first and second laminated bodies, first select transistors connected to an uppermost one of the first memory cells, second select transistors connected to an uppermost one of the second memory cells, isolation insulating films to separate the first and second select transistors into portions on the first and second laminated body sides, and a substrate potential applying electrode located to penetrate the isolation insulating films from a front surface side to a back surface side and connected to the first semiconductor layers.Type: GrantFiled: March 19, 2010Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Shigeto Oota, Yoshimasa Mikajiri, Ryouhei Kirisawa
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Patent number: 8581332Abstract: The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.Type: GrantFiled: August 11, 2011Date of Patent: November 12, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tamae Takano, Tetsuya Kakehata, Shunpei Yamazaki
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Patent number: 8581321Abstract: A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.Type: GrantFiled: October 26, 2011Date of Patent: November 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Byoungkeun Son, Changhyun Lee, Jaegoo Lee, Kwang Soo Seol, Byungkwan You
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Patent number: 8575684Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.Type: GrantFiled: February 2, 2012Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Izumida, Nobutoshi Aoki
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Patent number: 8576634Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.Type: GrantFiled: April 20, 2010Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventors: Fumitoshi Ito, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
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Patent number: 8575675Abstract: A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively.Type: GrantFiled: December 21, 2011Date of Patent: November 5, 2013Assignee: Hynix Semiconductor Inc.Inventors: Sun-Mi Park, Byung-Soo Park, Sang-Hyun Oh
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Patent number: 8569826Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a select gate electrode, a semiconductor pillar, a memory layer, and a select gate insulating film. The stacked structure includes a plurality of electrode films stacked in a first direction and an interelectrode insulating film provided between the electrode films. The select gate electrode is stacked with the stacked structure along the first direction and includes a plurality of select gate conductive films stacked in the first direction and an inter-select gate conductive film insulating film provided between the select gate conductive films. The semiconductor pillar pierces the stacked structure and the select gate electrode in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The select gate insulating film is provided between the select gate conductive films and the semiconductor pillar.Type: GrantFiled: September 16, 2010Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Yoshiaki Fukuzumi
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Patent number: 8569829Abstract: A nonvolatile semiconductor memory device according to an embodiment includes memory strings which have a plurality of transistors including gate electrode films formed over sides of columnar semiconductor films on gate dielectric films in a height direction of the semiconductor films, and which are arranged in a matrix shape substantially perpendicularly above a substrate. The gate electrode films of the transistors at same height of the memory strings arranged in a first direction are connected to one another. A distance between the semiconductor films at least in a forming position of the transistor at an uppermost layer of the memory strings adjacent to each other in the first direction is smaller than double of thickness of the gate dielectric films.Type: GrantFiled: May 20, 2010Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Masahiro Kiyotoshi
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Patent number: 8569828Abstract: A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.Type: GrantFiled: July 9, 2012Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Toshitake Yaegashi
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Patent number: 8569822Abstract: A memory structure having a memory cell including a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer is provided. The first dielectric layer is on the substrate. The gate includes a base portion on the first dielectric layer and a protruding portion disposed on the base portion and partially exposing the base portion. The semiconductor layer is conformally disposed on the gate, and includes a top portion over the protruding portion, a bottom portion over the base portion exposed by the protruding portion and a side portion located at a sidewall of the protruding portion and connecting the top and bottom portions. The first and second doped regions are respectively in the top and bottom portions. The side portion serves as a channel region. The charge storage layer is between the gate and the semiconductor layer.Type: GrantFiled: November 2, 2011Date of Patent: October 29, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Shih-Guei Yan
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Patent number: 8569827Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region.Type: GrantFiled: August 29, 2011Date of Patent: October 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Changhyun Lee, Byoungkeun Son, Hyejin Cho
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Patent number: 8569133Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.Type: GrantFiled: February 6, 2012Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
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Patent number: 8564045Abstract: Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.Type: GrantFiled: July 12, 2012Date of Patent: October 22, 2013Assignee: Micron Technology, Inc.Inventor: Zengtao Liu
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Publication number: 20130270627Abstract: A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni
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Patent number: 8557661Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.Type: GrantFiled: December 8, 2011Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Han-Geun Yu, Gyung-Jin Min, Seong-Soo Lee, Suk-Ho Joo, Yoo-Chul Kong, Dae-Hyun Jang
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Publication number: 20130264633Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.Type: ApplicationFiled: April 9, 2012Publication date: October 10, 2013Inventors: MARK D. HALL, MEHUL D. SHROFF
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Publication number: 20130264634Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.Type: ApplicationFiled: May 31, 2013Publication date: October 10, 2013Applicant: FREESCALESE MICONDUCTOR, INC.Inventors: Mark D. HALL, Mehul D. SHROFF
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Patent number: 8552490Abstract: A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the inner side wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate.Type: GrantFiled: June 18, 2010Date of Patent: October 8, 2013Assignee: United Microelectronics Corp.Inventors: Chih-Jen Huang, Chien-Hung Chen
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Patent number: 8546872Abstract: According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.Type: GrantFiled: March 25, 2011Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Sakuma, Atsuhiro Kinoshita
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Patent number: 8546909Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.Type: GrantFiled: September 16, 2011Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiko Noda, Hiroyuki Kutsukake, Mitsuhiro Noguchi
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Publication number: 20130248977Abstract: A non-volatile semiconductor storage device according to one embodiment of the present application has a memory cell array that includes at least one memory string, a first select transistor, and a second select transistor on a substrate in a lattice form. The first select transistor is electrically connected to a first end of the memory string. The second select transistor is electrically connected to a second end of the memory string. The memory string includes a columnar portion. Multiple memory cells are formed in the columnar portion by multiple conductive layers, multiple insulating layers, a first insulating layer, a charge accumulation layer, a second insulating layer, and a memory channel layer, and are serially connected. The memory channel layer comprises silicon germanium doped with phosphorus.Type: ApplicationFiled: March 8, 2013Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinji MORI, Jun FUJIKI, Kiyotaka MIYANO
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Publication number: 20130248978Abstract: According to an embodiment, a semiconductor device includes a plurality of first semiconductor regions that extend in a first direction and are arranged in a direction intersecting the first direction, and each element separation region that is provided between the plurality of first semiconductor regions. The element separation region includes a first element separation portion that is formed to a first depth from an upper surface of the first semiconductor region and a second element separation portion that is formed from the first depth to a second depth more than the first depth and electrically insulates between adjacent elements.Type: ApplicationFiled: March 15, 2013Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi SAKAGUCHI, Fumitaka Arai
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Patent number: 8541831Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: GrantFiled: December 3, 2009Date of Patent: September 24, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Patent number: 8541829Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.Type: GrantFiled: September 19, 2011Date of Patent: September 24, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kikuko Sugimae, Masayuki Ichige, Fumitaka Arai, Yasuhiko Matsunaga, Atsuhiro Sato
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Publication number: 20130240978Abstract: According to one embodiment, a nonvolatile semiconductor memory device has a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control electrode formed on the second insulating film. In the nonvolatile semiconductor memory device, the second insulating film has a laminated structure that has a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film, a first atom is provided at an interface between the first silicon oxide film and the first silicon nitride film, and/or at an interface between the second silicon oxide film and the first silicon nitride film, and the first atom is selected from the group consisting of aluminum, boron, and alkaline earth metals.Type: ApplicationFiled: August 31, 2012Publication date: September 19, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Masayuki TANAKA, Kazuhiro Matsuo
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Publication number: 20130234236Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.Type: ApplicationFiled: March 17, 2013Publication date: September 12, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Itaru YANAGI, Toshiyuki MINE, Hirotaka HAMAMURA, Digh HISAMOTO, Yasuhiro SHIMAMOTO
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Patent number: 8530956Abstract: A non-volatile memory device including a memory string including a plurality of memory cells coupled in series. The non-volatile memory device includes the memory string including a first semiconductor layer and a second conductive layer with a memory gate insulation layer therebetween, a first selection transistor comprising a second semiconductor layer coupled with one end of the first semiconductor layer, a second selection transistor comprising a third semiconductor layer coupled with the other end of the first semiconductor layer, and a fourth semiconductor layer contacting the first semiconductor layer in a region where the second conductive layer is not disposed.Type: GrantFiled: October 20, 2011Date of Patent: September 10, 2013Assignee: Hynix Semiconductor Inc.Inventor: Sang-Bum Lee
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Patent number: 8530958Abstract: A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.Type: GrantFiled: March 5, 2010Date of Patent: September 10, 2013Assignee: Renesas Electronics CorporationInventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Kentaro Saito, Toshikazu Matsui, Takashi Hashimoto, Kosuke Okuyama
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Patent number: 8525252Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.Type: GrantFiled: September 15, 2011Date of Patent: September 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenichiro Toratani, Masayuki Tanaka, Kazuhiro Matsuo
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Patent number: 8519472Abstract: A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.Type: GrantFiled: July 7, 2010Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jaehun Jeong, Ju-Young Lim, Hansoo Kim, Jaehoon Jang, Sunil Shim, Jae-Joo Shim
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Patent number: 8514620Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.Type: GrantFiled: November 29, 2010Date of Patent: August 20, 2013Assignee: Micron Technology, Inc.Inventor: Akira Goda
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Patent number: 8507976Abstract: A nonvolatile memory device includes a gate structure in which a plurality of interlayer dielectric layers and a plurality of gate electrodes are alternately stacked; a pass gate electrode lying under the gate structure; a sub channel hole defined in the pass gate electrode; a pair of main channel holes defined through the gate structure and communicating with the sub channel hole; a channel layer formed on inner walls of the pair of main channel holes and the sub channel hole; and a metallic substance layer contacting the channel layer in the sub channel hole.Type: GrantFiled: September 6, 2012Date of Patent: August 13, 2013Assignee: SK Hynix Inc.Inventor: Han-Soo Joo
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Patent number: 8507974Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; an insulator layer disposed over the semiconductor substrate; a fin structure disposed over the insulator layer, the fin structure having a source region, a drain region, and a channel region disposed between the source region and the drain region; a gate structure disposed adjacent to the channel region of the fin structure; and a doped region disposed in the semiconductor substrate below the channel region of the fin structure. The gate structure includes a first gate dielectric layer disposed adjacent to the fin structure, a second gate dielectric layer, a charge storing layer disposed between the first gate dielectric layer and the second gate dielectric layer, and a gate electrode layer disposed adjacent to the second gate dielectric layer.Type: GrantFiled: May 25, 2011Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Po-Wei Liu
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Patent number: 8507969Abstract: A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.Type: GrantFiled: May 7, 2012Date of Patent: August 13, 2013Assignee: Spansion LLCInventors: Mark S. Chang, Hao Fang, King Wai Kelwin Ko
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Patent number: 8507975Abstract: A semiconductor device having plural memory cell regions featuring nonvolatile memory cells, each nonvolatile memory cell including a first insulating film formed over a semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and arranged adjacent with the control gate electrode through the second gate insulating film, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, wherein each of the nonvolatile memory cells of a first memory cell region and each of the nonvolatile memory cells of a second memory cell region are formed adjacent to one another such that a drain region is shared between them.Type: GrantFiled: June 25, 2012Date of Patent: August 13, 2013Assignee: Renesas Electronics CorporationInventor: Shoji Shukuri
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Patent number: 8497547Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.Type: GrantFiled: August 21, 2012Date of Patent: July 30, 2013Assignee: Renesas Electronics CorporationInventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Takashi Hashimoto
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Patent number: 8488378Abstract: A nonvolatile semiconductor memory device according to one aspect includes a semiconductor substrate, a memory string, a plurality of first conductive layers, a second conductive layer, and a third conductive layer. The memory string has a plurality of memory cells, a dummy transistor and a back gate transistor connected in series in a direction perpendicular to the semiconductor substrate. The plurality of first conductive layers are electrically connected to gates of the memory cells. The second conductive layer is electrically connected to a gate of the dummy transistor. The third conductive layer is electrically connected to a gate of the back gate transistor. The second conductive layer is short-circuited with the third conductive layer.Type: GrantFiled: November 22, 2011Date of Patent: July 16, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Takashi Maeda