With Additional, Non-memory Control Electrode Or Channel Portion (e.g., Accessing Field Effect Transistor Structure) Patents (Class 257/326)
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Patent number: 8476708Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion. The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.Type: GrantFiled: January 10, 2012Date of Patent: July 2, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Hideaki Aochi, Masaru Kito, Kiyotaka Miyano, Shinji Mori, Ichiro Mizushima
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Patent number: 8476690Abstract: A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.Type: GrantFiled: September 1, 2011Date of Patent: July 2, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Hagishima, Atsuhiro Kinoshita
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Patent number: 8471326Abstract: According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.Type: GrantFiled: March 16, 2011Date of Patent: June 25, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Koji Nakahara, Kazuhiro Matsuo, Masayuki Tanaka
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Patent number: 8471324Abstract: A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.Type: GrantFiled: September 15, 2009Date of Patent: June 25, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Tin-Wei Wu, Cheng-Ming Yih, Chih-Hsiang Yang
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Patent number: 8471328Abstract: A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening.Type: GrantFiled: July 26, 2010Date of Patent: June 25, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Hung Chen, Tzu-Ping Chen, Yu-Jen Chang
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Patent number: 8471295Abstract: A flash memory cell string and a method of fabricating the same are provided. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially laminated on the semiconductor substrate. In each cell device, a source/drain region is not formed. The switching device does not include a source or drain region in a side connected to the cell devices. The switching device includes a source or drain region in the other side that is not connected to the cell devices. The source or drain region does or does not overlap the control electrode. Accordingly, it is possible to improve a miniaturization property and performance of NAND flash memory cell devices.Type: GrantFiled: December 4, 2007Date of Patent: June 25, 2013Assignee: SNU R&DB FoundationInventor: Jong-Ho Lee
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Patent number: 8466022Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a tunnel insulating film, a first electrode, an interelectrode insulating film and a second electrode. The tunnel insulating film is provided on the semiconductor substrate. The first electrode is provided on the tunnel insulating film. The interelectrode insulating film is provided on the first electrode. The second electrode is provided on the interelectrode insulating film. The interelectrode insulating film includes a stacked insulating layer, a charge storage layer and a block insulating layer. The charge storage layer is provided on the stacked insulating layer. The block insulating layer is provided on the charge storage layer. The stacked insulating layer includes a first insulating layer, a quantum effect layer and a second insulating layer. The quantum effect layer is provided on the first insulating layer. The second insulating layer is provided on the quantum effect layer.Type: GrantFiled: March 21, 2011Date of Patent: June 18, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Masayuki Tanaka
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Patent number: 8466509Abstract: The present invention provides a method for manufacturing a semiconductor device including the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating gate, etching a tunnel insulating film in a partial region through a window of a resist pattern; forming a metal silicide layer on the first impurity diffusion region in the partial region, forming an interlayer insulating film covering the flash memory cell, and forming, in a first hole of the interlayer insulating film, a conductive plug connected to the metal silicide layer.Type: GrantFiled: January 14, 2008Date of Patent: June 18, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Tetsuya Yamada
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Patent number: 8461643Abstract: A flash memory cell stack includes a semiconductor substrate; a control electrode formed in a vertical pillar shape on a surface of the semiconductor substrate; an insulating film formed between the control electrode and the semiconductor substrate; a gate stack formed on a side surface of the control electrode; a plurality of first insulating films formed as layers on a side surface of the gate stack; a plurality of second doping semiconductor areas formed as layers on a side surface of the gate stack; and a first doping semiconductor area formed on a portion of side surfaces of the first insulating films and the second doping semiconductor areas and formed on side surfaces facing each other in a first direction. The first insulating films and the second doping semiconductor areas are alternately provided on the side surface of the gate stack.Type: GrantFiled: September 24, 2009Date of Patent: June 11, 2013Assignee: SNU R & DB FoundationInventor: Jong-Ho Lee
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Patent number: 8455344Abstract: A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.Type: GrantFiled: September 21, 2011Date of Patent: June 4, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-Kang Sung, Choong-Ho Lee, Dong-Uk Choi, Hee-Soo Kang
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Patent number: 8455941Abstract: A nonvolatile semiconductor memory device includes a stacked body including electrode films stacked in a first direction; a conductive pillar piercing the stacked body in the first direction; an inner insulating film, a semiconductor pillar, an intermediate insulating film, a memory layer, and an outer insulating film provided between the conductive pillar and the electrode films. The inner insulating film is provided around a side face of the conductive pillar. The semiconductor pillar is provided around a side face of the inner insulating film. The intermediate insulating film is provided around a side face of the semiconductor pillar. The memory layer is provided around a side face of the intermediate insulating film. The outer insulating film is provided around a side face of the memory layer.Type: GrantFiled: December 29, 2010Date of Patent: June 4, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takamitsu Ishihara, Hideaki Aochi
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Patent number: 8450790Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.Type: GrantFiled: May 25, 2010Date of Patent: May 28, 2013Assignee: Renesas Electronics CorporationInventor: Yoshiyuki Kawashima
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Publication number: 20130119458Abstract: The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a a substrate, an active area, a first gate structure, a second gate structure and at least one third gate structure. The first gate structure covers a first partial region of the active area and is formed by a silicon-rich nitride material. The second gate structure covers a second partial region of the active area. The third gate structure covers a third partial region between a first opening and the first gate structure. The active area has the first opening, the first opening disposed on a first side of the first gate structure and the first side is not neighbor to the second gate structure. The NOR flash memory cell further comprises a first conducting structure for covering the first opening to form a bit line signal receiving terminal.Type: ApplicationFiled: December 18, 2012Publication date: May 16, 2013Applicant: EMEMORY TECHNOLOGY INC.Inventor: eMemory Technology Inc.
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Patent number: 8441059Abstract: A semiconductor device includes a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are provided on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.Type: GrantFiled: May 26, 2009Date of Patent: May 14, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Sung Sim, Jung-Dal Choi
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Patent number: 8436415Abstract: A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.Type: GrantFiled: March 15, 2010Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 8435855Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure.Type: GrantFiled: January 29, 2010Date of Patent: May 7, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-Uk Kim, Yong-Chul Oh
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Patent number: 8436411Abstract: A non-volatile memory including a substrate, two first conductive layers, a second conductive layer, a first dielectric layer, a second dielectric layer and two heavily doped regions is provided. The substrate has at least two isolation structures therein and an active region between the isolation structures. The first conductive layers are respectively disposed on the isolation structures. The second conductive layer is disposed on the substrate and covering a portion of the active region and a portion of each first conductive layer. The first dielectric layer is disposed between each first conductive layer and the second conductive layer. The second dielectric layer is disposed between the second conductive layer in the active region and the substrate. The heavily doped regions are disposed in the substrate beside the second conductive layer in the active region.Type: GrantFiled: January 6, 2009Date of Patent: May 7, 2013Assignee: United Microelectronics Corp.Inventors: Sung-Bin Lin, Yuan-Hsiang Chang, Yu-Huang Yeh, Che-Lieh Lin
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Patent number: 8431471Abstract: A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region.Type: GrantFiled: November 22, 2010Date of Patent: April 30, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Jane A. Yater, Sung-Taeg Kang, Mehul D. Shroff
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Publication number: 20130092999Abstract: A nonvolatile storage device includes a tunnel insulating film disposed on a surface of a semiconductor substrate and a charge trap layer disposed in contact with an upper surface of the tunnel insulating film. The charge trap layer includes a second charge trap film disposed in contact with the upper surface of the tunnel insulating film and a first charge trap film disposed in contact with an upper surface of the second charge trap film.Type: ApplicationFiled: September 12, 2012Publication date: April 18, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Motoki FUJII
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Patent number: 8406047Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.Type: GrantFiled: November 29, 2010Date of Patent: March 26, 2013Assignee: Micron Technology, Inc.Inventor: Akira Goda
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Patent number: 8405142Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.Type: GrantFiled: March 9, 2011Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Kazuyuki Higashi, Yoshiaki Fukuzumi
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Patent number: 8405143Abstract: A semiconductor device including a substrate, a gate structure, a spacer and source/drain regions is provided. The gate structure is on the substrate, wherein the gate structure includes, from bottom to top, a high-k layer, a work function metal layer, a wetting layer and a metal layer. The spacer is on a sidewall of the gate structure. The source/drain regions are in the substrate beside the gate structure.Type: GrantFiled: February 22, 2011Date of Patent: March 26, 2013Assignee: United Microelectronics Corp.Inventors: Chun-Hsien Lin, Chao-Ching Hsieh
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Publication number: 20130069142Abstract: A semiconductor device includes an element isolation region having an element isolation insulating film therein; an active region delineated by the element isolation region; agate insulating film formed in the active region; a charge storage layer above the gate insulating film; and an interelectrode insulating film. The interelectrode insulating film is formed in a first region above an upper surface of the element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a stack of a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a second silicon nitride film. A control electrode layer is formed above the interelectrode insulating film. The second silicon oxide film is thinner in the first region than in the third region.Type: ApplicationFiled: March 19, 2012Publication date: March 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiro MATSUO, Masayuki TANAKA, Hirofumi IIKAWA
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Patent number: 8399919Abstract: A unit block circuit of a semiconductor device includes a first well, a first pickup unit configured to form a closed loop over the first well, a first transistor including a first gate and a first active region, and formed within the first pickup unit, and a first reservoir capacitor formed in a spare within the first pickup unit and arranged in a major-axis direction of the first gate of the first transistor, wherein the first reservoir capacitor comprises a second active region and a second gate, the second gate being formed over the second active region.Type: GrantFiled: July 8, 2010Date of Patent: March 19, 2013Assignee: Hynix Semiconductor Inc.Inventor: Jong-Woo Kim
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Publication number: 20130062686Abstract: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.Type: ApplicationFiled: October 31, 2012Publication date: March 14, 2013Inventors: Tatsuo SHIMIZU, Koichi MURAOKA
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Patent number: 8378410Abstract: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.Type: GrantFiled: June 6, 2012Date of Patent: February 19, 2013Assignee: Macronix International Co., Ltd.Inventors: Sheng-Chih Lai, Hang-Ting Lue
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Patent number: 8373218Abstract: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.Type: GrantFiled: October 28, 2010Date of Patent: February 12, 2013Assignee: Macronix International Co., Ltd.Inventor: Chi-Pin Lu
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Patent number: 8373221Abstract: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.Type: GrantFiled: December 26, 2007Date of Patent: February 12, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Robert F. Steimle, Ramachandran Muralidhar, Bruce E. White
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Patent number: 8372720Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: December 9, 2008Date of Patent: February 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 8362456Abstract: To use a resistance change element having an MIM structure, which is obtained by stacking a metal, a metal oxide, and a metal, as a switching element, it is necessary to achieve OFF resistance higher than that required in a memory element by a factor of at least 1000. On the other hand, when a resistance change element is used as a memory element and when the difference between the ON resistance and the OFF resistance is a large value, high performance, for example, a short readout time, can be achieved. The present invention therefore provides a resistance change element capable of maintaining low ON resistance and achieving high OFF resistance. High OFF resistance can be achieved while low ON resistance is maintained by adding a second metal that is not contained in a metal oxide, which is a resistance change material, the second metal being capable of charge-compensating for metal deficiency or oxygen deficiency.Type: GrantFiled: March 21, 2008Date of Patent: January 29, 2013Assignee: NEC CorporationInventors: Kimihiko Ito, Hiroshi Sunamura, Yuko Yabe
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Patent number: 8363481Abstract: A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.Type: GrantFiled: January 31, 2008Date of Patent: January 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Hiroyasu Tanaka, Masaru Kito, Ryota Katsumata, Hideaki Aochi, Mitsuru Sato
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Publication number: 20130010535Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA
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Patent number: 8350602Abstract: A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.Type: GrantFiled: April 18, 2011Date of Patent: January 8, 2013Assignee: Seoul National University Research & Development Business FoundationInventors: Seunghun Hong, Sung Myung, Kwang Heo
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Patent number: 8350344Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.Type: GrantFiled: March 10, 2011Date of Patent: January 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Min Son, Woon-Kyung Lee
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Patent number: 8350315Abstract: Memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.Type: GrantFiled: August 18, 2009Date of Patent: January 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Kwang-soo Seol
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Patent number: 8344385Abstract: In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns.Type: GrantFiled: August 31, 2010Date of Patent: January 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hoo Kim, Hyo-San Lee, Sang-Won Bae, Bo-Un Yoon, Kun-Tack Lee
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Patent number: 8344446Abstract: Provided is an excellent nonvolatile storage device having advantageous in miniaturization and less variation in initial threshold value, and exhibiting a high writing efficiency, without an erasing failure and a retention failure. The nonvolatile storage device is characterized by including a film stack extending from between a semiconductor substrate and a gate electrode onto at least a surface of the gate electrode lying on a first impurity diffusion region side, the film stack including a charge accumulating layer and a tunnel insulating film sequentially from a gate electrode side.Type: GrantFiled: December 13, 2007Date of Patent: January 1, 2013Assignee: NEC CorporationInventor: Yukihide Tsuji
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Publication number: 20120326225Abstract: A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.Type: ApplicationFiled: June 21, 2012Publication date: December 27, 2012Inventors: SUNG-IL CHANG, Young-Woo Park
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Patent number: 8338874Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: GrantFiled: May 11, 2012Date of Patent: December 25, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Patent number: 8338882Abstract: According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.Type: GrantFiled: July 22, 2010Date of Patent: December 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi
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Patent number: 8334562Abstract: A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.Type: GrantFiled: August 26, 2010Date of Patent: December 18, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-dal Choi
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Patent number: 8334561Abstract: A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.Type: GrantFiled: February 22, 2010Date of Patent: December 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
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Patent number: 8330201Abstract: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.Type: GrantFiled: September 12, 2007Date of Patent: December 11, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Koichi Muraoka
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Patent number: 8325527Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.Type: GrantFiled: June 8, 2009Date of Patent: December 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Beom-jun Jin, Byung-seo Kim, Sung-Dong Kim
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Publication number: 20120299087Abstract: A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction.Type: ApplicationFiled: December 21, 2011Publication date: November 29, 2012Inventors: Han-Soo JOO, Yu-Jin PARK
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Patent number: 8318602Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.Type: GrantFiled: April 13, 2011Date of Patent: November 27, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Hirofumi Inoue
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Patent number: 8319265Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: October 16, 2009Date of Patent: November 27, 2012Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 8314455Abstract: A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.Type: GrantFiled: June 9, 2011Date of Patent: November 20, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Atsuhiro Sato, Takeshi Kamigaichi, Fumitaka Arai
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Patent number: 8314458Abstract: In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented.Type: GrantFiled: February 18, 2010Date of Patent: November 20, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Seiji Otake
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Patent number: 8314457Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.Type: GrantFiled: April 27, 2011Date of Patent: November 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Suk Kim, Sun-Il Shim, Chang-Seok Kang, Won-Cheol Jeong, Jung-Dal Choi, Jae-Kwan Park, Seung-Hyun Lim, Sun-Jung Kim