Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The method can includes forming a semiconductor layer containing an impurity and forming a pattern on the semiconductor layer. The method can include forming first insulating layers in a stripe shape from a surface of the semiconductor layer toward an inside and forming a first insulating film on the semiconductor layer and on the first insulating layers to form a stacked body including electrode layers on the first insulating film. The method can include forming a pair of holes in the stacked body and forming a space portion connected to a lower end of the holes. The method can include forming a memory film on a side wall of the holes. In addition, the method can include forming a channel body layer on a surface of the memory film.

Abstract: A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating film provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material.

Abstract: Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor pillar pierces the stacked body. The charge storage layer is provided between the electrode films and the semiconductor pillar. The tunneling layer is provided between the charge storage layer and the semiconductor pillar. The dividing trench is provided between the semiconductor pillars in one direction orthogonal to a stacking direction of the stacked body to divide the electrode films. The first heating unit is provided in an interior of the dividing trench.

Abstract: Nonvolatile memory has a modified channel region interface, such as a raised source and drain or a recessed channel region.

Abstract: Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.

Abstract: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.

Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.

Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.

Abstract: Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.

Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.

Abstract: A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.

Abstract: A semiconductor memory device includes a lower select transistor formed within a semiconductor substrate, memory cells stacked over the lower select transistors, and an upper select transistor formed over the memory cells.

Abstract: A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.

Abstract: A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, an electrode layer provided above the substrate, a first insulating layer provided on the electrode layer, a stacked body provided on the insulating layer, a memory film, a channel body layer, a channel body connecting portion and a second insulating layer. The stacked body has a plurality of conductive layers and a plurality of insulating film alternately stacked on each other. The memory film is provided on a sidewall of each of a pair of holes penetrating the stacked body in a direction of stacking the stacked body. The channel body layer is provided on an inner side of the memory film in each of the pair of the holes.

Abstract: First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode. The first channel includes a first-conductivity-type region and a second-conductivity-type region which is formed on at least a part of the first-conductivity-type region and whose conductivity type is opposite to the first conductivity type. The third channel includes the first-conductivity-type region and the second-conductivity-type region formed on the first-conductivity-type region. The number of data stored in the first memory cell is smaller than that of data stored in the second memory cell.

Abstract: According to one embodiment, a semiconductor device includes an active area that is formed on a semiconductor substrate, a trench that isolates the active area, a nitride film that is buried in the trench, an air gap that is formed above the nitride film along the trench, and a gate electrode that is formed on the active area to span the trench through the air gap.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Abstract: A semiconductor memory device includes conductive patterns vertically stacked on the substrate and having pad regions extended further at edge portions of the conductive patterns as the conductive patterns descend from an uppermost conductive pattern to a lowermost conductive pattern, a first contact plug disposed on a first pad region of the lowermost conductive pattern, a buffer conductive pattern disposed on a second pad region positioned above the first pad region, and a second contact plug formed on the buffer conductive pattern.

Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Abstract: A non-volatile memory includes a substrate, a gate dielectric layer, a gate conductive layer, a nitride layer, a spacer, a first oxide layer, and a second oxide layer. The gate conductive layer, substrate and gate dielectric layer cooperatively constitute a symmetrical opening thereamong. The nitride layer has an L-shape and formed with a vertical part extending along a sidewall of the gate conductive layer and a horizontal part extending into the opening, wherein the vertical part and the horizontal part are formed as an integral structure and a height of the vertical part is below a top surface of the gate conductive layer. The spacer is disposed on the substrate and the nitride layer. The first oxide layer is disposed among the gate conductive layer, the nitride layer and the gate dielectric layer. The second oxide layer is disposed among the gate dielectric layer, the nitride layer and the substrate.

Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.

Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that of the at least two conductive layers in the first and second blocks are disposed on the driver, and select gate lines in the first and second blocks are connected to the driver through the at least two conductive layers on the driver.

Abstract: In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.

Abstract: The memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.

Abstract: A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized.

Abstract: According to an embodiment, a nonvolatile memory device includes a memory cell string, a control gate, first and second insulating films. The memory cell string includes a semiconductor layer and a plurality of memory cells disposed on the semiconductor layer. The control gate is provided on each of the memory cells. The first insulating film covers each side surface of the memory cells, and a side surface of the control gate. The second insulating film covering an upper portion of the control gate is provided on each of two adjacent memory cells. A first air gap is disposed between the two adjacent memory cells and surround by the first insulating film and the second insulating film, and the semiconductor layer is exposed by the first gap, or thickness of an insulating film between the first gap and the semiconductor layer is thinner than the first insulating film.

Abstract: According to an embodiment, a non-volatile memory device includes a memory cell including a semiconductor layer, a charge storage layer provided on the semiconductor layer, and a first insulating film provided between the semiconductor layer and the charge storage layer. The device also includes a first conductive layer provided on the charge storage layer, a second conductive layer provided between the charge storage layer and the first conductive layer, a second insulating film provided between the charge storage layer and the second conductive layer, and a third insulating film provided between the first conductive layer and the second conductive layer.

Abstract: A first dielectric is formed over a semiconductor layer, a first gate layer over the first dielectric, a second dielectric over the first gate layer, and a third dielectric over the second dielectric. An etch is performed to form a first sidewall of the first gate layer. A second etch is performed to remove portions of the first dielectric between the semiconductor layer and the first gate layer to expose a bottom corner of the first gate layer and to remove portions of the second dielectric between the first gate layer and the third dielectric layer to expose a top corner of the first gate layer. An oxide is grown on the first sidewall and around the top and bottom corners to round the corners. The oxide is then removed. A charge storage layer and second gate layer is formed over the third dielectric layer and overlapping the first sidewall.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of insulative separating films, a channel body, and a memory film. The stacked body includes a plurality of electrode layers and a plurality of insulating layers. The plurality of insulative separating films separates the stacked body into a plurality. The channel body extends in the stacking direction between the plurality of insulative separating films. A width of the electrode layer of a lower layer side between the insulative separating film and the memory film is greater than a width of the electrode layer of an upper layer side between the insulative separating film and the memory film. An electrical resistivity of the electrode layer is higher for the electrode layer of the lower layer side having the greater width than for the electrode layer of the upper layer side having the lesser width.

Abstract: A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.

Abstract: A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.

Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure.

Abstract: The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.

Abstract: A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract: Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.

Abstract: A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.