Abstract: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.

Abstract: A field-effect transistor, having a source electrode, a drain electrode and a gate electrode, which has a connection between the gate electrode and the source electrode or between the gate electrode and the drain electrode or between the gate electrode and the substrate which carries a leakage current.

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80?, 80?), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44?, 84, 84?) and drift (50, 50?, 90, 90?) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50?, 90, 90?) at least into the underlying body region (44, 44? 84, 84?), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50?, 90, 90?).

Abstract: An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer.

Abstract: The present invention discloses AC/DC converters and methods of manufacturing the same. The method includes providing a substrate; forming an oxide layer on a top surface of the substrate; applying a photo-resist layer on the oxide layer to define a well region; performing an ion-implantation in the well region using a dopant; and driving in atoms of the dopant to a depth in the well region through a thermal treatment, wherein the driving in process provides a concentration profile of the dopant in the well region such that the semiconductor structure has a high breakdown voltage.

Abstract: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.

Abstract: The electronic device comprising a RF transistor (100) that is designed for a fundamental RF frequency and that is integrated with an electrostatic protection structure (250) with a further transistor (200). The transistors are suitably MOS transistors, with a gate, source and drain electrodes, and wherein the sources are coupled to a grounded substrate region. The drain region of the further transistor is coupled to the gate of the RF transistor (100), giving rise to a parasitic diode (300) between the drain region of the further transistor and the grounded substrate region under application of a certain input voltage. A filter (350) is present for filtering the fundamental RF frequency from the parasitic diode (300).

Abstract: A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity layer formed in at least a portion of the low-voltage device region and coupled to a second voltage less than the first voltage; and a well formed on the second buried impurity layer in the low-voltage device region and coupled to a third voltage less than the second voltage.

Abstract: A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall.

Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor.

Abstract: A method of manufacturing a semiconductor device is provided which comprises: forming a first gate insulating film and a second gate insulating film in an active region of a semiconductor substrate; introducing an impurity of a first conductivity type into a first site where a first body region is to be formed, the first site being disposed under the first gate insulating film in the active region; forming a gate electrode on each of the first gate insulating film and the second gate insulating film; and introducing an impurity of the first conductivity type into the first site and a second site where a second body region is to be formed, the second site being disposed under the second gate insulating film in the active region, to form the first body region and the second body region, respectively.

Abstract: An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first conductivity type below the buried layer. The device further includes a field oxide located between a drain and both a gate on a gate oxide and a source with a saddle shaped vertical doping gradient of the second conductivity type in the epitaxial layer above the buried well such that the dopant concentration in the epitaxial layer above the buried well and below a central portion of the field oxide is lower than the dopant concentration at the edges of the field oxide nearest the drain and nearest the gate.

Abstract: A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate electrodes, respectively. The fourth gate electrode is electrically connected to the third gate electrode. Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node. Each of the first, second, third, and fourth gate electrodes is defined to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature defined within any gate level feature layout channel associated with a gate electrode track adjacent thereto.

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers.

Abstract: In a semiconductor device of the present invention, a thin gate oxide film is formed on a P-type diffusion layer. On the gate oxide film, a gate electrode is formed. N-type diffusion layers are formed in the P-type diffusion layer, and the N-type diffusion layer is used as a drain region. The N-type diffusion layer is diffused in a ? shape at least below the gate electrode. With the structure described above, a diffusion region of the N-type diffusion layer expands and comes to be a low-concentration region in the vicinity of a surface of an epitaxial layer. Thus, it is possible to reduce an electric field from the gate electrode and an electric field between a source and a drain.

Abstract: A lateral trench DMOS device formed in a substrate of a first conductivity type includes a trench extending downward from a surface of the substrate, the trench lined with a dielectric layer and containing a gate electrode. The device includes a source region of a second conductivity type adjacent the surface of the substrate and a sidewall of the trench, a drain region of the second conductivity type adjacent the surface of the substrate and spaced apart from the source region, a body region of the first conductivity type adjacent the source region and the sidewall of the trench, a drift region of the second conductivity type adjacent the body region, the sidewall of the trench and the drain region; and a body contact region of the first conductivity type disposed in the body region and spaced apart from the source region.

Abstract: A power metal-oxide semiconductor (MOS) transistor device is provided. The power MOS transistor device includes a drain region disposed in a substrate, a gate structure layer disposed over the substrate, and enclosing a periphery of the drain region, and a source region formed in the substrate and distributed at an outer periphery of the gate structure layer. In addition, the MOS transistor device can, for example, form a transistor array.

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

Abstract: A reverse conducting insulated gate bipolar transistor (IGBT) includes a semiconductor substrate having a front side and a back side and a first conductivity region between the front and back sides. The first conductivity region includes a reduced lifetime zone, a first lifetime zone between the reduced lifetime zone and the front side, and an intermediate lifetime zone between the reduced lifetime zone and the back side. Charge carriers in the first lifetime zone have a first carrier lifetime, charge carriers in the reduced lifetime zone have a reduced carrier lifetime shorter than the first carrier lifetime, and charge carriers in the intermediate lifetime zone have an intermediate carrier lifetime shorter than the first carrier lifetime and longer than the reduced carrier lifetime.

Abstract: The present invention relates to a method of manufacturing a semiconductor device having a shared contact for connection between a source/drain region and a gate electrode. After formation of a gate electrode via a gate insulating film on a semiconductor substrate, a top surface of the substrate is covered with a cover film. After removal of the cover film from at least one of sidewall surface of the gate electrode and a part of the top surface of the substrate adjacent to the sidewall surface, a semiconductor layer is epitaxially grown on a top surface of an exposed substrate to electrically connect the substrate and the at least one sidewall surface of the gate electrode. Then, a source/drain region is formed in a top surface part of the substrate or the semiconductor layer using the gate electrode as a mask.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar transistor that exists in parallel with the DMOS transistor. The instant invention is a cascoded DMOS transistor in an integrated circuit incorporating an NMOS transistor on the DMOS source node to reverse bias the parasitic emitter-base junction during on-state operation, eliminating snapback. The NMOS transistor may be integrated with the DMOS transistor by connections in the interconnect system of the integrated circuit, or the NMOS transistor and DMOS transistor may be fabricated in a common p-type well and integrated in the IC substrate. Methods of fabricating an integrated circuit with the incentive cascoded DMOS transistor are also disclosed.

Abstract: A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases and long time reliability improves. Moreover, the lateral DMOS of the invention can be fabricated without increasing the manufacturing cost.

Abstract: An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode.

Abstract: A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low and higher operation transistor devices. The second diffusion region of the DDD is self-aligned to the spacer on the sidewalls of the gate and gate dielectric, so that the transistor size may be decreased.

Abstract: A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.

Abstract: In a body of semiconductor material, a field region separates a first active area and a second active area. A drain region is formed in the first active area; a body region is formed in the second active area and accommodates a source region. A body-contact region is formed inside the source region and extends from the surface as far as the body region. An insulating layer extends on top of the surface and accommodates a plurality of metal contacts, which extend as far as the drain region, the source region and the body-contact region. The body-contact region is self-aligned to a respective contact.

Abstract: A semiconductor device includes a semiconductor substrate which has first and second principal surface regions; an insulated gate structure which is formed in the first principal surface region; a back surface region semiconductor layer which is formed in the second principal surface region and has a thickness of at most 5 ?m; an outermost metal film; and a back surface electrode which is formed in the second principal surface region between the back surface region semiconductor layer and the outermost metal film and which is composed of a plurality of films which are laminated and include a stress relaxation film so that false judgment of chip quality based on leakage current measurements during manufacturing is reduced particularly when dust is present and skews leakage current measurements due to strain on the wafer and the piezoelectric effect produced.

Abstract: A semiconductor device includes field effect transistors, each having a semiconductor layer formed on a major surface of a semiconductor substrate, a base region formed in a surface layer portion of a semiconductor layer, a source region formed in a surface layer portion of the base region, a source electrode formed on the base region and the source region, a gate electrode formed on the semiconductor layer and the base region via a gate insulating film interposed therebetween, and a drain electrode formed on a back surface of the semiconductor substrate, and which are placed side by side. A columnar intermediate region is formed in its corresponding predetermined region of the surface layer portion of the semiconductor layer placed below each gate electrode. Connection regions are formed in the surface layer portion of the semiconductor layer to contact the intermediate region and the base regions.

Abstract: A semiconductor integrated circuit device (IC1) comprises a semiconductor chip (CHIP1), a first frame lead (FR1), and a second frame lead (FR2). The semiconductor chip (CHIP1) includes common-base transistors (P1, P2), pads (T11, T12) connected to the respective emitters of the common-base transistors (P1, P2), pads (T21, T22) connected to the respective collectors of the common-base transistors (P1, P2), and a means (DRV, ERR, E1) for generating a base signal. The pads (T11, T12) are connected through the respective bonding wires (W11, W12) to the first frame lead (FR1). The pads (T21, T22) are connected through the respective bonding wires (W21, W22) to the second frame lead (FR2). This structure can easily detect breaking of the bonding wires connected in parallel.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FET (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type.

Abstract: A silicon (Si)-on-insulator (SOI) high voltage transistor with a body ground is provided with an associated fabrication process. The method provides a SOI substrate with a buried oxide (BOX) layer and a Si top layer having a first thickness and a second thickness, greater than the first thickness. A body ground is formed in the second thickness of Si top layer overlying the BOX layer. A control channel is formed in the first thickness of the Si top layer. A control gate is formed overlying the control channel. An auxiliary channel is formed in the second thickness of Si top layer partially overlying the body ground and extending into the first thickness of the Si top layer. An auxiliary gate is formed overlying the auxiliary channel. A pn junction is formed in the second thickness of Si top layer between the auxiliary channel and the body ground.

Abstract: A semiconductor device is disclosed which has a shorter turn-on time. The semiconductor device includes an epitaxial layer, two base regions embedded in a surface portion of the epitaxial layer, source regions respectively embedded in the base regions, a drain region including at least a portion of the epitaxial layer excluding the base regions, and a gate electrode provided on the epitaxial layer with the intervention of an insulation film with ends thereof respectively opposed to surfaces of the two base regions. The drain region is arranged so that depletion layers respectively extending from boundaries between the drain region and the two base regions are connected to each other in an OFF state in a portion of the drain region located between the two base regions.

Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.

Abstract: A semiconductor device includes a substrate. The substrate includes a semiconductor material. An electrically isolated region is formed over the substrate. A metal-oxide-semiconductor field-effect transistor (MOSFET) is formed over the substrate within the electrically isolated region. The electrically isolated region includes a trench formed around the electrically isolated region. An insulative material such as silicon dioxide (SiO2) may be deposited into the trench. A diode is formed over the substrate within the electrically isolated region. In one embodiment, the diode is a Schottky diode. A metal layer may be formed over a surface of the substrate to form an anode of the diode. A first electrical connection is formed between a source of the MOSFET and an anode of the diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the diode.

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.

Abstract: A lateral DMOS device and a fabrication method therefor that may include forming a second conductive type well in a first conductive type semiconductor substrate and forming a Schottky contact in contact with the second conductive type well in a Schottky diode region, thereby preventing breakdown of the device due to high voltage.

Abstract: A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FET (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type.

Abstract: A non-insulated DC-DC converter hs a power MOS•FRT for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS•FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.

Abstract: A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.

Abstract: Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).

Abstract: A technique for suppressing lowering of withstand voltage and lowering of breakdown resistance and reducing a feedback capacitance of a power MISFET is provided. A lateral power MISFET that comprises a trench region whose insulating layer is formed shallower than an HV-Nwell layer is provided in the HV-Nwell layer (drift region) formed on a main surface of a semiconductor substrate in a direction from the main surface to the inside. The lateral power MISFET has an arrangement on a plane of the main surface including a source layer (source region) and a drain layer (drain region) arranged at opposite sides to each other across a gate electrode (first conducting layer), and a dummy gate electrode (second conducting layer) that is different from the gate electrode is arranged between the gate electrode and the drain layer.

Abstract: An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.

Abstract: A power actuator of the emitter-switched type is described, the power actuator comprising at least one high voltage bipolar transistor and a low voltage DMOS transistor connected in cascode configuration between a collector terminal of the bipolar transistor and a source terminal of the DMOS transistor and having respective control terminals. Advantageously, the power actuator further comprises at least a Zener diode, inserted between the source terminal of the DMOS transistor and the control transistor of the bipolar transistor.

Abstract: In a semiconductor device, source/drain layers have a low resistivity region and an extension region extending from the low resistivity region toward the channel region. The extension regions are lower in impurity concentration and shallower in depth than the low resistivity regions. The device also has a first impurity-doped layer formed in the channel region between the source/drain layers, a second impurity-doped layer formed under the first impurity-doped layer, and a third impurity-doped layer formed under the second impurity-doped layer. The first impurity-doped layer is equal or less in junction depth than the extension regions. The second impurity doped layer has impurity concentration and thickness to be fully depleted due to a built-in potential as created between the first and third impurity-doped layers.

Abstract: A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.

Abstract: An integrated LDMOS transistor comprises a semiconductor substrate (11), an LDMOS gate region (17), LDMOS source (14) and drain (15) regions, and a channel region (13) arranged beneath the LDMOS gate region, where the channel region interconnects the LDMOS source and drain regions. The LDMOS gate region comprises first (18a) and second (18b) gate insulation layer regions, a centrally located gate-dividing insulation region (19) provided between the first and second gate insulation layer regions, and first (20a) and second (20b) individual gate conducting layer regions, each being provided on top of a respective one of the first and second gate insulation layer regions, and each being an etched outside spacer region at the centrally located insulation layer region.