Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

Abstract: A snubber circuit connected to a rectifying circuit including a reference voltage node and a switch node, the snubber circuit comprises a snubber capacitor; and a P-type MOS transistor, wherein a positive electrode of the snubber capacitor is connected to the switch node, and a drain of the P-type MOS transistor is connected to a negative electrode of the snubber capacitor, and a source of the P-type MOS transistor is connected to the reference voltage node.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.

Abstract: A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.

Abstract: An integrated circuit includes a pull-up circuit, an electrostatic discharge (ESD) primary circuit, and a pull-down circuit. The pull-up circuit is coupled between a pad and a first voltage terminal. The ESD primary circuit includes a first terminal which is coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal. The pull-down circuit has a first terminal which is coupled to the pad, the ESD primary circuit and the pull-up circuit, and a second terminal coupled to the second voltage terminal. The pull-down circuit includes at least one first transistor of a first conductivity type having a first terminal coupled to the first terminal of the pull-down circuit. A breakdown voltage of the at least one first transistor is greater than a trigger voltage of the ESD primary circuit.

Abstract: A method includes forming a first-type deep well with a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first-type deep well to form a second-type doped region, in which a concentration of the first impurity in the first-type deep well is greater than a concentration of the second impurity in the second-type doped region and less than about ten times the concentration of the second impurity in the second-type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide laterally extending from a first side of the second-type doped region; forming a second-type well of the second conductivity type in the first-type deep well and on a second side of the second-type doped region opposite the first side of the second-type doped region.

Abstract: A semiconductor device includes a semiconductor substrate, a field oxide layer, a gate region and field plate integrated structure and a plurality of contact holes. A body region and a drift region are formed in the semiconductor substrate. An active region is formed in the body region, and a drain region is formed in the drift region. A field oxide layer is located on the drift region and the drift region surrounds a part of the field oxide layer. An integrated structure including a gate region and a field plate, the integrated structure extending from above the field oxide layer to above the body region. A depth of a contact hole closer to the source region penetrating into the field oxide layer is greater than a depth of a contact hole closer to the drain region penetrating into the field oxide layer.

Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

Abstract: A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.

Abstract: A FinFET includes a semiconductor fin, and a source region and a drain region in the same semiconductor fin. The drain region has a first fin height above a trench isolation; and the source region has a second fin height above the trench isolation. The first fin height is less than the second fin height. The FinFET may be used, for example, in a scaled laterally diffused metal-oxide semiconductor (LDMOS) application, and exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. A drain extension region may have the first fin height, and a channel region may have the second fin height. A method of making the FinFET is also disclosed.

Abstract: A RESURF isolation structure surrounds an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other. The RESURF isolation structure includes a high-voltage isolation region, a high-voltage N-ch MOS, and a high-voltage P-ch MOS. The high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a plurality of field plates (9,19a,19b,19c). An inner end of the field plate (19c) of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the field plate (19b) of the high-voltage N-ch MOS located closest to the low-side circuit region.

Abstract: A high voltage depletion mode MOS device with adjustable threshold voltage includes: a first conductive type well region; a second conductive type channel region, wherein when the channel region is not depleted, the MOS device is conductive, and when the channel region is depleted, the MOS device is non-conductive; a second conductive type connection region which contacts the channel region; a first conductive type gate, for controlling the conductive condition of the MOS device; a second conductive type lightly doped diffusion region formed under a spacer layer of the gate and contacting the channel region; a second type source region; and a second type drain region contacting the connection region but not contacting the gate; wherein the gate has a first conductive type doping or both a first and a second conductive type doping, and wherein a net doping concentration of the gate is determined by a threshold voltage target.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: Techniques are disclosed for monolithic co-integration of silicon (Si)-based transistor devices and III-N semiconductor-based transistor devices over a commonly shared semiconductor substrate. In accordance with some embodiments, the disclosed techniques may be used to provide a silicon-on-insulator (SOI) or other semiconductor-on-insulator structure including: (1) a Si (111) surface available for formation of III-N-based n-channel devices; and (2) a Si (100) surface available for formation of Si-based p-channel devices, n-channel devices, or both. Further processing may be performed, in accordance with some embodiments, to provide n-channel and p-channel devices over the Si (111) and Si (100) surfaces, as desired.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer over an inner wall and a bottom of the trench. The method includes forming a mask layer over the gate dielectric layer over the bottom. The method includes removing the gate dielectric layer over the inner wall. The method includes removing the mask layer. The method includes forming a gate electrode in the trench.

Abstract: Integrated circuits including an electrostatic discharge device and methods of forming the integrated circuits are provided herein. In an embodiment, an integrated circuit includes an n-type epitaxy layer, a segmented p-well, a p-type buried layer, and a collector region. The segmented p-well is formed in the n-type epitaxy layer. The segmented p-well defines and laterally surrounds a spacing region of the n-type epitaxy layer. The p-type buried layer is formed in the spacing region. The p-type buried layer laterally extends into the segmented p-well about the spacing region and impedes current flow between an underlying portion of the n-type epitaxy layer in relation to the p-type buried layer and an overlying portion of the n-type epitaxy layer in the spacing region. The collector region of the electrostatic discharge device is formed in the overlying portion of the n-type epitaxy layer in the spacing region.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.

Abstract: The present disclosure provides a semiconductor memory including a first capacitor, a second capacitor, and a transistor. The first capacitor includes a first conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the first conductive layer and separated from the n-type diffusion layers. The second capacitor includes a second conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the second conductive layer and separated from the n-type diffusion layers.

Abstract: According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base material, and further includes a first transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, and a second transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, in which the shallow N-well is formed in such a way as to surround the peripheral edge of the region of the shallow P-well.

Abstract: A display panel, which an also function as a touch input device, includes a substrate and at least one TFT on the substrate. Such a multi-function panel also includes a force sensor sensitive to pressure of touches on the panel. The force sensor includes a first conductive layer and a second conductive layer on the substrate.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.

Abstract: A manufacturing method of an epitaxial contact structure in a semiconductor memory device includes the following steps. A recess is formed in a semiconductor substrate by an etching process. An etching defect is formed in the recess by the etching process. An oxidation process is performed after the etching process. An oxide layer is formed in the recess by the oxidation process, and the etching defect is encompassed by the oxide layer. A cleaning process is performed after the oxidation process. The oxide layer and the etching defect encompassed by the oxide layer are removed by the cleaning process. An epitaxial growth process is performed to form an epitaxial contact structure in the recess after the cleaning process.

Abstract: A semiconductor device includes device isolation layer on a substrate to define an active region, a first gate electrode on the active region extending in a first direction parallel to a top surface of the substrate, a second gate electrode on the device isolation layer and spaced apart from the first gate electrode in the first direction, a gate spacer between the first gate electrode and the second gate electrode, and source/drain regions in the active region at opposite sides of the first gate electrode. The source/drain regions are spaced apart from each other in a second direction that is parallel to the top surface of the substrate and crossing the first direction, and, when viewed in a plan view, the first gate electrode is spaced apart from a boundary between the active region and the device isolation layer.

Abstract: A method is provided for forming a direct emission display. The method provides a transparent substrate with an array of wells formed in its top surface. A fluid stream is supplied to the substrate top surface comprising a plurality of top-contact light emitting diode (LED) disks. The wells are filled with the LED disks. A first array of electrically conductive lines is formed over the substrate top surface to connect with a first contact of each LED disk, and a second array of electrically conductive lines is formed over the substrate top surface to connect with a second contact of each LED disk. An insulator over the disk exposes an upper disk (e.g., p-doped) contact region. A via is formed through the disk, exposing a center contact region of a lower (e.g., n-doped) disk contact region. Also provided are a top-contact LED disk and direct emission display.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor substrate, and a current carrying region (e.g., a drain region of an LDMOS transistor) is disposed in the semiconductor substrate at the surface. The device further includes a drift region of a second, opposite conductivity type disposed in the semiconductor substrate at the surface. The drift region extends laterally from the current carrying region to the gate structure. The device further includes a buried region of the second conductivity type disposed in the semiconductor substrate below the current carrying region. The buried region is vertically aligned with the current carrying region, and a portion of the semiconductor substrate with the first conductivity type is present between the buried region and the current carrying region.

Abstract: An amplifier circuit including a substrate layer and a plurality of lateral bipolar junction transistors positioned entirely above the substrate. The lateral bipolar junction transistors include a plurality of monolithic emitter-collector regions coplanar to each other. Each of the emitter-collector regions is both an emitter region of a first bipolar junction transistor a collector region of a second bipolar junction transistor from the lateral bipolar junction transistors. Accordingly, the lateral bipolar junction transistors are electrically coupled in series circuit at the emitter-collector regions.

Abstract: Provided are a diode, a junction field effect transistor (JFET), and a semiconductor device that have a top doped region. A dopant concentration gradient of the top doped region at one side is different from the dopant concentration gradient of the top doped region at an opposite side. The top doped region is able to increase a breakdown voltage of the device and decrease an on-state resistance (Ron) of the device.

Abstract: An NLDMOS device that includes a drift region, a P well, and a first PTOP layer and a second PTOP layer formed on the drift region, wherein the first PTOP layer has the same lateral size with the second PTOP layer, the first PTOP layer is spaced from the second PTOP layer in the longitudinal direction and located on the bottom of the second PTOP layer, with the depth of the first PTOP layer less than or equal to that of the bottom of the P well. The present invention also discloses a method for manufacturing the NLDMOS device.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having a first region and a second region; a first fin feature formed on the substrate within the first region; and a second fin feature formed on the substrate within the second region. The first fin feature includes a first semiconductor feature of a first semiconductor material formed on a dielectric feature that is an oxide of a second semiconductor material. The second fin feature includes a second semiconductor feature of the first semiconductor material formed on a third semiconductor feature of the second semiconductor material.

Abstract: A method for fabricating a LDMOS device in a well region of a semiconductor substrate, including: etching a polysilicon layer above the well region through a window for a body region; and forming spacers at side walls of the polysilicon layer, to define positions of source regions in the well region.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

Abstract: According to the present invention, a semiconductor device includes a transistor provided in a first substrate, a gate pad of the transistor, a conductive bump provided on the gate pad, a second substrate provided above the first substrate, a first electrode passing through from a first face to a second face of the second substrate and connected with the conductive bump on the second face side, a resistor connected to the first face side of the first electrode with its one end and connected to an input terminal with the other end and a second electrode provided adjacent to the first electrode on the first face and connected to the input terminal without interposing the resistor, wherein a gate leakage current of the transistor flows from the first electrode to the input terminal through a base material of the second substrate and the second electrode.

Abstract: A MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the semiconductor substrate and the epitaxial layer. In a p-type body layer provided in a surface portion of the epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the epitaxial layer in spaced relation from the body layer. An n-type drain layer is provided in a surface portion of the epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the epitaxial layer between the drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer.

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

Abstract: Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating vertical FET devices with reduced contact resistance. For example, a semiconductor device includes a vertical FET device formed on a substrate, and a vertical source/drain contact. The vertical FET device comprises a first source/drain region disposed on a buried insulating layer of the substrate. The first source/drain region comprises an upper surface, sidewall surfaces, and a bottom surface that contacts the buried insulating layer. The vertical source/drain contact is disposed adjacent to the vertical FET device and contacts at least one sidewall surface of the first source/drain region. The vertical source/drain contact comprises an extended portion which is disposed between the first source/drain region and the buried insulating layer and in contact with at least a portion of the bottom surface of the first source/drain region.

Abstract: A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

Abstract: Methods of forming a semiconductor fin and methods for controlling dopant diffusion to a semiconductor fin are disclosed herein. The methods provide alternative ways to incorporate a carbon dopant into the fin to later control out-diffusion of dopants from a dopant-including epitaxial layer. One method includes depositing a carbon-containing layer over a portion of the fin adjacent to the gate and annealing to diffuse carbon from the carbon-containing layer into at least the portion of the semiconductor fin. This method can be applied to SOI or bulk semiconductor substrates. Another method includes epitaxially growing a carbon dopant containing semiconductor layer for later use in forming the fin.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor substrate, and a current carrying region (e.g., a drain region of an LDMOS transistor) is disposed in the semiconductor substrate at the surface. The device further includes a drift region of a second, opposite conductivity type disposed in the semiconductor substrate at the surface. The drift region extends laterally from the current carrying region to the gate structure. The device further includes a buried region of the second conductivity type disposed in the semiconductor substrate below the current carrying region. The buried region is vertically aligned with the current carrying region, and a portion of the semiconductor substrate with the first conductivity type is present between the buried region and the current carrying region.

Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract: In one embodiment, an IGBT is formed to include a plurality of termination trenches in a termination region of the IGBT. An embodiment may include that one end of one or more termination trenches may be exposed on one surface of the semiconductor device.