Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.

Abstract: To provide a semiconductor integrated circuit device with a reduced noise at a low cost in a semiconductor integrated circuit composed of an MOSFET and adapted to operate, in particular, through DC drive or low-frequency drive. The semiconductor integrated circuit device is configured, in which a surface channel P-type MOSFET (101) and a buried channel N-type MOSFET (100) constitute a complementary MOS transistor with a P+ type gate electrode.

Abstract: An isolated high voltage p-type DMOS transistor comprises a layer of p-type semiconductor material in which a first n-well is disposed. A first annular p-type region is disposed in the first n-well. A first annular shallow trench isolation region is spaced apart from the first annular p-type region. An annular p-well region is spaced apart from the first shallow trench isolation region. An inner perimeter of the annular p-well region is disposed outside of the first annular p-type region. A second annular p-type region is disposed in the p-well. An annular gate has an inner perimeter aligned with the outer perimeter of the first annular p-type region and an outer perimeter disposed over the first shallow trench isolation region. A second annular n-well region is disposed outside of a second annular shallow trench isolation region. The second annular shallow trench isolation region is disposed outside of the annular p-well region.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A liquid-crystal electro-optical device capable of compensating for the operation of any malfunctioning one of TFTs (thin-film transistors) existing within the device if such a malfunction occurs. Plural complementary TFT configurations are provided per pixel electrode. Each complementary TFT configuration consists of at least one p-channel TFT and at least one n-channel TFT. The input and output terminals of the plural complementary TFT configurations are connected in series. One of the input and output terminals is connected to the pixel electrode, while the other is connected to a first signal line. All the gate electrodes of the p-channel and n-channel TFTs included in said plural complementary TFT configurations are connected to a second signal line.

Abstract: A circuit configuration for load-relieved switching has a bridge circuit with at least two controllable power switches, whose controlled paths are arranged in series with one another and between a first and a second supply potential. The circuit configuration has a drive circuit for driving the power switches, and an inductive element that is connected to output terminals of the bridge circuit. At least one power switch is designed as a field-effect-controllable, integrated transistor in accordance with the principle of charge carrier compensation or at least one power switch has deep pn junctions.

Abstract: A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide layer. The hard masking layer includes a full thickness portion and a thinner portion. The polysilicon layer below the full thickness portion is lightly doped forming a high resistance region. Below the thinner portion the polysilicon layer is heavily doped forming a low resistance region. However, in spite of the differences in resistance, the high resistance region and the low resistance region have the same thickness.

Abstract: On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.

Abstract: A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

Abstract: A vertical voltage-controlled bidirectional monolithic switch formed between the upper and lower surfaces of a semiconductor substrate surrounded with a peripheral wall, including: a first multiple-cell vertical IGBT transistor extending between a cathode formed on the upper surface side and an anode formed on the lower surface side; and a second multiple-cell vertical IGBT transistor extending between a cathode formed on the lower surface side and an anode formed on the upper surface side, in which the cells of each transistor are arranged so that portions of the cells of a transistor are active upon operation of the other transistor.

Abstract: A dynamic semiconductor memory device includes memory cells each having a one-transistor/one-capacitor. The memory cells are arranged at their respective intersections of bit lines and word lines. Bit-line precharge circuits are provided at bit line pairs, respectively, to precharge and equalize the bit line pairs. An output potential of a plate potential generator is applied to the power supply terminals of the bit-line precharge circuits. The memory cells have a plurality of capacitors. A plate electrode of the capacitors are connected in common. An insulation film is formed on the plate electrode and a wiring layer is formed on the insulation film. The wiring layer is electrically connected to the plate electrode through a via hole formed in the insulation film and connected in common to the power supply terminals of the bit-line precharge circuits through a contact hole formed in the insulation film, thereby transmitting a potential in proportion to variations in plate potential.

Abstract: A trench DMOS transistor structure is provided that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type. The plurality of individual DMOS transistor cells is dividable into peripheral transistor cells and interior transistor cells. Each of the individual transistor cells includes a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. A conductive electrode is located in the trench, which overlies the insulating layer. Interior transistor cells, but not the peripheral transistor cells, each further include a source region of the first conductivity type in the body region adjacent to the trench.

Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a non-power enhanced metal oxide semiconductor (non-PEMOS) device having first source/drain regions located in a semiconductor substrate, wherein the first source/drain regions include a first dopant profile. The semiconductor device further includes a power enhanced metal oxide semiconductor (PEMOS) device located adjacent the non-PEMOS device and having second source/drain regions located in the semiconductor substrate, wherein the second source/drain regions include the first dopant profile.

Abstract: An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Abstract: A technique for supplying drive voltage to the gate of a high-side depletion-mode N-channel MOS-device for high-side switches or any circuit with a depletion-mode N-channel MOS-device with its source at a voltage above local ground.

Abstract: Ion implantation is conducted using contact holes of a MOS transistor as.a mask to form high concentration diffusion regions, whereby a MOS transistor having a medium withstand voltage structure is provided, in which a high drain withstand voltage, a small capacitance between a source/drain region and a gate electrode, and a high junction withstand voltage between a source/drain region and a channel stop region under a field oxide film are obtained, and the drain withstand voltage can be controlled. Low impurity concentration source and drain regions of a second conductivity type are formed in a semiconductor substrate surrounded by a field oxide film and a gate electrode. An interlayer insulating film is formed thereover for electrically insulating a gate electrode and the source and drain regions. A wiring layer is formed on the interlayer insulating film.

Abstract: A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: In a semiconductor device having high voltage resistance and low ON voltage characteristics, charge-storage regions (insulation layer) are formed in a drift region. Formed above the drift region are a channel region, an emitter region, trench-type gate electrodes, and an emitter electrode. Strips of the insulation layer extend in a direction intersecting a direction of extension of the gate electrodes, and form a stripe pattern. The insulation layer curbs extraction of holes into the channel region. Openings in the stripe pattern of the insulation layer form depletion layers.

Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

Abstract: A semiconductor device, full bridge converter employing the same, and methods of fabrication thereof are provided. The device includes a vertical MOSFET having a parasitic body diode at a junction face between a body region and a semiconductor layer thereof. The parasitic body diode is suppressed by having no direct electrical connection to the body region, resulting in the parasitic body diode being open-circuited within the MOSFET. Co-packaged with the MOSFET is a separate bypass diode connected across a source and a drain of the MOSFET. The bypass diode functions to clamp the voltage across the MOSFET without employing the parasitic, electrically isolated body diode of the MOSFET.

Abstract: A semiconductor device has an element region including MOS structure. A p-well region, a connecting impurity diffused region, and an impurity diffused region for guard ring are formed in an n-type semiconductor layer so as to form a well region, The well region has a step defining a higher portion and a lower portion lower than the higher portion so that the impurity diffused region for guard ring is located at the lower portion. The lower portion is located at a periphery of the element region. In this structure, the impurity diffused region for guard ring is completely depleted while the connecting impurity diffused region is partially depleted so that a portion having carriers remains therein while a depletion layer expands in the connecting impurity diffused region before a breakdown due to a reverse bias occurs in the element region.

Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.

Abstract: A semiconductor device with a SOI structure comprises; a SOI substrate having a buried insulating film and a first conductivity type surface semiconductor layer on the buried insulating film; second conductivity type source and drain regions formed in the surface semiconductor layer; and a gate electrode formed over a first conductivity type channel region between the source and drain regions via a gate insulating film, wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer has a first conductivity type high-concentration impurity diffusion region whose first conductivity type impurity concentration is higher than that in a surface of the channel region and which is adjacent to the buried insulating film.

Abstract: The integrated circuit device has a vertical conduction structure in which a region, which contains the base of a bipolar transistor, has zones having different concentrations. The concentrations are lower where the flow of charges is more intense and higher elsewhere. A high gain of the bipolar transistor and a low resistance of the electronic switch in conduction are thus obtained.

Abstract: When a field effect transistor (e.g., an LDMOSFET) saturates, the electrons traveling through the device slow down. This causes a phase shift with respect to electrons that travel through the device when the device is not saturated. By providing a shorter signal path for the electrons during saturation, it is possible to compensate for the slower speed of the electrons so that the electrons will take the same amount of time to travel through the device regardless of whether the device is saturated or not.

Abstract: A semiconductor device having a substrate composed of a DMOS transistor, a complementary MOS (CMOS) transistor and a bipolar junction transistor is disclosed. A highly-doped bottom layer is formed on a lower edge of a body region of the DMOS transistor, a heavily doped bottom layer of a conductivity type opposite to that of the substrate is formed on a lower edge of source and drain regions of the CMOS transistor, and a highly-doped bottom layer of the same conductivity type as that of the substrate is formed on a lower portion of an intrinsic base region of the bipolar junction transistor, to thereby enhance the electrical characteristics of devices.

Abstract: A semiconductor device and a method of modulating the conductivity of a DMOS transistor included in the device utilize photocurrent generated by a photodetector for minority-carrier injection. The injection of minority carriers into the DMOS transistor of the device reduces the on-resistance of the transistor. The semiconductor device may be used in an optocoupling application. In a first embodiment, the semiconductor device includes a lateral DMOS transistor, a minority-carrier injector, and a photodetector. In a preferred embodiment, the semiconductor device is an integrated device, such that the transistor, the injector and the photodetector are collectively formed on a single semiconductive substrate. The photodetector of the device includes at least one electrically isolated photodiode. As an example, the photodetector may include two dielectrically isolated photodiodes. The photodiodes are serially connected between the drain terminal of the transistor and the minority-carrier injector.

Abstract: A method and apparatus for manufacturing an electrostatic discharge protection device. A first gate structure for the electrostatic device is formed. A first lightly doped drain and a second lightly doped drain for the electrostatic discharge protection device is formed. A second gate structure for a data path transistor is formed. A third lightly doped drain and a fourth lightly doped drain for a data path transistor is formed, wherein the first lightly doped drain and the second lightly doped drain have a higher doping level relative to the third lightly doped drain and the fourth lightly doped drain.

Abstract: In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore, the polycrystalline silicon residue is prevented from being left and prevention of electric short circuit is allowed.

Abstract: An emitter-side structure (2) is formed at an upper main surface of a silicon substrate (1), and an n-type buffer layer (3) is formed at a lower main surface thereof. A p-type collector layer (4) is formed in a main surface of the n-type buffer layer (3), and an n-type cathode region (6) is selectively formed in spaced apart relation with the p-type collector layer (4). A collector electrode (5p) of metal is formed in contact with the p-type collector layer (4), and a cathode electrode (5n) of metal is formed in contact with the n-type cathode region (6) and part of the n-type buffer layer (3). A diode (13) serving as a current suppressing device is connected between the cathode electrode (5n) and a collector terminal (c). A power semiconductor device including an IGBT and a free wheeling diode is reduced in size, and prevents device breakdown due to current concentration during the operation of the free wheeling diode incorporated in the IGBT.

Abstract: A vertical MOS semiconductor device in accordance with the present invention is provided with a semiconductor base; and a vertical MOS transistor having a well diffusion layer of a conductive type opposite to that of the semiconductor base, and a source diffusion layer of the same conductive type as that of the semiconductor base; wherein a channel length in a horizontal direction with respect to a main surface of the semiconductor base from a junction of the source diffusion layer to a junction of the well diffusion layer is set such that it is larger than a length at which a punch-through phenomenon takes place between the semiconductor base and the source diffusion layer and at which a minimum resistance value of the well diffusion layer is obtained. This arrangement makes it possible to reduce the size of the entire vertical MOS semiconductor device to 90% as compared with a conventional vertical MOS semiconductor device, without sacrificing a high breakdown voltage characteristic.

Abstract: A lateral conduction MOS structure characterized by reduced source resistance and reduced pitch. The structure includes a semiconductor substrate having an epitaxial semiconductor layer thereon, the substrate and epitaxial layer being of the same conductivity type. The structure further includes a source layer and a drain layer, each layer being of a second conductivity type, and a channel layer disposed between the source layer and the drain layer. The channel layer has an oxide layer and a gate disposed thereon. At least one of a wet anisotropic and a reactive ion etching step is performed to define a trench having a maximum width of about from 4-6 microns and a depth that extends well into the substrate. An electrically conductive via is then formed by deposition of metal into the trench to thereby establish a low resistance path between the source and the substrate ground.

Abstract: A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.

Abstract: An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material. The high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter.

Abstract: An LDMOS transistor formed in an N-type substrate. A polysilicon gate is formed atop the N-type substrate. A P-type well is formed in the N-type substrate extending from the source side to under the polysilicon gate. A N+ source region is formed in the P-type well and adjacent to the polysilicon gate. A N+ drain region is formed in the N-type substrate and in the drain side of the polysilicon gate. Finally, an N-type drift region is formed between the N+ drain region and the polysilicon gate, wherein the N-type drift region does not extend to said polysilicon gate.

Abstract: A gated semiconductor device comprising a substrate defining an active surface area including source regions, and a series of gates formed adjacent and insulated from the source regions. A source electrode contacts the source regions. A termination extends around the periphery of the active surface area, The termination comprises a gate electrode and a layer of conductive material electrically connected between the gate electrode and the gates. The layer of conductive material extends to the source electrode and incorporates a series of regions which are alternately N and P type so as to define a series of breakdown diode junctions distributed around the active surface area and interposed between tie gate electrode and source electrode, In normal operation gate current flows through portions of the conductive layer which do not incorporate diode junctions. In the event that the gate/source voltage exceeds a predetermined level, the diode junctions break down, shorting the gate to the source.

Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

Abstract: Process for fabricating a semiconductor non-volatile memory device arranged in rows and columns in a matrix structure, including a first step of forming active area's parallel lines delimited by field oxide lines using a Shallow Trench Isolation process, a second step of forming matrix rows which extend transversally to the active area lines, a third step of forming common source lines alternated between pairs of the matrix rows. The second step includes a first sub-step of forming first lines in a first polysilicon layer, along the active area lines, a second sub-step of forming an intermediate dielectric layer, a third sub-step of forming second lines in a second polysilicon layer for defining the matrix rows, a fourth sub-step of defining the intermediate dielectric layer, a fifth sub-step of etching the first polysilicon lines.

Abstract: A semiconductor device includes a first semiconductor element and a second semiconductor element, wherein the first semiconductor element of trench structure and the control circuit including the second semiconductor element such as a TFT or a bipolar transistor can be easily integrated by making the device structure such that the source layer of the buried gate electrode of the first semiconductor element and part of the second semiconductor element, such as the emitter or collector region, can be simultaneously formed.

Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

Abstract: A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.

Abstract: A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to define portions of the dielectric layers that will be removed in an etch step to create voids to the surface of the semiconductor substrate. Subsequently, epitaxially growth is employed to form active regions within the voids that were previously formed. Transistors are then formed in and on the active regions and are subsequently interconnected to form an integrated circuit.

Abstract: The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

Abstract: A silicon-on-insulator insulated gate bipolar transistor (SOI-IGBT) has a channel zone of a first conductivity type, at least one cell zone of a second conductivity type, and at least one intermediate zone of the first conductivity type which delimits the SOI-IGBT. The channel zone, the cell zone, and the intermediate zone are disposed in an insulator layer, which is provided on a semiconductor body of the first conductivity type. The channel zone, the cell zone, and the intermediate zone are connected to the semiconductor body via openings provided in the insulator layer. A semiconductor configuration having a CMOS circuit integrated with an SOI-IGBT is also provided.

Abstract: A semiconductor integrated circuit includes an internal clock generating circuit generating an internal clock, and a flip-flop circuit configured so that n latch circuits are cascaded via switch circuits performing switching operations in synchronism with the internal clock where n is an integer equal to or greater than 2. An initialization control circuit is provided so that it applies, after power on, an initialization signal to the flip-flop circuit whereby a first latch circuit among the n latch circuits is initialized. The initialization control circuit causes the internal clock generating circuit to generate the internal clock during a predetermined period so that the second through nth latch circuits are sequentially initialized.

Abstract: A power transistor device, for example a MOSFET or an IGBT, comprises a semiconductor body (10) which accommodates an array (11) of parallel device cells (1a) in which heat is generated in operation of the device. A hot-location temperature sensor (Mh) is located inside the array (11), and a cool-location temperature sensor (Mc) is located outside the array (11). These sensors each comprises at least one sensor cell (1b; 1c) which is of the same transistor type as the device cells (1a). The sensor cells (1b; 1c) have a cellular region structure (12,13,14,15) similar to that of the device cells (1a), but each sensor (Mh; Mc) has a respective output electrode (31; 32) separate from electrodes (22,23,25) of the device cells (1a).

Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

Abstract: The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.