Abstract: A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.

Abstract: A memory integrated circuit which is driven with a low power and reduced the cell area and a method for manufacturing the same. A plurality of active regions having an H-shape with four source regions and common drain region are formed on a semiconductor substrate. Four word lines each having a different source correspondingly pass through each of the four source regions of an active region, thereby forming four transistors driven, independently. These four transistors are designed so as to share one bit line, thereby reducing the driving voltage of the transistor to 1/4 Vcc. With a low power driving source, four transistors and a capacitor are formed on a small area to thereby reduce the cell size to 33% and even more.

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of body stripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion.

Abstract: A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions.

Abstract: A semiconductor nonvolatile memory device capable of lowering an operation voltage such as an erase voltage and capable of lowering costs and a method of production of the same, wherein a thin film transistor acting as the memory transistor is formed with a semiconductor layer 31b having a channel formation region formed on an insulating substrate 10 made of glass or plastic, a charge storing layer 32a formed on the semiconductor layer, a control gate 33a formed above the charge storing layer, and source and drain regions formed connected to the channel formation region.

Abstract: In an IGBT with a current sensing function having a plurality of principal current cells and at least one current sensing cell, a P-type base region of the current sensing cell in a current sensing cell region is formed larger than a P-type base region of the principal current cell in a principal current cell region. The IGBT is so constituted that the influence of temperature characteristic of parasitic resistor between the principal current cells and current sensing cell upon detected current can be eliminated and the same interval between the P-type base regions can be set for all the cells.

Abstract: A field-effect-controllable power semiconductor component, such as a power MOSFET or IGBT, includes a semiconductor body, at least one cell field, a multiplicity of mutually parallel-connected transistor cells disposed in the at least one cell field, and at least two temperature sensors integrated in the semiconductor body and disposed at different locations from each other on the semiconductor body. Thus a temperature gradient between a strongly heated local region of the semiconductor body and one of the temperature sensors is reduced and a response time in the event of an overload is shortened.

Abstract: The formation of a shortage protection region is disclosed. In one embodiment, a method includes three steps. In the first step, a first ion implantation is applied to form lightly doped regions within a semiconductor substrate adjacent to sidewalls of a gate over the substrate. In the second step, two spaces are formed on the substrate, each adjacent to a sidewall of the gate, so that a second ion implantation forms heavily doped regions within the substrate adjacent to the first spacers. In the third step, two additional spacers are formed on the substrate, each overlapping and extending beyond a corresponding spacer previously formed. Thus, a third ion implantation forms lightly doped shortage protection regions within the substrate adjacent to the spacers most recently formed.

Abstract: A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and forming a channel region over the oxygen-rich punchthrough region. The use of an oxygen-rich punchthrough region may, for example, inhibit the diffusion of dopants used in forming the channel region.

Abstract: A monolithic integrated circuit is mounted in a speaker cabinet to drive the voice coil of the speaker. The monolithic integrated circuit may be a class D amplifier and is at least a half bridge or full bridge power MOSFET device. Structures comprise MOS switching devices of the bridge driver and N+ buried layer of the QVDMOS transistors of the bridge circuits.

Abstract: A method of fabricating a field effect transistor (FET) having an asymmetrical spacer formation includes the steps of forming a gate oxide and a gate electrode on a semiconductor material of a first conductivity type. The gate electrode includes a first and second side edges proximate first and second regions, respectively, of the semiconductor material. Ions of a second conductivity type are implanted to form lightly doped regions extending at least between the first side edge and the first region and at least between the second side edge and the second region, respectively. Blanket layers of oxide and nitride are then formed on the gate electrode and the semiconductor material. The nitride layer is patterned and a first sidewall spacer is formed in a remaining portion of the nitride layer proximate the second side edge. A second blanket layer of oxide is then formed on the first oxide layer and first sidewall spacer.

Abstract: A semiconductor memory device is provided which includes: a memory cell portion including at least one gate electrode formed on a semiconductor substrate and a plurality of source/drain regions formed in the semiconductor substrate and extending parallel to each other and perpendicular to the gate electrode, the gate electrode and the plurality of source/drain regions constituting a plurality of first conductivity type channel transistors; and a peripheral circuitry portion including a first conductivity type channel transistor having a gate electrode formed on the semiconductor substrate and source/drain regions; wherein channels of the first conductivity type channel transistors in the memory cell portion each have a higher impurity concentration than a channel of the first conductivity type channel transistor in the peripheral circuitry portion.

Abstract: A semiconductor manufacturing process comprising providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming a conductive gate on an upper surface of the gate dielectric, forming a first pair of spacer structures on the first and second sidewalls of the conductive gate, introducing a first source impurity distribution into the semiconductor substrate, forming a second pair of spacer structures on respective exterior sidewalls on the first pair of spacer structures, and introducing a drain impurity distribution into the detached drain region of the semiconductor substrate. The semiconductor substrate includes a channel region laterally displaced between a first source region and a detached drain region. The conductive gate includes a first and a second sidewall. Exterior sidewalls of the first pair of spacer structures are displaced from the first and second sidewalls of the conductive gate by a source displacement.

Abstract: The present invention discloses a trenched DMOS device supported on a substrate of a first conductivity type including a core cell area which includes at least a trenched DMOS cell having a gate disposed in a trench and a drain region disposed in the substrate, the substrate further includes a termination area which includes at least a channel-stop trench. The trenched DMOS cell includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches in the substrate. The trenched DMOS cell further includes a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface surrounding the source region adjacent the trenches in the substrate. The trenched DMOS device further includes an insulating layer lining the trenches and a conductive material filling the trenches.

Abstract: An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer.

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of bodystripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion.

Abstract: A semiconductor device having an output element which comprises an IGBT, a diode connected to the IGBT in inverse-parallel, and a voltage-detecting section. The voltage-detecting section comprises a MOSFET and an electrode. The MOSFET is connected to the diode, for generating a voltage proportional to the cathode voltage of the diode. The electrode is provided to detect the voltage generated by the MOSFET. The current flowing in the IGBT can be determined from the voltage detected by the electrode. It is therefore possible to monitor the current flowing through the output element, without increasing the power consumption of the semiconductor device.

Abstract: A power IC is provided which facilitates applying a high voltage to the gate electrode of the MOS semiconductor element for the power output of the power IC to break down defects around the gate oxide film in a short time thereby screening the power ICs efficiently. A gate terminal for testing is led out from the gate electrode of the MOS type semiconductor element for the power output of the power and the screening test is conducted by applying a high voltage to the gate terminal for testing. The expected bad influence of the applied high voltage on the control circuit is avoided by the level shift means or the switching means switched off only during the screening test and short-circuited after the test is over.

Abstract: A method of fabricating a semiconductor device containing a HVDMOS transistor and a LVDMOS transistor and the device which includes providing a region of semiconductor material of a first conductivity type and forming a high voltage DMOS transistor disposed in the region. A relatively low voltage DMOS transistor is also disposed in that region and electrically isolated from the high voltage DMOS transistor. The low voltage DMOS transistor has spaced apart source and drain regions disposed in the region of semiconductor material and a back gate region of the first conductivity type disposed in the region of semiconductor material between the source and drain regions. The back gate region is electrically coupled to the region of semiconductor material. The region of semiconductor material includes a surface, the source, drain and back gate regions extending to that surface.

Abstract: A lateral semiconductor device, such as an LIGBT, LMOSFET, lateral bipolar transistor, lateral thyristor, or lateral MOS control thyristor, includes a device area surrounded by an n-type region in an n-channel lateral semiconductor device or by a p-type region in a p-channel lateral semiconductor device. Connecting the n-type region in the n-channel lateral semiconductor device or the p-type region in the p-channel lateral semiconductor device at a same potential as a first main electrode suppresses operation of parasitic transistors, as well as prevents carrier accumulation in isolated regions or a substrate. As a result, a switching loss of the lateral semiconductor device is greatly reduced, a switching speed of the lateral semiconductor device is improved, and a current capacity of the lateral semiconductor device is increased.

Abstract: A depletion mode power MOSFET has a gate electrode formed of material that is refractory, or resistant, to high temperature encountered during device fabrication. A depletion channel region which is formed in a base region of a MOSFET and which interconnects the source and drain regions is formed after a high temperature drive to form the base region, but before a gate oxide and gate and source electrodes are formed at lower temperatures. The depletion channel region is thus subjected to reduced temperatures and grows only slightly in thickness, so that it can be easily depleted. The gate oxide, similarly, is subjected to reduced temperatures, and, particularly when made thin, exhibits high insensitivity to radiation exposure.

Abstract: A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the transistor further includes a large number of identical cells that are connected in parallel with a second electrode and a control electrode formed on the top surface. The power transistor includes at least one additional cell, formed in the semiconductor layer, having the same shape as the identical cells but a smaller lateral size than the identical cells, and a circuit to turn on the power transistor when the additional cell reaches an avalanche mode.

Abstract: A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices.

Abstract: Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve cost savings by simplified device structure and fabrication processes, and also by reducing the required die size. Specifically, in a novel MOSFET device, insulation of mobile ions are achieved by extending the poly gate and metal contacts such that the passivation layer is no longer required and the fabrication process is simplified such that the MOSFET device can be manufactured at a lower price. Furthermore, in another MOSFET device, the gate runner is used to replace the field plate such that the requirement of a field plate as that in a conventional MOSFET device is also eliminated and, by reducing the die size, the cost of manufacture is further reduced.

Abstract: A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.

Abstract: A high current power transistor is provided that comprises a drain region that includes a highly-doped drain region (54) and a lightly-doped drain region (50). The channel region (52) is activated by a gate conductor (32). The channel region separates the lightly-doped drain region (50) from a D-well region (40). A sidewall insulator body (44) is used to form the lightly-doped drain region (50) and the lightly-doped drain region (54). The transistor is formed in an active region (20) which comprises a portion of an n-type epitaxial layer (12) formed outwardly from a p-type substrate (10). The isolation structures (14) and (16) as well as the epitaxial layer (12) provides for a transistor that can be used in both source follower and common source configurations.

Abstract: A semiconductor device including first, second, third and fourth MOSFETs constituting an H bridge circuit. Each of the first and second MOSFETs is a vertical DMOSFET and each of the third and fourth MOSFETs is a lateral DMOSFET having a surface diffusion region formed in a portion of a drain region. The surface diffusion region has a conductivity type opposite that of a source region of the lateral DMOSFET and is electrically connected to the source region. Each of the surface diffusion regions may be made of a part of a channel stop region formed under a field insulator film. Each of the third and fourth MOSFETs may be a lateral DMOSFET having no surface diffusion region. Low on-resistance and small chip size of the device are obtained.

Abstract: A vertical MOSFET, which can control AC current flowing through a device only by the gate voltage, is obtained. On an n.sup.+ silicon layer is formed an n.sup.- silicon layer. Within the n.sup.- silicon layer is formed a p-body region. Within the p-body region is formed an n.sup.+ source region. On top of a substrate are formed a source electrode in contact only with the source region and a base electrode in contact only with the p-body region. The source electrode and the base electrode are connected to each other through a resistance at the outside. On a channel region is formed a gate electrode through a gate oxide film (insulating film). When the above semiconductor device is in the reverse bias conduction, the exciting current is controlled only by the gate voltage by setting the current flowing from a source terminal through the resistance to the base electrode, the p-body region and the n.sup.

Abstract: In integrated structure sensing resistor for a power MOS device consists of a doped region extending from a deep body region of at least one cell of a first plurality of cells, constituting a main power device, to a deep body region of a corresponding cell of a second smaller plurality of cells constituting a current sensing device. The first plurality of cells and the second plurality of cells are formed using trench technology.

Abstract: A vertical field effect transistor comprises a MOSFET cell zone which is formed in a principal surface of an N-type semiconductor substrate and in which a plurality of MOSFET cells are formed and connected in parallel with one another. A gate electrode pad and a source electrode pad are formed in the principal surface of the semiconductor substrate, separately from the MOSFET cell zone. A drain electrode pad is formed on a rear surface of the semiconductor substrate. A plurality of diodes are formed in the principal surface of the semiconductor substrate and arranged to form at least one array of diodes along an outer periphery of the MOSFET cell zone. An N-type region of each of the diodes is formed of the N-type semiconductor substrate itself and a P-type region of each of the diodes is connected to an electrode which is connected to a source electrode of the MOSFET cells.

Abstract: An isolated pilot transistor 100 for a QVDMOS device 10 has a gate and drain region in symmetry with the sources 20 of device 10 and an additional resistance 116 in the drain 118 to compensate for current spreading between the source 120 and the buried layer resistor 132.

Abstract: A semiconductor device having a surge input detecting circuit is provided with the driving circuit for, for example, reversible motor. To prevent MOS power transistors constituting the power driving circuit from their destructive breakdowns (failures), when the surge input detecting circuit block detects the surge voltage input through the driving circuit which exceeds a predetermined voltage, namely, a maximum rated power supply voltage of the power driving circuit, the surge input detecting circuit outputs the signal to turn the MOS power transistors in off-states. These circuit elements are integrally mounted on a semiconductor chip. The surge input detecting circuit block detects such a surge input through a power supply terminal in terms of either of its voltage, its current, or the temperature rise in the semiconductor chip. The breakdown voltage per power transistor can be half the maximum rated power supply voltage.

Abstract: A recording head comprises electrothermal transducers for jetting ink and functional devices for driving these electrothermal transducers, both of which are arranged on a single substrate plate. The functional devices comprise a pair of major electrode regions such as drain and source regions arranged on the substrate plate, a region comprising control electrode region and surrounding one of electrode regions used to be grounded, an insulating layer arranged on the control electrode region and a control electrode arranged on the insulating layer. The control layer alters the semiconductor types of a boundary surface of the control electrode region by applying a control voltage through the insulating layer and as a result a current flow between major electrode regions, source and drain, is controlled.

Abstract: A plurality of minority carriers, which cause a conductivity modulation effect in a semiconductor device, are supplied from a separately disposed minority carrier injection region which is alternately connected to and separated from a drain region. The minority carriers are injected via the minority carrier injection region connected to the drain region during forward biasing. The minority carrier injection is stopped by separating the injection region from the drain region when the turn-off operation begins. This operation reduces the carriers that need to be swept off during a turn-off operation. The turn-off time is shortened in a bipolar semiconductor device, such as an IGBT with a reduced on-voltage, by utilizing the conductivity modulation to reduce switching loss.

Abstract: An FET having a high breakdown voltage comprises a P type semiconductor substrate (5), a plurality of pairs of source regions (S) and drain regions (D) each comprising N.sup.- impurity layers (3) formed in the substrate, gate electrodes (9) each formed through an insulating film over a region interposed between each of the source regions and each of the drain regions, N.sup.+ impurity diffused layers (4) formed, shifted by a constant dimension in the N.sup.- impurity diffused layers, a source terminal (7a) connecting a plurality of source regions and a drain terminal (7b) connecting a plurality of drain regions in the plurality of pairs such that a dimensional error caused by shifting is compensated for.

Abstract: A MOS transistor included in a peripheral circuit of a DRAM has conductive layers for interconnection on respective surfaces of a pair of source.multidot.drain regions. The source.multidot.drain interconnection layers are electrically connected to the source.multidot.drain regions through the conductive layers. One of the pair of conductive layers is formed in the same step as a bit line of a memory cell, by the same material as the bit line. The other one of the pair of conductive layers is formed in the same step as a storage node of a capacitor of the memory cell, by using the same material as the storage node. The pair of conductive layers prevent direct connection between the source.multidot.drain interconnection layer and the source.multidot.drain regions, so that reduction in size of the source.multidot.drain regions can be realized.

Abstract: A method of forming a retarded double diffused drain structure, and the resultant retarded double diffused drain structure, for a field effect transistor are described. A silicon substrate with field isolation regions and a gate structure is provided. A layer of photoresist is formed on the field isolation region, the silicon substrate, and the gate structure. The photoresist is patterned to expose the silicon substrate and the gate structure, but covers an area of the silicon substrate that is offset from the field isolation regions. A first ion implant is performed in a vertical direction in exposed regions of the silicon substrate, with suitable dopant having a high doping concentration. The photoresist is removed. A second ion implant is performed in a vertical direction in the silicon substrate, with suitable dopant with higher doping concentration than the first ion implant, in regions between the field isolation regions and the gate structure. The substrate is heated to drive in both the dopants.

Abstract: A power semiconductor device having a current detecting function comprising a detection part that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part.

Abstract: A cellular insulated gate bipolar transistor ("IGBT") device of the lateral conduction type employs increased concentration in the active region between spaced bases to a depth greater than the depth of the base regions. The implant dose which is the source of the increased concentration is about 3.5.times.10.sup.12 atoms per centimeter squared and is driven for about 10 hours at 1175.degree. C. Lifetime is reduced by an increased radiation dose to reduce switching loss without reducing breakdown voltage or increasing forward voltage drop above previous levels. The increased concentration region permits a reduction in the spacing between bases and provides a region of low localized bipolar gain, increasing the device latch current. The avalanche energy which the device can successfully absorb while turning off an inductive load is significantly increased. The very deep increased conduction region is formed before the body and source regions in a novel process for making the new junction pattern.

Abstract: A lateral double-diffused MOSFET has a semiconductor substrate, a drain region formed on the substrate, a gate insulation film formed on the drain region, a gate electrode formed on the gate insulation film, source and drain openings formed through the gate electrode, a first conductive region formed under the drain region, a source electrode formed on the source openings, a drain electrode formed on the drain openings, and second conductive regions for connecting the drain electrode to the first conductive region. The source and drain openings are cyclically arranged so that at least two rows of source openings are arranged between adjacent drain openings, to reduce the ON resistance of the MOSFET.

Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate.

Abstract: An object of the present invention is to provide an LD-MOS transistor with a reduced device real estate and high breakdown strength. An extended drain region doped with phosphorus is formed in contact with an underside of an insulation layer and a drain diffusion region, respectively. The insulation layer is deposited over a conductive gate layer and a drain diffusion region, respectively.

Abstract: In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.

Abstract: A semiconductor device capable of stably operating even at a low voltage, includes: a semiconductor substrate having a surface region of a first conductivity type; a conductive film directly formed on a surface of the surface region at an area thereof, the conductive film containing impurities of a second conductivity type opposite to the first conductivity type; an oozed diffusion region of the second conductivity type formed by diffusion of the impurities in the conductive film into the substrate, the oozed diffusion region being formed at an area contiguous to the conductive film in the surface region; a low resistivity region of the second conductivity type extending from an area adjacent to the conductive film in the surface region and overlapping the conductive film; and a DDD structure transistor formed on another region of the surface region, wherein a length of a portion of the low resistivity region overlapping the conductive film is substantially the same as a length of a portion of the deep source

Abstract: A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively high resistivity epitaxially formed region. The epitaxially formed region then receives a drain region which is on the same surface as the channels. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

Abstract: A polysilicon gate resistor consists of a plurality of parallel polysilicon strips extending from gate finger to gate pad. Different numbers of parallel strips can be selected during manufacture by using different contact masks.

Abstract: A large sense voltage is produced by the semiconductor device of the present invention. The semiconductor device, utilizing current mirror techniques, is comprised of a power MOSFET having a plurality of power cells and a plurality of sense cells formed in a semiconductor epitaxial layer. The large sense voltage is provided by isolating and separating the plurality of power cells from the plurality of sense cells by at least the thickness of the semiconductor epitaxial layer. Isolation can be provided by forming a plurality of inactive cells or an elongated cell between the plurality of power cells and the plurality of sense cells. In addition, high voltage capabilities can be maintained by including a partially active region adjacent the power cells to provide for good termination.

Abstract: Mutual interference is reduced between a main cell portion and a sensing cell portion for detecting the current flowing through the main cell portion of a vertical MOS semiconductor device, and accuracy and reliability of overcurrent detection are improved. In the device, well regions of (p) type are formed between the main and sensing cell portions for capturing the minority carriers. Breakdown of the gate oxide film caused by an open emitter electrode of the sensing cell portion is prevented by forming the (p) type well regions with ring shapes, by spacing the (p) type well regions by 5 to 20 .mu.m, and by adjusting the isolation withstand voltage between the main and sensing cell portions below the withstand voltage of the gate oxide film. A voltage spike is minimized by narrowing the overlap of the detecting and gate electrodes for reduced capacitance between these electrodes.

Abstract: A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the source, channel and drain and that which has a sidewall at which a gate dielectric and a gate electrode are arranged. The complementary MOS transistors connected in parallel with one another are realized in a common layer sequence of the source, channel and drain. The layer sequences that form the series-connected transistors are arranged above one another. The circuit structure is manufactured by epitaxal definition of the layer sequences, such as by molecular beam epitaxy.

Abstract: A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the transistor further includes a large number of identical cells that are connected in parallel with a second electrode and a control electrode formed on the top surface. The power transistor includes at least one additional cell, formed in the semiconductor layer, having the same shape as the identical cells but a smaller lateral size than the identical cells, and a circuit to turn on the power transistor when the additional cell reaches an avalanche mode.